taskit Stamp9G45 Use and care manual

Stamp9G45
Technical Reference

Stamp9G45
Stamp9G45: Technical Reference
Copyright © 2011 taskit GmbH
All rights to this documentation and to the product(s) described herein are reserved by taskit GmbH.
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This document was generated on 2014-07-09T15:28:29+02:00.

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Table of Contents
1. Introduction ................................................................................................................. 1
2. Scope ........................................................................................................................... 2
3. Overview of Technical Characteristics ........................................................................ 3
3.1. CPU .................................................................................................................... 3
3.2. Memory ............................................................................................................. 3
3.3. Interfaces and external signals ......................................................................... 3
3.4. Miscellaneous .................................................................................................... 4
3.5. Power Supply .................................................................................................... 4
3.6. Dimensions ........................................................................................................ 4
4. Hardware Description ................................................................................................. 5
4.1. Mechanics .......................................................................................................... 5
4.2. AT91SAM9G45 Processor Core ......................................................................... 5
4.3. Memory ............................................................................................................. 5
4.3.1. NAND Flash ............................................................................................ 5
4.3.2. LPDDR-SDRAM ........................................................................................ 6
4.3.3. EEPROM .................................................................................................. 6
4.3.4. SRAM ....................................................................................................... 6
4.4. Bus Matrix ......................................................................................................... 7
4.5. Advanced Interrupt Controller (AIC) ................................................................ 7
4.6. Battery Backup .................................................................................................. 8
4.7. Reset Controller (RSTC) ................................................................................... 8
4.8. Serial Number ................................................................................................... 8
4.9. Peripheral Input/Output Controller (PIO) ......................................................... 8
4.10. Clock Generation ............................................................................................. 9
4.10.1. Processor Clocks ................................................................................... 9
4.10.2. Programmable Clocks ......................................................................... 10
4.11. Power Management Controller (PMC) .......................................................... 10
4.11.1. Function ............................................................................................... 10
4.11.2. Power Management ............................................................................. 11
4.12. Real-time Timer (RTT) ................................................................................... 11
4.13. Timer Counter (TC) ....................................................................................... 12
4.14. Periodic Interval Timer (PIT) ........................................................................ 12
4.15. Watchdog Timer ............................................................................................ 12
4.16. Real-time Clock (RTC) ................................................................................... 12
4.17. True Random Number Generator (TRNG) .................................................... 12
4.18. Peripheral DMA Controller (PDC) ................................................................. 13
4.19. Debug Unit (DBGU) ...................................................................................... 13
4.20. JTAG Unit ...................................................................................................... 13
4.21. Two-wire Interface (TWI) .............................................................................. 14
4.22. Multimedia Card Interface (MCI) ................................................................. 14
4.23. USB Host Port (UHP) .................................................................................... 14
4.24. USB Device Port (UDP) ................................................................................. 15
4.25. Ethernet MAC (EMAC) .................................................................................. 15
4.26. Universal Sychronous Asynchronous Receiver and Transmitter (USART)
.................................................................................................................................. 15
4.27. Synchronous Peripheral Interface (SPI) ........................................................ 17
4.28. Synchronous Serial Controller (SSC) ............................................................ 17

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4.29. AC97 Controller (AC97C) .............................................................................. 18
4.30. Image Sensor Interface (ISI) ......................................................................... 18
4.31. LCD controller ............................................................................................... 18
4.31.1. LCDC Initialisation and LCD Power Sequencing ................................. 19
4.31.2. LCDC Frame Buffer ............................................................................ 19
4.32. Touch Screen ADC Controller (TSADCC) ...................................................... 20
5. Design Considerations ............................................................................................... 21
5.1. Ethernet Controller (EMAC) ........................................................................... 21
5.2. USB .................................................................................................................. 21
5.2.1. USB Host Controller (UHP) .................................................................. 21
5.2.2. USB Device Controller (UDP) ............................................................... 22
5.3. Memory Bus .................................................................................................... 22
A. Peripheral Color Codes ............................................................................................. 25
B. Peripheral Identifiers ................................................................................................ 26
C. Address Map (Physical Address Space) .................................................................... 27
D. Stamp9G45 Pin Assignment ..................................................................................... 29
E. Stamp9G45 Electrical Characteristics ...................................................................... 32
F. Stamp9G45 Clock Characteristics ............................................................................. 33
G. Stamp9G45 Environmental Ratings .......................................................................... 34
H. Stamp9G45 Dimensions ........................................................................................... 35
I. Starterkit Schematics ................................................................................................ 36

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List of Figures
5.1. Buffered Memory Bus (PIOC) 1.8V - 3.3V ............................................................. 24
H.1. Stamp9G45 Dimensions ......................................................................................... 35
I.1. Starterkit FX8 ......................................................................................................... 36
I.2. Starterkit Buffer ...................................................................................................... 37
I.3. Starterkit Memory .................................................................................................. 38
I.4. Starterkit Serial ...................................................................................................... 39
I.5. Starterkit Ethernet .................................................................................................. 40
I.6. Starterkit USB, Power ............................................................................................ 41

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List of Tables
4.1. Bus Matrix Masters .................................................................................................. 7
4.2. Bus Matrix Slaves .................................................................................................... 7
4.3. AT91SAM9G45 Clocks ............................................................................................ 10
4.4. AC97 I/O Lines ....................................................................................................... 18
4.5. LCDC palette entry ................................................................................................ 19
4.6. LCDC 24 bit memory organization ........................................................................ 19
B.1. Peripheral Identifiers ............................................................................................. 26
C.1. Physical Address Space ......................................................................................... 27
D.1. Pin Assignment BUS Interface .............................................................................. 29
D.2. Pin Assignment IO Interface .................................................................................. 30
E.1. Electrical Characteristics ....................................................................................... 32
F.1. Clock Characteristics .............................................................................................. 33
G.1. Environmental Ratings .......................................................................................... 34

Introduction
1
1. Introduction
The Stamp9G45 is intended to be used as a small size "intelligent" CPU module as well
as a universal Linux CPU card. It can be used anywhere where restricted energy and
space requirements play a role. The design of the Stamp9G45 is limited to the processors
core needs like DDRAM and Flash, thus giving the customer a wide-ranged choice of
configurations of the peripherals and environment. Featuring an integrated LCD/TFT
and touch controller applications with graphical needs can be realized cost-efficient and
individually.
The Stamp9G45 has all the necessary interfaces to support a huge variety of peripheral
devices. Equipped with a 16-Bit parallel bus it gives fast access to a number of chips and
additional devices.
The ARM architecture as a modern and widely supported processor architecture is
currently the platform of choice for medium performance embedded devices. Almost all
major processor manufacturers have ARM products in their portfolio.
The availability of the widespread operating system "Linux" for the ARM platform opens
access to a broad range of software, including tools, drivers, and software libraries.
Programs written for ARM can easily be employed on the PC platform for testing and
debugging.
Examples of actual or potential applications are: protocol converters, measuring and test
equipment, data-logging, as well as simple or more complex control and automation tasks.

Scope
2
2. Scope
This document describes the most important hardware features of the Stamp9G45. It
includes all informations necessary to develop a customer specific hardware for the
Stamp9G45. The Operating System Linux is described in a further document.
The manual comprises only a brief description of the AT91SAM9G45 processor, as this
is already described in depth in the manual of the manufacturer Atmel. Descriptions of
the ARM core ARM926EJ‑S are available from Atmel and also at http://www.arm.com. It
is much recommended to have a look at these documents for a thorough understanding
of the processor and its integrated peripherals.

Overview of Technical Characteristics
3
3. Overview of Technical Characteristics
3.1. CPU
Atmel AT91SAM9G45 Embedded Processor featuring an ARM926EJ-S™ ARM® Thumb®
Core
• CPU Clock 400 MHz
• 32KB Instruction Cache
• 32KB Data Cache
• Memory Management Unit (MMU)
• 3.3V Supply Voltage, 1.8V Memory Bus Voltage, 1.0V Core Voltage
3.2. Memory
• 128 MB NAND flash memory (optional up to 1GB)
• 128 MB LPDDR-SDRAM (optional up to 512 MB)
• 64 KB SRAM
• 128 Bytes EEPROM
• Onboard Micro-SD Card Slot
3.3. Interfaces and external signals
• 2x 100-pin fine-pitch low-profile Connectors (Hirose FX8)
• Ethernet 10/100 Mbit MAC
• USB 2.0 High Speed Host
• USB 2.0 Full Speed OTG (USB-On-the-Go)
• USB 2.0 High Speed Device
• Four USARTs
• One UART
• One Synchronous Serial Controller (SSC, I2S)
• One Serial Peripheral Interface (SPI)
• Two Two Wire Interface (TWI, I2C)
• One High Speed MultiMedia Card Interface

Overview of Technical Characteristics
4
• Three PWM
• 4-wire Touch Controller
• AC'97 Sound Controller
• LCD/TFT Controller (1280 x 860 pixels)
• JTAG debug port
• Digital Ports - up to 100 available
• Control Signals: IRQs, BMS, SHDN, WKUP
• Two Programmable Clocks
• Image Sensor Interface
• Analog-to-Digital Converter
• 16-Bit parallel CPU-Bus
Some of the various functions are realized by multiplexing connector pins; therefore not
all functions may be used at the same time (see AppendixD, Stamp9G45 Pin Assignment)).
3.4. Miscellaneous
• Three 16-Bit Timer/Counter
• True Random Number Generator
• Real Time Timer (RTT), with battery backup support
• RTC
• Periodic Interval Timer (PIT)
• Watchdog Timer (WDT)
• Unique Hardware Serial Number
3.5. Power Supply
• 3.3V power supply
• 3V backup power supply, e.g. from a lithium battery
3.6. Dimensions
• Dimensions: 53.6x38x6 mmm (WxDxH)

Hardware Description
5
4. Hardware Description
4.1. Mechanics
The Stamp9G45 was designed as a flexible CPU-Module, which can be connected to base
boards via 2x 100-pin fine pitch low profile Hirose ® FX8 connectors
The size of the Stamp9G45's PCB is only 53.6x38x6.0 mm fitting it in even the smallest
design. While having implemented the sensible CPU, DDRAM and Flash design it still
exports almost all possible CPU-Pins on it's connectors to allow a flexible design on base
boards
The Stamp9G45 has an on-board Micro SD-Card slot, thus supporting even large memories
needs in its compact design
4.2. AT91SAM9G45 Processor Core
The AT91SAM9G45 runs at 400 MHz with a memory bus frequency of 132 MHz.
Here are some of the most important features of the SAM9G45 ARM926EJ-S core:
• 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Write Buffer
• Two 32 Bit Data Bus
• ARM v4 and v5 Memory Management Unit (MMU)
• ARM v5 32-bit Instruction Set, ARM Thumb 16-bit Instruction Set supported
• DSP Instruction Extensions
• ARM Jazelle® Technology for Java® Acceleration
• EmbeddedICE™ Debug Communication Channel Support
Some of these features - like Jazelle - are currently not supported by the operating system
of the product.
4.3. Memory
The Stamp9G45 is equipped with two 32-Bit external bus interfaces, EBI0 and EBI1. Only a
16-Bit bus of EBI0 is exported on the interface connectors of the Stamp9G45. The memory
bus voltage is 1.8 V and runs at 133 MHz. The memory bus voltage is different from normal
operating voltage, which is 3.3 V. This has to be considered, when designing additional
peripherals connected to the memory bus. Eventually buffer chips are necessary.
4.3.1. NAND Flash
The Stamp9G45 is equipped with a 128 MB NAND flash with 100000 erase and write
cycles.It is organized in 128KB blocks. Customer specific adaptations are possible up
to 1 GB on-board NAND flash. It is connected to chip select three (NCS3) of the
microcontroller.

Hardware Description
6
NAND flash has a different organisation of transistors than the commonly used NOR flash.
While it allows a much higher density and thus an increase in storage capacity, there are
some differences which need to be kept in mind.
Typically, NAND flash is organized in pages and blocks, similar to hard disks. Pages are
512, 2048 or 4096 bytes in size, typical block sizes are 16, 128, 256 or 512 KB. Reading and
programming are performed on a page basis. Programming can only be done sequently
in one block.
Additionally, NAND flash requires bad block management, either by the driver software
or by a separate controller chip. Most NAND devices are shipped with bad blocks. These
are identified and marked according to a specified bad block strategy. Further bad blocks
may be detected during runtime. They are detected via an ECC (error correcting code). If
a bad block is detected, the data is written to a different, good block, and the bad block
table is updated. So the overall memory capacity gradually shrinks as more and more
blocks are marked bad.
This error detection is done by software like U-boot and Linux. Additionally, NAND flash is
subject to a limited number of write and erase cycles. These are typically 100.000 cycles
per block. So it is highly recomended to use wear levelling filesystems.
4.3.2. LPDDR-SDRAM
The Stamp9G45 is equipped with 128MB LPDDR-SDRAM (Low power DDR-SDRAM).
Customer specific adaptations allow configurations up to 512MB. In 128MB and 256MB
configurations, the LPDDR-SDRAM is connected to EBI0. The external Bus is not affected.
In 512MB configuration 256MB of the LPDDR-SDRAM are connected to chip select one
(NCS1) of the micrcontroller's EBI1.
DDR-SDRAM allows random access to any of its memory area and is volatile memory.
DDR-SDRAM (Double Data Rate) takes over data at the rising and falling edge of a clock
pulse, thus achieving almost twice the bandwidth than a similar connected SDRAM. It has
a synchronous interface, that means it waits for a clock signal before responding to control
inputs and is therefore synchronized with the CPU bus. The clock is used to drive a final
state machine in the chip, which allows to accept new instructions, before the previous
one has finished executing.
4.3.3. EEPROM
The Stamp9G45 is equipped with a 128 bytes EEPROM, connected to the Dallas™ 1 wire
bus.
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is
non-volatile memory, which is used to store small amounts of data like calibration or
configuration data. EEPROMS are byte-wise erasable, thus allowing true random access.
4.3.4. SRAM
The Stamp9G45's microcontroller is equipped with 64 KB internal SRAM. The internal
SRAM can be accessed in one bus cycle and may be used for time critical sections of code
or interrupt handlers.

Hardware Description
7
4.4. Bus Matrix
The bus matrix of AT91SAM-controllers allows many master and slave devices to be
connected independently of each other. Each master has a decoder and can be defined
specially for each master. This allows concurrent access of masters to their slaves
(provided the slave is available).
The bus matrix is thus the bridge between external devices connected to the EBI, the
microcontroller's embedded peripherals and the CPU core.
Master 0 ARM926™ Instruction
Master 1 ARM926™ Data
Master 2 PDC
Master 3 USB HOST OHCI
Master 4 DMA
Master 5 DMA
Master 6 ISI Controller DMA
Master 7 LCD DMA
Master 8 Ethernet MAC DMA
Master 9 USB Device High Speed DMA
Master 10 USB Host High Speed EHCI DMA
Master 11 Reserved
Table4.1.Bus Matrix Masters
Slave 0 Internal SRAM
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
Slave 1
Reserved
Slave 2 DDR Port 0
Slave 3 DDR Port 1
Slave 4 DDR Port 2
Slave 5 DDR Port 3
Slave 6 External Bus Interface
Slave 7 Internal Peripherals
Table4.2.Bus Matrix Slaves
4.5. Advanced Interrupt Controller (AIC)
The core features of the Advanced Interrupt Controller are:
• 32 Internal or External Interrupt Sources
• 8-level Priority Controller

Hardware Description
8
• Level Sensitive or Edge Triggered
• Programmable Polarity for External Sources
Moreover, all PIO lines can be used to generate a PIO interrupt. However, the PIO lines
can only generate level change interrupts, that is, positive as well as negative edges will
generate an interrupt. The PIO interrupt itself (PIO to AIC line) is usually programmed to
be level-sensitive. Otherwise interrupts will be lost if multiple PIO lines source an interrupt
simultaneously.
On the Stamp9G45 only GPIO interrupts are available. The list of peripheral identifiers,
which are used to program the AIC can be found in TableB.1, “Peripheral Identifiers”
4.6. Battery Backup
The following parts of the AT91SAM9G45 Processor can be backed-up by a battery:
• Slow Clock Oscillator
• Real Time Timer
• Reset Controller
• Shutdown Controller
• RTC
• General Purpose Backup Registers
It is recommended to always use a backup power supply (normally a battery) in order to
speed up the boot-up time and to avoid reset problems.
4.7. Reset Controller (RSTC)
The embedded microcontroller has an integrated Reset Controller which samples the
backup and the core voltage. The presence of a backup voltage (VDDBU) when the card
is powered down speeds up the boot time of the microcontroller.
4.8. Serial Number
Every Stamp9G45 has a unique 48-bit hardware serial number chip which can be used
by application software. The chip is a Dallas® one-wire-chip. A Linux driver is provided.
Additionally it functions as the 128 Byte EEPROM.
4.9. Peripheral Input/Output Controller (PIO)
The Stamp9G45 has a maximum of 105 freely programmable digital I/O ports on its
connectors. These pins are also used by other peripheral devices.
The Parallel Input/Output Controller(PIO) manages up to 32 programmable I/O ports. Each
I/O port is associated with a bit number in the 32 bit register of the user interface. Each I/O

Hardware Description
9
port may be configured for general purpose I/O or assigned to a function of an integrated
peripheral device. In doing so multiplexing with multiple integrated devices is possible.
That means a pin may be used as GPIO or only as one of the peripheral functions. The
PIO Controller also features a synchronous output providing up to 32 bits of data output
in a single write operation.
The following characteristics are individually configurable for each PIO pin:
• PIO enable
• Peripheral enable
• Output enable
• Output level
• Write Enable
• Level change interrupt
• Glitch filter: pulses that are lower than a half clock cycle are ignored
• Open-drain outputs
• Pull-up resistor
All configurations as well as the pin status can be read back by using the appropriate
status register. Multiple pins of each PIO can also be written simultaneously by using the
synchronous output register.
For interrupt handling, the PIO Controllers are considered as user peripherals. This means
that the PIO Controller interrupt lines are connected among the interrupt sources 2 to
31. Refer to the PIO Controller peripheral identifier Table B.1, “Peripheral Identifiers”
to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller
interrupt can be generated only if the PIO Controller clock is enabled.
A number of the PIO signals might be used internally on the module. Care has to be taken
when accessing the PIO registers in order not to change the settings of these internal
signals, otherwise a system crash is likely to happen.
4.10. Clock Generation
4.10.1. Processor Clocks
The AT91SAM9G45 has no PLLB, but provides the 480 MHz USB Clock via a UPLL.
The CPU generates its clock signals based on two crystal oscillators: One slow clock
(SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 18.432
MHz. The slow clock oscillator also serves as the time base for the real time timer. It draws
a minimum of current (a few micro-Amps) and can therefore be backeded up by a small
lithium battery when the board is powererd down.

Hardware Description
10
From the main clock oscillator, the CPU generates two further clocks by using two PLLs.
PLLA provides the processor clock (PCK) and the master clock (MCK). PLLB typically
provides the 48 MHz USB clock and is normally used only for this purpose. The clocks of
most peripherals are derived from MCK. These include EBI, USART, SPI, TWI, SSC, PIT
and TC.
Some peripherals like the programmable clocks and the timer counters (TC) can also run
on SLCK. The real time timer (RTT) always runs on SLCK.
Clock Frequency Source
PCK (Processor Clock) 800 MHz PLLA
MCK (Master Clock) 133 MHz PCK/3
USB Clock 480 MHz UPLL
Slow Clock 32.768 KHz Slow Clock Oscillator
Table4.3.AT91SAM9G45 Clocks
4.10.2. Programmable Clocks
The programmable clocks can be individually programmed to derive their input from
SLCK, PLLA, PLLB and Main Clock. Each PCK has a divider of 2, 4, 8, 16, 32 or 64.
The Stamp9G45 features two programmable clocks PCK0, PCK1.
4.11. Power Management Controller (PMC)
4.11.1. Function
The PMC has a Peripheral Clock register which allows to individually enable or disable the
clocks of all integrated peripherals by using their "Peripheral Identifier" (see TableB.1,
“Peripheral Identifiers”). The System Clock register allows to enable or disable each of
the following clocks individually:
• Processor Clock
• ISI Clock
• USB Host Clock (common for both channels)
• USB Device Clock
• Programmable Clocks
The PMC status register provides "Clock Ready" or, respectively, "PLL Lock" status bits
for each of these clocks. An interrupt is generated when any of these bits changes from
0 to 1. The PMC provides status flags for the
• Main Oscillator
• Master Clock
• PLLA

Hardware Description
11
• PLLB
• Programmable Clocks
The Main Oscillator frequency can be measured by using the PMC Main Clock Frequency
register. The SLCK is used as reference for the measurement.
4.11.2. Power Management
Using power management can dramatically reduce the power consumption of an
Embedded Device. Via the PMC various clocks can be disabled or their speed can be
reduced:
• stopping the PLLs (PLLA and / or PLLB)
• stopping the clocks of the various peripherals
• reducing the clock rates of peripherals, especially by changing MCK.
The PMC supports the following power-saving features: Idle mode and power-down mode.
Please note that not every operating system supports these modes.
•Idle Mode. In idle mode, the processor clock will be re-enabled by any interrupt. The
peripherals, however, are only able to generate an interrupt if they still have a clock, so
care has to be taken as to when a peripheral can be powered down.
•Power-down Mode. In many cases a system waits for a user action or some other
rare event. In such a case, it is possible to change MCK to SLCK. Any external event
which changes the state on peripheral pins (not the USB) can then be detected by the
PIO controller or the AIC.
It should also be taken into account that when a PLL is stopped it will take some time to
restart it. Changing the PLL frequencies or stopping them can therefore be done only
at a moderate rate. If short reaction times are required, this is not a choice.
Additionally, the following measures can reduce power consumption considerably:
• switching off the TFT supply voltage
• putting peripheral chips like Ethernet controller and / or PHY or serial driver devices
in power down mode
• putting the SDRAM into self-refresh mode
4.12. Real-time Timer (RTT)
The Real-time Timer is a 32-bit counter combined with a 16-bit prescaler running at Slow
Clock (SLCK=32768 Hz). As the RTT keeps running if only the backup supply voltage is
available, it is used as a Real-time clock.
The RTT can generate an interrupt every time the prescaler rolls over. Usually the RTT is
configured to generate an interrupt every second, so the prescaler will be programmed
with the value 7FFFh.

Hardware Description
12
The RTT can also generate an alarm if a preprogrammed 32-bit value is reached by the
counter.
4.13. Timer Counter (TC)
The Stamp9G45 features two blocks of timer counters with three counters each. Due to
multiplexing four timer counters may be used with external signals.
The TC consists of three independent 16-bit Timer/Counter units. They may be cascaded
to form a 32-bit or 48-bit timer/counter. The timers can run on the internal clock sources
MCK/2, MCK/8, MCK/32, MCK/128, SLCK or the output of another timer channel. External
clocks may be used as well as the counters can generate signals on timer events. They
also can be used to generate PWM signals.
4.14. Periodic Interval Timer (PIT)
The PIT consists of a 20-bit counter running on MCK / 16. This counter can be preloaded
with any value between 1 and 220. The counter increments until the preloaded value is
reached. At this stage it rolls over and generates an interrupt. An additional 12-bit counter
counts the interrupts of the 20 bit counter.
The PIT is intended for use as the operating system’s scheduler interrupt.
4.15. Watchdog Timer
The watchdog timer is a 12-bit timer running at 256 Hz (Slow Clock / 128). The maximum
watchdog timeout period is therefore equal to 16 seconds. If enabled, the watchdog
timer asserts a hardware reset at the end of the timeout period. The application program
must always reset the watchdog timer before the timeout is reached. If an application
program has crashed for some reason, the watchdog timer will reset the system, thereby
reproducing a well defined state once again.
The Watchdog Mode Register can be written only once. After a processor reset, the
watchdog is already activated and running with the maximum timeout period. Once the
watchdog has been reconfigured or deactivated by writing to the Watchdog Mode Register,
only a processor reset can change its mode once again.
4.16. Real-time Clock (RTC)
The Real-time clock combines a complete time-of-day clock with alarm, a two-hundred-
year Gregorian calendar and a programmable periodic interrupt. The time and calendar
values are coded in BCD format.
4.17. True Random Number Generator (TRNG)
The True Random Generator (TRNG) passes the American NIST Special Publication
800-22 and the Diehard Random Tests Suites. It provides a 32-bit value every 84 clock
cycles.

Hardware Description
13
4.18. Peripheral DMA Controller (PDC)
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals
and the on- and/or off-chip memories. The PDC contains unidirectional and bidirectional
channels. The full-duplex peripherals feature unidirectional channels used in pairs
(transmit only or receive only). The half-duplex peripherals feature one bidirectional
channel. Typically full-duplex peripherals are USARTs, SPI or SSC. The MCI is a half duplex
device.
The user interface of each PDC channel is integrated into the user interface of the
peripheral it serves. The user interface of unidirectional channels (receive only or
transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set
(pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The
bidirectional channel user interface contains four 32-bit memory pointers and four 16-bit
counters. Each set (pointer, counter) is used by current transmit, next transmit, current
receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the
transfer. This significantly reduces the number of clock cycles required for a data transfer,
which improves microcontroller performance. To launch a transfer, the peripheral triggers
its associated PDC channels by using transmit and receive signals. When the programmed
data is transferred, an end of transfer interrupt is generated by the peripheral itself. There
are four kinds of interrupts generated by the PDC:
• End of Receive Buffer
• End of Transmit Buffer
• Receive Buffer Full
• Transmit Buffer Empty
The "End of Receive Buffer" / "End of Transmit Buffer" interrupts signify that the DMA
counter has reached zero. The DMA pointer and counter register will be reloaded from the
reload registers ("DMA new pointer register" and "DMA new counter register") provided
that the "DMA new counter register" has a non-zero value. Otherwise a "Receive Buffer
Full" or, respectively, a "Transmit Buffer Empty" interrupt is generated, and the DMA
transfer terminates. Both reload registers are set to zero automatically after having been
copied to the DMA pointer and counter registers.
4.19. Debug Unit (DBGU)
The Debug Unit is a simple UART which provides only RX/TX lines. It is used as a simple
serial console for Firmware and Operating Systems.
4.20. JTAG Unit
The JTAG unit can be used for hardware diagnostics, hardware initialization, flash memory
programming, and debug purposes. The JTAG unit supports two different modes, namely
the "ICE Mode", and the "Boundary Scan" mode. It is normally jumpered for "ICE Mode".

Hardware Description
14
JTAG interface devices are available for the unit. However, the use of them is not within
the scope of this document.
4.21. Two-wire Interface (TWI)
The TWI is also known under the expression "I2C-Bus", which is a trademark of Philips
and may therefore not be used by other manufacturers. However, interoperability is
guaranteed. The TWI supports both master or slave mode.
The TWI uses only two lines, namely serial data (SDA) and serial clock (SCL). According to
the standard, the TWI clock rate is limited to 400 kHz in fast mode and 100 kHz in normal
mode, but configurable baud rate generator permits the output data rate to be adapted
to a wide range of core clock frequencies.
4.22. Multimedia Card Interface (MCI)
The Stamp9G45 features a onboard Micro-SD-Card slot, which is connected to the MCI-
B interface of the microcontroller. The MCI-A interface is provided for external additional
use.
The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification
V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0.
The MCI includes a command register, response registers, data registers, timeout
counters and error detection logic that automatically handle the transmission of
commands and, when required, the reception of the associated responses and data with a
limited processor overhead. The MCI supports stream, block and multi-block data read and
write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing
processor intervention for large buffer transfers.
The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing
of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards)
or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed).
A bit field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command,
four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock,
command, one data, three power lines and one reserved for future use). The SD Memory
Card interface also supports MultiMedia Card operations. The main differences between
SD and MultiMedia Cards are the initialization process and the bus topology.
4.23. USB Host Port (UHP)
In the current revision of the AT91SAM9G45 USB High speed is not working. It will
work in the processor's next revision, which is expected in august 2011. The Stamp9G45
integrates two USB host ports supporting speeds up to 480 MBit/s. USB Host Port A is
connected directly to the transceiver, USB Host Port B is multiplexed with the USB device
port. Only one of them can be used at a time.
The controller is fully compliant with the Enhanced HCI(EHCI) specification. It supports
both High-speed 480 Mbps and Full-speed 12 Mbps devices.