Toshiba TXZ User manual

TXZ Family
Flash Memory
2018-06-05 1 / 120 Rev. 2.0
© 2018
Toshiba Electronic Devices & Storage Corporation
2018-06
32-bit RISC Microcontroller
TXZ Family
Reference Manual
Flash Memory
(Code Flash: 1.5MB/1.0MB/768KB/512KB)
(Data: Flash 32KB)
(FLASH15MHD32-A)
Revision 2.0

TXZ Family
Flash Memory
2018-06-05 2 / 120 Rev. 2.0
Contents
Preface ................................................................................................................................................................. 8
Related documents ................................................................................................................................................... 8
Conventions ............................................................................................................................................................ 9
Terms and Abbreviation .......................................................................................................................................... 11
1. Outline ......................................................................................................................................................... 12
Memory map .................................................................................................................................................... 14
2. Configuration ............................................................................................................................................... 15
Block Diagrams ................................................................................................................................................ 15
Configuration of Code Flash ............................................................................................................................ 16
2.2.1. Unit of the composition ............................................................................................................................................... 16
2.2.2. Block Configuration .................................................................................................................................................... 16
2.2.3. Page Configuration ..................................................................................................................................................... 21
2.2.4. User Information Area Configuration of Code Flash ................................................................................................... 24
2.2.5. Program/Erase Time of Code Flash ........................................................................................................................... 24
2.2.6. Memory Capacity and the Configuration .................................................................................................................... 25
Configuration of Data Flash ............................................................................................................................. 26
2.3.1. Unit of the composition ............................................................................................................................................... 26
2.3.2. Block Configuration of Data Flash .............................................................................................................................. 26
2.3.3. Page Configuration ..................................................................................................................................................... 27
2.3.4. Program/Erase Time of Data Flash ............................................................................................................................ 28
2.3.5. Memory Capacity and the Configuration .................................................................................................................... 28
3. Function Description and Functional Explanations .................................................................................... 29
Code Flash ....................................................................................................................................................... 30
3.1.1. Command Sequence .................................................................................................................................................. 30
3.1.1.1. List of Command Sequence .......................................................................................................................................... 30
3.1.1.2. Address Bit Configuration in the Bus Write Cycle (Code Flash) .................................................................................... 32
3.1.1.3. Area Address (AA), Block Address (BA): Code Flash .................................................................................................... 34
3.1.1.4. Protect Bit Assignment (PBA): Code flash ..................................................................................................................... 34
3.1.1.5. ID-Read Code (IA, ID): Code Flash ............................................................................................................................... 36
3.1.1.6. Memory Swap Bit Assignment (MSA) ............................................................................................................................ 36
Data Flash ........................................................................................................................................................ 37
3.2.1. Command Sequence .................................................................................................................................................. 37
3.2.1.1. List of Command Sequence .......................................................................................................................................... 37
3.2.1.2. Address Configuration in the Bus Write Cycle (Data Flash)........................................................................................... 38
3.2.1.3. Area Address (AA), Block Address (BA) ........................................................................................................................ 39
3.2.1.4. Protect Bit Assignment (PBA) ........................................................................................................................................ 40
3.2.1.5. ID-Read Code (IA, ID): Data Flash ................................................................................................................................ 40
Flowchart.......................................................................................................................................................... 41
3.3.1. Automatic Programming ............................................................................................................................................. 41
3.3.2. Automatic Erasing ...................................................................................................................................................... 43
3.3.3. Protect bit ................................................................................................................................................................... 45
3.3.4. Security bit .................................................................................................................................................................. 47

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3.3.5. Memory Swap............................................................................................................................................................. 49
4. Details of Flash Memory ............................................................................................................................. 51
Functions.......................................................................................................................................................... 51
4.1.1. Operation Mode of the Flash Memory ........................................................................................................................ 52
4.1.2. Command Execution .................................................................................................................................................. 52
4.1.3. Command Description ................................................................................................................................................ 54
4.1.3.1. Automatic Programming ................................................................................................................................................ 54
4.1.3.2. Automatic chip erasing .................................................................................................................................................. 55
4.1.3.3. Automatic Area Erasing ................................................................................................................................................. 55
4.1.3.4. Automatic Block Erasing ............................................................................................................................................... 56
4.1.3.5. Automatic Page Erasing ................................................................................................................................................ 56
4.1.3.6. Automatic Protect Bit Programming............................................................................................................................... 56
4.1.3.7. Automatic Protect Bit Erasing ........................................................................................................................................ 57
4.1.3.8. Automatic Security Bit Programming ............................................................................................................................. 57
4.1.3.9. Automatic Security Bit Erasing ...................................................................................................................................... 58
4.1.3.10. ID-Read ....................................................................................................................................................................... 58
4.1.3.11. Read/Reset Command ................................................................................................................................................ 59
4.1.3.12. Automatic Memory Swap ............................................................................................................................................ 59
4.1.3.13. Automatic Memory Swap Erasing ............................................................................................................................... 59
4.1.4. Stopping Automatic Chip Erasing ............................................................................................................................... 60
4.1.5. Completion Detection of the Automatic Operation ...................................................................................................... 60
4.1.5.1. Procedure ..................................................................................................................................................................... 60
4.1.6. Protection Function ..................................................................................................................................................... 61
4.1.6.1. How to Set the Protection Function ............................................................................................................................... 61
4.1.6.2. Protection Release ........................................................................................................................................................ 61
4.1.6.3. Protection Temporary Release Function ....................................................................................................................... 61
4.1.7. Security Function ........................................................................................................................................................ 62
4.1.7.1. Security Setting ............................................................................................................................................................. 62
4.1.7.2. Security Setting Release ............................................................................................................................................... 62
4.1.7.3. Operation ...................................................................................................................................................................... 62
4.1.8. Memory Swap Function .............................................................................................................................................. 63
4.1.8.1. Memory Swap Setting ................................................................................................................................................... 63
4.1.8.2. Memory Swap Operation ............................................................................................................................................... 63
4.1.8.3. Erasing the Memory Swap Information .......................................................................................................................... 64
4.1.9. User Information Area ................................................................................................................................................ 65
4.1.9.1. Switching Procedure of the User Information Area ........................................................................................................ 65
4.1.9.2. Data programming Method for the User Information Area ............................................................................................. 65
4.1.9.3. Data Erasing Method for the User Information Area ...................................................................................................... 65
5. Registers ..................................................................................................................................................... 66
Register List ..................................................................................................................................................... 66
Detail of Register ............................................................................................................................................. 67
5.2.1. [FCSBMR] (Flash Security Bit Mask Register) ........................................................................................................... 67
5.2.2. [FCSSR] (Flash Security Status Register) .................................................................................................................. 67
5.2.3. [FCKCR] (Flash Key Code Register) .......................................................................................................................... 67
5.2.4. [FCSR0] (Flash Status Register 0) ............................................................................................................................. 68

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5.2.5. [FCPSR0] (Flash Protect Status Register 0) .............................................................................................................. 69
5.2.6. [FCPSR1] (Flash Protect Status Register 1) .............................................................................................................. 70
5.2.7. [FCPSR3] (Flash Protect Status Register 3) .............................................................................................................. 71
5.2.8. [FCPSR4] (Flash Protect Status Register 4) .............................................................................................................. 71
5.2.9. [FCPSR6] (Flash Protect Status Register 6) .............................................................................................................. 72
5.2.10. [FCPMR0] (Flash Protect Mask Register 0) ............................................................................................................. 72
5.2.11. [FCPMR1] (Flash Protect Mask Register 1) ............................................................................................................. 73
5.2.12. [FCPMR3] (Flash Protect Mask Register 3) ............................................................................................................. 74
5.2.13. [FCPMR4] (Flash Protect Mask Register 4) ............................................................................................................. 75
5.2.14. [FCPMR6] (Flash Protect Mask Register 6) ............................................................................................................. 76
5.2.15. [FCSR1] (Flash Status Register 1) ........................................................................................................................... 76
5.2.16. [FCSWPSR] (Flash Memory SWAP Status Register) ............................................................................................... 77
5.2.17. [FCAREASEL] (Flash Area Selection Register)........................................................................................................ 78
5.2.18. [FCCR] (Flash Control Register) ............................................................................................................................... 79
5.2.19. [FCSTSCLR] (Flash Status Clear Register) ............................................................................................................. 79
5.2.20. [FCBNKCR] (Flash Bank Change Register) ............................................................................................................. 80
5.2.21. [FCBUFDISCLR] Flash Buffer Disable and Clear Register ...................................................................................... 80
6. The programming method .......................................................................................................................... 81
Initialization ...................................................................................................................................................... 81
Mode Description ............................................................................................................................................. 81
Mode Determination ......................................................................................................................................... 82
Memory Map in Each Mode ............................................................................................................................. 82
How to Reprogramming the Flash ................................................................................................................... 82
6.5.1. (1-A) Procedure that a Programming Routine Stored in Flash memory ..................................................................... 83
6.5.1.1. Step-1 ........................................................................................................................................................................... 83
6.5.1.2. Step-2 ........................................................................................................................................................................... 84
6.5.1.3. Step-3 ........................................................................................................................................................................... 84
6.5.1.4. Step-4 ........................................................................................................................................................................... 85
6.5.1.5. Step-5 ........................................................................................................................................................................... 85
6.5.1.6. Step-6 ........................................................................................................................................................................... 86
6.5.2. (1-B) Procedure that a Programming Routine is Transferred from External Host ....................................................... 86
6.5.2.1. Step-1 ........................................................................................................................................................................... 86
6.5.2.2. Step-2 ........................................................................................................................................................................... 87
6.5.2.3. Step-3 ........................................................................................................................................................................... 87
6.5.2.4. Step-4 ........................................................................................................................................................................... 88
6.5.2.5. Step-5 ........................................................................................................................................................................... 88
6.5.2.6. Step-6 ........................................................................................................................................................................... 89
How to Reprogram the Flash in Single Boot Mode ......................................................................................... 90
6.6.1. Single Boot Mode ....................................................................................................................................................... 90
6.6.2. Mode Setting .............................................................................................................................................................. 91
6.6.3. Interface Specifications .............................................................................................................................................. 91
6.6.4. Restrictions on Memories ........................................................................................................................................... 92
6.6.5. Operation Command .................................................................................................................................................. 92
6.6.5.1. RAM transfer ................................................................................................................................................................. 92
6.6.5.2. Flash Memory Erasing .................................................................................................................................................. 92

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6.6.6. Common Operation Regardless of the Command ...................................................................................................... 93
6.6.6.1. Serial Operation Mode Determination ........................................................................................................................... 93
6.6.6.2. Acknowledgement Response Data ............................................................................................................................... 95
6.6.6.3. Password ...................................................................................................................................................................... 96
6.6.6.4. Password Determination ............................................................................................................................................... 99
6.6.6.5. CHECKSUM Calculation ............................................................................................................................................... 99
6.6.7. Communication Rules for Determination of Serial Operation Mode ......................................................................... 100
6.6.8. Communication Rules of RAM Transfer Command .................................................................................................. 101
6.6.9. Communication Rules of Flash memory Erasing ...................................................................................................... 103
6.6.10. Internal Boot Program General Flowchart .............................................................................................................. 104
6.6.11. Reprogramming Procedure of the Flash Using Reprogramming Algorithm in Boot ROM ...................................... 105
6.6.11.1. Step-1 ....................................................................................................................................................................... 105
6.6.11.2. Step-2 ....................................................................................................................................................................... 105
6.6.11.3. Step-3 ....................................................................................................................................................................... 106
6.6.11.4. Step-4 ....................................................................................................................................................................... 106
6.6.11.5. Step-5 ....................................................................................................................................................................... 107
6.6.11.6. Step-6 ....................................................................................................................................................................... 107
How to Reprogramming using Dual Mode ..................................................................................................... 108
6.7.1. Example of Flash Memory Reprogramming Procedure ............................................................................................ 108
6.7.1.1. Step-1 ......................................................................................................................................................................... 108
6.7.1.2. Step-2 ......................................................................................................................................................................... 109
6.7.1.3. Step-3 ......................................................................................................................................................................... 109
6.7.1.4. Step-4 ......................................................................................................................................................................... 110
6.7.1.5. Step-5 ......................................................................................................................................................................... 110
How to Reprogramming User Boot Program ................................................................................................. 111
6.8.1. Example of Flash Memory Reprogramming Procedure ............................................................................................ 111
6.8.1.1. Step-1 ......................................................................................................................................................................... 111
6.8.1.2. Step-2 ......................................................................................................................................................................... 112
6.8.1.3. Step-3 ......................................................................................................................................................................... 112
6.8.1.4. Step-4 ......................................................................................................................................................................... 113
6.8.1.5. Step-5 ......................................................................................................................................................................... 113
6.8.1.6. Step-6 ......................................................................................................................................................................... 114
6.8.1.7. Step-7 ......................................................................................................................................................................... 114
6.8.1.8. Step-8 ......................................................................................................................................................................... 115
6.8.1.9. Step-9 ......................................................................................................................................................................... 115
6.8.1.10. Step-10 ..................................................................................................................................................................... 116
7. General Precautions ................................................................................................................................. 117
8. Revision History ........................................................................................................................................ 118
RESTRICTIONS ON PRODUCT USE ............................................................................................................. 120

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List of Figures
Figure 1.1 The example of a memory map .............................................................................................. 14
Figure 2.1 The Block Diagrams of a flash memory.................................................................................. 15
Figure 3.1 Flowchart of automatic programming (1) ................................................................................ 41
Figure 3.2 Flowchart of automatic programming (2) ................................................................................ 42
Figure 3.3 Flowchart of automatic erasing (1) ......................................................................................... 43
Figure 3.4 Flowchart of automatic erasing (2) ......................................................................................... 44
Figure 3.5 Flowchart of protect (1) ........................................................................................................... 45
Figure 3.6 Flowchart of protect (2) ........................................................................................................... 46
Figure 3.7 Flowchart of security (1) ......................................................................................................... 47
Figure 3.8 Flowchart of security (2) ......................................................................................................... 48
Figure 3.9 Flowchart of memory swap (1) ............................................................................................... 49
Figure 3.10 Flowchart of memory swap (2) ............................................................................................. 50
Figure 4.1 Example of Procedure of Memory Swap ................................................................................ 64
Figure 6.1 Procedure that a Programming Routine Stored in Flash memory (1) .................................... 83
Figure 6.2 Procedure that a Programming Routine Stored in Flash memory (2) .................................... 84
Figure 6.3 Procedure that a Programming Routine Stored in Flash memory (3) .................................... 84
Figure 6.4 Procedure that a Programming Routine Stored in Flash memory (4) .................................... 85
Figure 6.5 Procedure that a Programming Routine Stored in Flash memory (5) .................................... 85
Figure 6.6 Procedure that a Programming Routine Stored in Flash memory (6) .................................... 86
Figure 6.7 Procedure that a Programming Routine is Transferred from External Host (1) ..................... 86
Figure 6.8 Procedure that a Programming Routine is Transferred from External Host (2) ..................... 87
Figure 6.9 Procedure that a Programming Routine is Transferred from External Host (3) ..................... 87
Figure 6.10 Procedure that a Programming Routine is Transferred from External Host (4) ................... 88
Figure 6.11 Procedure that a Programming Routine is Transferred from External Host (5) ................... 88
Figure 6.12 Procedure that a Programming Routine is Transferred from External Host (6) ................... 89
Figure 6.13 Serial operation mode determination data ........................................................................... 93
Figure 6.14 Reception flowchart in serial operation mode ...................................................................... 94
Figure 6.15 Serial operation mode determination flowchart .................................................................... 95
Figure 6.16 Password configuration (Example of Transmission) ............................................................ 97
Figure 6.17 Password check flowchart .................................................................................................... 99
Figure 6.18 Boot program general flowchart ......................................................................................... 104
Figure 6.19 Procedure of Using Reprogramming Algorithm in Boot ROM (1) ...................................... 105
Figure 6.20 Procedure of Using Reprogramming Algorithm in Boot ROM (2) ...................................... 105
Figure 6.21 Procedure of Using Reprogramming Algorithm in Boot ROM (3) ...................................... 106
Figure 6.22 Procedure of Using Reprogramming Algorithm in Boot ROM (4) ...................................... 106
Figure 6.23 Procedure of Using Reprogramming Algorithm in Boot ROM (5) ...................................... 107
Figure 6.24 Procedure of Using Reprogramming Algorithm in Boot ROM (6) ...................................... 107
Figure 6.25 Reprogramming using Dual Mode (1) ................................................................................ 108
Figure 6.26 Reprogramming using Dual Mode (2) ................................................................................ 109
Figure 6.27 Reprogramming using Dual Mode (3) ................................................................................ 109
Figure 6.28 Reprogramming using Dual Mode (4) ................................................................................ 110
Figure 6.29 Reprogramming using Dual Mode (5) ................................................................................ 110
Figure 6.30 Reprogram by User Boot Program (1) ................................................................................ 111
Figure 6.31 Reprogram by User Boot Program (2) ................................................................................ 112
Figure 6.32 Reprogram by User Boot Program (3) ................................................................................ 112
Figure 6.33 Reprogram by User Boot Program (4) ................................................................................ 113
Figure 6.34 Reprogram by User Boot Program (5) ................................................................................ 113
Figure 6.35 Reprogram by User Boot Program (6) ................................................................................ 114
Figure 6.36 Reprogram by User Boot Program (7) ................................................................................ 114
Figure 6.37 Reprogram by User Boot Program (8) ................................................................................ 115
Figure 6.38 Reprogram by User Boot Program (9) ................................................................................ 115
Figure 6.39 Reprogram by User Boot Program (10) .............................................................................. 116

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List of Tables
Table 1.1 Functional description (code flash) .......................................................................................... 12
Table 1.2 Functional description (user information area) ........................................................................ 13
Table 1.3 Functional description (data flash) ........................................................................................... 13
Table 2.1 Signal list .................................................................................................................................. 15
Table 2.2 Block Configuration of 1536KB code flash .............................................................................. 16
Table 2.3 Block Configuration of 1024KB code flash .............................................................................. 18
Table 2.4 Block Configuration of 768KB code flash ................................................................................ 19
Table 2.5 Block Configuration of 512KB code flash ................................................................................ 20
Table 2.6 Page Configuration of 1536KB code flash ............................................................................... 21
Table 2.7 Page Configuration of 1024KB code flash ............................................................................... 22
Table 2.8 Page Configuration of 768KB code flash ................................................................................. 23
Table 2.9 Page Configuration of 512KB code flash ................................................................................. 24
Table 2.10 User Information Area Configuration of Code Flash ............................................................. 24
Table 2.11 Memory capacity and the configuration ................................................................................. 25
Table 2.12 Block configuration of 32 KB data flash ................................................................................. 26
Table 2.13 Page Configuration of 32KB data flash.................................................................................. 27
Table 2.14 Memory capacity and the configuration ................................................................................. 28
Table 3.1 JEDEC compliant functions ..................................................................................................... 29
Table 3.2 Flash memory access using the internal CPU (code flash) ..................................................... 30
Table 3.3 Address bit configuration in the bus write cycle (Code flash) .................................................. 32
Table 3.4 Protect bit programming address ............................................................................................. 34
Table 3.5 ID-Read Command code assignment and the code contents ................................................. 36
Table 3.6 Setting values assigned to [FCSWPSR] using Memory Swap command, and example of
address ................................................................................................................................................ 36
Table 3.7 Command sequence (Data flash) ............................................................................................ 37
Table 3.8 Address bit configuration in the bus write cycle (data flash) ................................................... 38
Table 3.9 Protect bit program address (Data flash) ................................................................................. 40
Table 3.10 ID-Read command code assignment and the contents (Data flash) ..................................... 40
Table 4.1 Flash memory function ............................................................................................................. 51
Table 4.2 Detection of Completion Flash programming/Erasing ............................................................. 60
Table 4.3 Flash memory operation when the security function is enabled ............................................. 62
Table 6.1 The mode and operation .......................................................................................................... 81
Table 6.2 Operation mode setting ............................................................................................................ 82
Table 6.3 Functions and Commands ....................................................................................................... 90
Table 6.4 Pins used in the internal boot program .................................................................................... 91
Table 6.5 Restrictions on the memories in single boot mode .................................................................. 92
Table 6.6 Operation commands in single boot mode .............................................................................. 92
Table 6.7 Setting of baud rate in Single boot mode (fc=10MHz, No error) ............................................. 93
Table 6.8 ACK response data corresponding to serial operation determination data ............................. 95
Table 6.9 ACK response data corresponding to operation command data ............................................ 95
Table 6.10 ACK response data corresponding to CHECKSUM data ...................................................... 96
Table 6.11 ACK response data corresponding to flash memory erasing operation ................................ 96
Table 6.12 Password setting values and setting ranges ......................................................................... 98
Table 6.13 Communication rules for determination of serial operation mode ....................................... 100
Table 6.14 Communication Rules of RAM Transfer Command ............................................................ 101
Table 6.15 Communication Rules of Flash memory Erasing ................................................................ 103
Table 8.1 Revision history ...................................................................................................................... 118

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Preface
Related documents
Document name
Clock Control and Operation Mode
Exception
Input/Output Ports
Product Information
Asynchronous Serial Communication Circuit

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Conventions
● Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the “0b” when the number of bit can be distinctly
understood from a sentence.
● “_N” is added to the end of signal names to indicate low active signals.
● It is called “assert” that a signal moves to its active level, “deassert” to its inactive level.
● When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
● The characters surrounded by [ ] defines the register.
Example: [ABCD]
● “n” substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3]
 [XYZn]
● "x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, “x” means A, B, and C . . .
Example: [ADACR0], [ADBCR0], [ADCCR0]  [ADxCR0]
In case of channel, “x” means 0, 1, and 2 . . .
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA]  [T32AxRUNA]
● The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
● The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> = 0x01 (hexadecimal), [XYZn]<VW> = 1 (binary)
● Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
● Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
● Unless otherwise specified, register access supports only word access.
● The register defined as reserved must not be rewritten. Moreover, do not use the read value.
● The value read from the bit having default value of "-" is unknown.
● When a register containing both of writable bits and read-only bits is written, read-only bits should be
written with their default value, In the cases that default is "-", follow the definition of each register.
● Reserved bits of the Write-only register should be written with their default value. In the cases that default is
"-", follow the definition of each register.
● Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

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The flash memory uses the Super Flash® technology under the license of Silicon Storage Technology, Inc.
Super Flash® is registered trademark of Silicon Storage Technology, Inc.
All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

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Terms and Abbreviation
Some of abbreviations used in this document are as follows:
ACK Acknowledgement
Addr Address
Adr Address
BLK Block
KB Kilo Bytes
PG Page
POR Power On Reset
SFR Special Function Register
UART Universal Asynchronous Receiver Transmitter

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1. Outline
The code flash which stores a program code, and the data flash which stores data are explained.
A code flash stores an instruction code, and CPU reads and executes it.
There is user information area which can be accessed in a code flash by bank change. Since user information area is
not erased by a chip erasing command, for example, it can be written a unique management number etc. for every
chip.
A data flash stores data, and even if power supply is intercepted, it keeps data.
Table 1.1 Functional description (code flash)
Flash memory
Function
classification
Function Functional Description Comments
Code Flash
1.5MB
1.0MB
768KB
512KB
Programming and
Erasing
Automatic
Programming
Data programming is performed
at 4 words (16 bytes).
Automatic chip erasing
Erasing of all the area of a flash
memory is performed
automatically.
Object:
Code flash
Data flash
Except User
information
area in code
flash.
Automatic area erasing
Erasing in an area unit is
performed automatically.
Automatic block erasing
Erasing in a block unit is
performed automatically.
Automatic page erasing
Erasing in a page unit is
performed automatically.
Program/erase
protection
Protection
Programming and erasing can
be prohibited per block.(Note)
Security Security
Prohibition of read-out from the
flash memory by a flash writer
and using a debugging tools.
Memory swap Automatic memory
swap
Swap /swap release /swap size
specification of a code flash
block is performed automatically.
Execute Instruction Execute Instruction
Instructions can be executed.
program/erase to
other Flash I/F
program/erase to
code/data Flash I/F
Basic operation to a code/data
flash can be performed.
Dual mode
Note: First 32KB of each FLASH I/F is protected by page unit.

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Table 1.2 Functional description (user information area)
Flash memory
Function
classification
Function Functional Description Comments
User information
area (Code
Flash)
4KB
Programming and
Erasing
Automatic
Programming
Data programming is performed
at 4 words (16 bytes).
Automatic page
erasing
Erasing all the User information
area is performed automatically.
Program/erase
protection Protection
Programming and erasing can
be prohibited per block.
It is the same as
the same address
of a code flash.
Security Security
Prohibition of read-out of the
flash memory by a flash writer
and the usage restrictions of a
debugging function can be
carried out.
It is controlled by
the operation on
the code flash
side.
Execute Instruction - -
Execution of
instruction cannot
be performed.
Table 1.3 Functional description (data flash)
Flash memory
Function
classification
Function Functional Description Comments
Data Flash
32KB
Programming and
Erasing
Automatic
Programming
Data programming is performed
at 1 words (4 bytes).
Automatic area erasing
Erasing in an area unit is
performed automatically.
Automatic block erasing
Erasing in a block unit is
performed automatically.
Automatic page erasing
Erasing in a page unit is
performed automatically.
Program/erase
protection Protection
Programming and erasing can
be prohibited per block.
Security Security
Prohibition of read-out of the
flash memory by a flash writer
and the usage restrictions of a
debugging function can be
carried out.
It becomes
effective
simultaneously by
the operation on
the code flash
side.
Execute Instruction
Execute Instruction
Instructions can be executed.
No prefetch buffer
program/erase to
other Flash area
program/erase to code
Flash area
Basic operation to a code flash
can be performed.
Dual mode

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Memory map
Figure 1.1 The example of a memory map
0xFFFFFFFF
0x5E180000
0x5E000000
0x5DFF0000
0x3F7F9800
0x3F7F8000
0x30008000
0x30000000
0x20030800
0x20000000 RAM(194KB) RAM(194KB)
0x00180000
0x00001800
0x00000000
Single Boot Mode Single Chip Mode
CODE FLASH
(1536KB)
BOOT ROM
DATA FLASH
(32KB)
BOOT ROM(6KB)
code
SRAM
Peripheral
DATA FLASH
(32KB)
CODE FLASH
(Mirror 1536KB)
FLASH (SFR)
BOOT ROM
(Mirror)
CODE FLASH
(Mirror 1536KB)
フラッシュ(SFR)
FLASH (SFR)
Flash domain (Mirror)
Code Flash
Programming/ Erasing/
Read
Flash domain (Data)
Data Flash
Programming/ Erasing/
Read
Flash domain (Code)
Code Flash
Read/Execution

TXZ Family
Flash Memory
2018-06-05 15 / 120 Rev. 2.0
2. Configuration
Block Diagrams
The Block Diagrams of a Flash memory and a signal list are shown.
INTFLCRDY0
INTFLDRDY
The clock for program/
erasing timing generation
f
IHOSC1
Flash Security Bit
Mask Register
[FCSBMR]
Code Flash interface0
(FL AS H I/F0)
Control circuit for Code Flash
（Includ e au tomatic sequence
control circuit）
Flash Security Status
Register
[FCSSR]
Flash Key Code
Register
[FCKCR]
Flash Status
Register 0
[FCSR0]
Flash Protect Status
Register n
[FCPSRn]
n = 0,1,3,4
Flash Protect Status
Register 6
[FCPSR6]
Flash Protect Mask
Register 6
[FCPMR6]
Flash Status
Register 1
[FCSR1]
Flash Memory SWAP
Status Register
[FCSWPSR]
Flash Area Selection
Register
[FCAREASEL]
Flash Control
Register
[FCCR]
Flash Status Clear
Register
[FCSTSCLR]
Data Flash
Data Flash interface (FL AS H I/F2)
Code Flas h0
Read buffer
Flash Bank Change
Register
[FCBNKCR]
Flash Buffer Disable
and Clear Register
[FCBUFDISCLR]
Control circuit for Data Flash
（Include automatic sequence
control circuit）
U ser Info rm at ion A rea
Protect bit
Protect bit
Security bit Me m ory S WA P bit
< KEYCODE>
Flash Protect Mask
Register n
[FCPMRn]
n = 0,1,3,4
Code Flash interface1
(FL AS H I/F1)
Code Flas h1
INTFLCRDY1
Figure 2.1 The Block Diagrams of a flash memory
Table 2.1 Signal list
No
Symbol
Signal name
I/O
Related reference manual
1 fIHOSC1
The clock for program/erasing
timing generation Input Clock Control and Operation Mode
2 INTFLCRDY0
FLASH I/F0 Code FLASH
Ready interruption n
Output Exception
3 INTFLCRDY1
FLASH I/F1 Code FLASH
Ready interruption n
Output Exception
4 INTFLDRDY
Data FLASH Ready
interruption
Output Exception

TXZ Family
Flash Memory
2018-06-05 16 / 120 Rev. 2.0
Configuration of Code Flash
2.2.1. Unit of the composition
There are "Area", "Block", and "Page" as a unit of the composition of a code flash.
 Area
It is used by an erase function.
One area size is a maximum of 512 KB. It changes with memory sizes of a product.
 Block
It is used by the erase function and a protection function.
One block size is 32 KB.
 Page
It is used by the erase function and a protection function.
One page size is 4096 byte.
2.2.2. Block Configuration
Table 2.2 Block Configuration of 1536KB code flash
FLASH
I/F
Area Block name Code execution address Program/erase/read address Block size
(KB)
0
0
Block0
PG0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 4
PG1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 4
PG2 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF 4
PG3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF 4
PG4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 4
PG5 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 4
PG6
0x00006000-0x00006FFF
0x5E006000-0x5E006FFF
4
PG7 0x00007000-0x00007FFF 0x5E007000-0x5E007FFF 4
Block1 0x00008000-0x0000FFFF 0x5E008000-0x5E00FFFF 32
Block2 0x00010000-0x00017FFF 0x5E010000-0x5E017FFF 32
Block3 0x00018000-0x0001FFFF 0x5E018000-0x5E01FFFF 32
Block4 0x00020000-0x00027FFF 0x5E020000-0x5E027FFF 32
Block5 0x00028000-0x0002FFFF 0x5E028000-0x5E02FFFF 32
Block6 0x00030000-0x00037FFF 0x5E030000-0x5E037FFF 32
Block7 0x00038000-0x0003FFFF 0x5E038000-0x5E03FFFF 32
Block8 0x00040000-0x00047FFF 0x5E040000-0x5E047FFF 32
Block9 0x00048000-0x0004FFFF 0x5E048000-0x5E04FFFF 32
Block10
0x00050000-0x00057FFF
0x5E050000-0x5E057FFF
32
Block11 0x00058000-0x0005FFFF 0x5E058000-0x5E05FFFF 32
Block12 0x00060000-0x00067FFF 0x5E060000-0x5E067FFF 32
Block13 0x00068000-0x0006FFFF 0x5E068000-0x5E06FFFF 32
Block14 0x00070000-0x00077FFF 0x5E070000-0x5E077FFF 32
Block15 0x00078000-0x0007FFFF 0x5E078000-0x5E07FFFF 32
1 Block16 0x00080000-0x00087FFF 0x5E080000-0x5E087FFF 32
Block17 0x00088000-0x0008FFFF 0x5E088000-0x5E08FFFF 32

TXZ Family
Flash Memory
2018-06-05 17 / 120 Rev. 2.0
Block18 0x00090000-0x00097FFF 0x5E090000-0x5E097FFF 32
Block19 0x00098000-0x0009FFFF 0x5E098000-0x5E09FFFF 32
Block20 0x000A0000-0x000A7FFF 0x5E0A0000-0x5E0A7FFF 32
Block21 0x000A8000-0x000AFFFF 0x5E0A8000-0x5E0AFFFF 32
Block22 0x000B0000-0x000B7FFF 0x5E0B0000-0x5E0B7FFF 32
Block23 0x000B8000-0x000BFFFF 0x5E0B8000-0x5E0BFFFF 32
Block24 0x000C0000-0x000C7FFF 0x5E0C0000-0x5E0C7FFF 32
Block25
0x000C8000-0x000CFFFF
0x5E0C8000-0x5E0CFFFF
32
Block26 0x000D0000-0x000D7FFF 0x5E0D0000-0x5E0D7FFF 32
Block27 0x000D8000-0x000DFFFF 0x5E0D8000-0x5E0DFFFF 32
Block28 0x000E0000-0x000E7FFF 0x5E0E0000-0x5E0E7FFF 32
Block29 0x000E8000-0x000EFFFF 0x5E0E8000-0x5E0EFFFF 32
Block30 0x000F0000-0x000F7FFF 0x5E0F0000-0x5E0F7FFF 32
Block31 0x000F8000-0x000FFFFF 0x5E0F8000-0x5E0FFFFF 32
1 2
Block0
PG0 0x00100000-0x00100FFF 0x5E100000-0x5E100FFF 4
PG1 0x00101000-0x00101FFF 0x5E101000-0x5E101FFF 4
PG2 0x00102000-0x00102FFF 0x5E102000-0x5E102FFF 4
PG3
0x00103000-0x00103FFF
0x5E103000-0x5E103FFF
4
PG4 0x00104000-0x00104FFF 0x5E104000-0x5E104FFF 4
PG5 0x00105000-0x00105FFF 0x5E105000-0x5E105FFF 4
PG6 0x00106000-0x00106FFF 0x5E106000-0x5E106FFF 4
PG7 0x00107000-0x00107FFF 0x5E107000-0x5E107FFF 4
Block1 0x00108000-0x0010FFFF 0x5E108000-0x5E10FFFF 32
Block2 0x00110000-0x00117FFF 0x5E110000-0x5E117FFF 32
Block3 0x00118000-0x0011FFFF 0x5E118000-0x5E11FFFF 32
Block4 0x00120000-0x00127FFF 0x5E120000-0x5E127FFF 32
Block5 0x00128000-0x0012FFFF 0x5E128000-0x5E12FFFF 32
Block6
0x00130000-0x00137FFF
0x5E130000-0x5E137FFF
32
Block7 0x00138000-0x0013FFFF 0x5E138000-0x5E13FFFF 32
Block8 0x00140000-0x00147FFF 0x5E140000-0x5E147FFF 32
Block9 0x00148000-0x0014FFFF 0x5E148000-0x5E14FFFF 32
Block10 0x00150000-0x00157FFF 0x5E150000-0x5E157FFF 32
Block11 0x00158000-0x0015FFFF 0x5E158000-0x5E15FFFF 32
Block12 0x00160000-0x00167FFF 0x5E160000-0x5E167FFF 32
Block13 0x00168000-0x0016FFFF 0x5E168000-0x5E16FFFF 32
Block14 0x00170000-0x00177FFF 0x5E170000-0x5E177FFF 32
Block15
0x00178000-0x0017FFFF
0x5E178000-0x5E17FFFF
32
Note: Block0 is a generic name for PG0 to PG7. It can access as PG0 to PG7.

TXZ Family
Flash Memory
2018-06-05 18 / 120 Rev. 2.0
Table 2.3 Block Configuration of 1024KB code flash
FLASH
I/F
Area Block name Code execution address Program/erase/read
address
Block size
(KB)
0
0
Block0
PG0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 4
PG1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 4
PG2 0x00002000-0x00002FFF 0x5E002000-0x5E002FFF 4
PG3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF 4
PG4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 4
PG5 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 4
PG6 0x00006000-0x00006FFF 0x5E006000-0x5E006FFF 4
PG7 0x00007000-0x00007FFF 0x5E007000-0x5E007FFF 4
Block1 0x00008000-0x0000FFFF 0x5E008000-0x5E00FFFF 32
Block2 0x00010000-0x00017FFF 0x5E010000-0x5E017FFF 32
Block3 0x00018000-0x0001FFFF 0x5E018000-0x5E01FFFF 32
Block4 0x00020000-0x00027FFF 0x5E020000-0x5E027FFF 32
Block5 0x00028000-0x0002FFFF 0x5E028000-0x5E02FFFF 32
Block6 0x00030000-0x00037FFF 0x5E030000-0x5E037FFF 32
Block7 0x00038000-0x0003FFFF 0x5E038000-0x5E03FFFF 32
Block8 0x00040000-0x00047FFF 0x5E040000-0x5E047FFF 32
Block9 0x00048000-0x0004FFFF 0x5E048000-0x5E04FFFF 32
Block10 0x00050000-0x00057FFF 0x5E050000-0x5E057FFF 32
Block11
0x00058000-0x0005FFFF
0x5E058000-0x5E05FFFF
32
Block12
0x00060000-0x00067FFF
0x5E060000-0x5E067FFF
32
Block13 0x00068000-0x0006FFFF 0x5E068000-0x5E06FFFF 32
Block14 0x00070000-0x00077FFF 0x5E070000-0x5E077FFF 32
Block15 0x00078000-0x0007FFFF 0x5E078000-0x5E07FFFF 32
1
Block16 0x00080000-0x00087FFF 0x5E080000-0x5E087FFF 32
Block17 0x00088000-0x0008FFFF 0x5E088000-0x5E08FFFF 32
Block18 0x00090000-0x00097FFF 0x5E090000-0x5E097FFF 32
Block19 0x00098000-0x0009FFFF 0x5E098000-0x5E09FFFF 32
Block20 0x000A0000-0x000A7FFF 0x5E0A0000-0x5E0A7FFF 32
Block21
0x000A8000-0x000AFFFF
0x5E0A8000-0x5E0AFFFF
32
Block22 0x000B0000-0x000B7FFF 0x5E0B0000-0x5E0B7FFF 32
Block23 0x000B8000-0x000BFFFF 0x5E0B8000-0x5E0BFFFF 32
Block24 0x000C0000-0x000C7FFF 0x5E0C0000-0x5E0C7FFF 32
Block25 0x000C8000-0x000CFFFF 0x5E0C8000-0x5E0CFFFF 32
Block26 0x000D0000-0x000D7FFF 0x5E0D0000-0x5E0D7FFF 32
Block27 0x000D8000-0x000DFFFF 0x5E0D8000-0x5E0DFFFF 32
Block28 0x000E0000-0x000E7FFF 0x5E0E0000-0x5E0E7FFF 32
Block29 0x000E8000-0x000EFFFF 0x5E0E8000-0x5E0EFFFF 32
Block30 0x000F0000-0x000F7FFF 0x5E0F0000-0x5E0F7FFF 32
Block31
0x000F8000-0x000FFFFF
0x5E0F8000-0x5E0FFFFF
32
Note: Block0 is a generic name for PG0 to PG7. It can access as PG0 to PG7.

TXZ Family
Flash Memory
2018-06-05 19 / 120 Rev. 2.0
Table 2.4 Block Configuration of 768KB code flash
FLASH
I/F
Area Block name Code execution address Program/erase/read
address
Block size
(KB)
0
0
Block0
PG0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 4
PG1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 4
PG2
0x00002000-0x00002FFF
0x5E002000-0x5E002FFF
4
PG3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF 4
PG4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 4
PG5 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 4
PG6 0x00006000-0x00006FFF 0x5E006000-0x5E006FFF 4
PG7 0x00007000-0x00007FFF 0x5E007000-0x5E007FFF 4
Block1 0x00008000-0x0000FFFF 0x5E008000-0x5E00FFFF 32
Block2 0x00010000-0x00017FFF 0x5E010000-0x5E017FFF 32
Block3 0x00018000-0x0001FFFF 0x5E018000-0x5E01FFFF 32
Block4 0x00020000-0x00027FFF 0x5E020000-0x5E027FFF 32
Block5
0x00028000-0x0002FFFF
0x5E028000-0x5E02FFFF
32
Block6 0x00030000-0x00037FFF 0x5E030000-0x5E037FFF 32
Block7 0x00038000-0x0003FFFF 0x5E038000-0x5E03FFFF 32
Block8 0x00040000-0x00047FFF 0x5E040000-0x5E047FFF 32
Block9 0x00048000-0x0004FFFF 0x5E048000-0x5E04FFFF 32
Block10 0x00050000-0x00057FFF 0x5E050000-0x5E057FFF 32
Block11 0x00058000-0x0005FFFF 0x5E058000-0x5E05FFFF 32
Block12 0x00060000-0x00067FFF 0x5E060000-0x5E067FFF 32
Block13 0x00068000-0x0006FFFF 0x5E068000-0x5E06FFFF 32
Block14 0x00070000-0x00077FFF 0x5E070000-0x5E077FFF 32
Block15
0x00078000-0x0007FFFF
0x5E078000-0x5E07FFFF
32
1
Block16 0x00080000-0x00087FFF 0x5E080000-0x5E087FFF 32
Block17 0x00088000-0x0008FFFF 0x5E088000-0x5E08FFFF 32
Block18 0x00090000-0x00097FFF 0x5E090000-0x5E097FFF 32
Block19 0x00098000-0x0009FFFF 0x5E098000-0x5E09FFFF 32
Block20 0x000A0000-0x000A7FFF 0x5E0A0000-0x5E0A7FFF 32
Block21 0x000A8000-0x000AFFFF 0x5E0A8000-0x5E0AFFFF 32
Block22 0x000B0000-0x000B7FFF 0x5E0B0000-0x5E0B7FFF 32
Block23 0x000B8000-0x000BFFFF 0x5E0B8000-0x5E0BFFFF 32
Note: Block0 is a generic name for PG0 to PG7. It can access as PG0 to PG7.

TXZ Family
Flash Memory
2018-06-05 20 / 120 Rev. 2.0
Table 2.5 Block Configuration of 512KB code flash
FLASH
I/F
Area Block name Code execution address Program/erase/read
address
Block size
(KB)
0 0
Block0
PG0 0x00000000-0x00000FFF 0x5E000000-0x5E000FFF 4
PG1 0x00001000-0x00001FFF 0x5E001000-0x5E001FFF 4
PG2
0x00002000-0x00002FFF
0x5E002000-0x5E002FFF
4
PG3 0x00003000-0x00003FFF 0x5E003000-0x5E003FFF 4
PG4 0x00004000-0x00004FFF 0x5E004000-0x5E004FFF 4
PG5 0x00005000-0x00005FFF 0x5E005000-0x5E005FFF 4
PG6 0x00006000-0x00006FFF 0x5E006000-0x5E006FFF 4
PG7 0x00007000-0x00007FFF 0x5E007000-0x5E007FFF 4
Block1 0x00008000-0x0000FFFF 0x5E008000-0x5E00FFFF 32
Block2 0x00010000-0x00017FFF 0x5E010000-0x5E017FFF 32
Block3 0x00018000-0x0001FFFF 0x5E018000-0x5E01FFFF 32
Block4 0x00020000-0x00027FFF 0x5E020000-0x5E027FFF 32
Block5
0x00028000-0x0002FFFF
0x5E028000-0x5E02FFFF
32
Block6 0x00030000-0x00037FFF 0x5E030000-0x5E037FFF 32
Block7 0x00038000-0x0003FFFF 0x5E038000-0x5E03FFFF 32
Block8 0x00040000-0x00047FFF 0x5E040000-0x5E047FFF 32
Block9 0x00048000-0x0004FFFF 0x5E048000-0x5E04FFFF 32
Block10 0x00050000-0x00057FFF 0x5E050000-0x5E057FFF 32
Block11 0x00058000-0x0005FFFF 0x5E058000-0x5E05FFFF 32
Block12 0x00060000-0x00067FFF 0x5E060000-0x5E067FFF 32
Block13 0x00068000-0x0006FFFF 0x5E068000-0x5E06FFFF 32
Block14 0x00070000-0x00077FFF 0x5E070000-0x5E077FFF 32
Block15
0x00078000-0x0007FFFF
0x5E078000-0x5E07FFFF
32
Note: Block0 is a generic name for PG0 to PG7. It can access as PG0 to PG7.