PLX Technology CompactPCI 9030RDK-LITE Quick user guide

CompactPCI 9030RDK-LITE
Hardware Reference Manual

CompactPCI 9030RDK-LITE
Hardware Reference Manual
Version 1.2
October 2004
Website: http://www.plxtech.com
Technical Support: http://www.plxtech.com/support/
Phone: [phone]
800 759-3735
Fax: [phone]

© 2004 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: CPCI 9030/LITE-RDK-HRM-P1-1.2
Printed in the USA, October 2004

PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any
damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX CompactPCI 9030RDK-LITE, a Reference Design Kit, from a hardware
perspective. It contains a description of all major functional circuit blocks on the board and also is a
reference for the creation of software for this product. This manual also includes the complete schematics
and bill of materials.
REVISION HISTORY
Date Version Comments
May 2000 1.0 Hardware Reference Manual release
•Updated Schematics
•Other minor changes
March 2003 1.1 •Updated Table 3-2 with new value for offset 7Ah
•Updated Bill of Materials
•Updated Schematics
October 2004 1.2 •Updated EEPROM table, Manual and BOM
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. i

TABLE OF CONTENTS
1. GENERAL INFORMATION...................................................................................................1
1.1 FEATURES...................................................................................................................................... 2
1.2 RDK INSTALLATION ........................................................................................................................ 2
2. SYSTEM ARCHITECTURE...................................................................................................3
3. HARDWARE ARCHITECTURE............................................................................................5
3.1 HARDWARE MEMORY MAP.............................................................................................................. 6
3.2 PCI 9030....................................................................................................................................... 6
3.3 SERIAL EEPROM ..........................................................................................................................7
3.4 SYNCHRONOUS DUAL-PORT RAM (DPRAM) ................................................................................ 10
3.5 HOT SWAP CONTROL CIRCUIT....................................................................................................... 10
3.5.1 Hardware Connection Control ............................................................................................. 10
3.5.2 Software Connection Control............................................................................................... 10
3.6 TEST HEADERS ............................................................................................................................ 11
3.7 PLX OPTION MODULE CONNECTOR .............................................................................................. 11
3.8 HARDWARE MODULES .................................................................................................................. 11
3.8.1 RS232 Serial Port................................................................................................................ 11
3.8.2 Debug and Status LEDs...................................................................................................... 11
3.8.3 Reset Circuitry ..................................................................................................................... 11
3.8.3.1 Power-on-Reset...............................................................................................................................11
3.8.3.2 Reset Pushbutton Switch.................................................................................................................11
3.8.4 Flash ROM Socket............................................................................................................... 11
3.9 PROTOTYPING AREA..................................................................................................................... 11
3.9.1 Thirty-three (33) Surface Mount Footprints ......................................................................... 12
3.9.2 The Common BGA Landscape............................................................................................ 13
3.10 CONFIGURING THE RDK BOARD .................................................................................................... 14
3.10 CONFIGURING THE RDK BOARD .................................................................................................... 14
3.11 MEMORY ACCESS TO THE DPRAM ............................................................................................... 14
4. PCB LAYOUT CONSIDERATION ......................................................................................15
4.1 REQUIREMENTS OF STANDARDS.................................................................................................... 15
4.2 μBGA FOOTPRINT LAYOUT........................................................................................................... 15
5. CONVERTING THE 6U BOARD TO A 3U BOARD ...........................................................16
6. CUSTOMER SUPPORT......................................................................................................16
7. REFERENCES....................................................................................................................16
8. ABEL CODE / BILL OF MATERIALS / SCHEMATICS......................................................17
8.1 ABEL CODE FOR U13................................................................................................................... 17
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. iii

Contents / Figures / Tables
LIST OF FIGURES
FIGURE 1-1. COMPACT PCI 9030RDK-LITE LAYOUT DIAGRAM (6U/4HP CARD)..........................1
FIGURE 2-1. COMPACTPCI 9030RDK-LITE SYSTEM ARCHITECTURE...........................................3
FIGURE 3-1. COMPACTPCI 9030RDK-LITE HARDWARE BLOCK DIAGRAM....................................5
FIGURE 3-2. BGA LANDSCAPES ................................................................................................13
LIST OF TABLES
TABLE 3-1. COMPACTPCI 9030RDK-LITE MEMORY MAP.............................................................6
TABLE 3-2. CONTENTS OF THE SERIAL EEPROM.........................................................................8
TABLE 3-3. PROTOTYPING FOOTPRINTS AND PROTOTYPING AREA ON THE
COMPACTPCI 9030RDK-LITE BOARD .....................................................................12
TABLE 8-1. BILL OF MATERIALS..................................................................................................19
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
iv © 2004 PLX Technology, Inc. All rights reserved.

1. General Information
5VCC
3.3V
GND
3.3V
GND
16 pin
SOIC
16 pin
SOIC
16 pin
SOIC 16 pin SOIC
20 pin
SSOIC
20 pin
SOIC
20 pin
SOIC
20 pin SOIC
208/144/80
PQFP
footprints
44 pin
TQFP
20 pin
PLCC
54 pin TSOP54 pin TSOP
84/68/44/28
PLCC
footprints
25x25 0.1" through hole
prototyping area
176/100/48
PQFP
footprints
48 pin
SSOP 48 pin SSOP
24 pin
SSOP
24 pin
SSOP
LAH1 LAH2
DPRAM
U8
16 pin
SSOP
16 pin
SSOP
28 pin SOIC28 pin SOIC
48 pin
SSOP 48 pin SSOP
LEDs
Hot Swap
Circuit
POM Connector
LAH1LAH2
DPRAM
U12
DPRAM
U11
J
3
LAH3
LAH4LAH6
LAH5
GAL
PCI
9030
Blue
LED
switch
DB 9
Connector
reset circuit
RS232 Port
Flash
ROM
Socket
60MHz
OSC
LED's
CPCI connector J1
26x26 0.05"
pitch BGA
landscape
Serial
EEPROM
Figure 1-1. CompactPCI 9030RDK-LITE Layout Diagram (6U/4HP Card)
The CompactPCI 9030RDK-LITE Reference Design Kit (RDK) is a CompactPCI bus target
prototyping kit, which can be used for custom design development such as networking, telecom,
imaging, industrial, and storage applications using the PLX PCI 9030 SMARTarget™ I/O Accelerator
chip. The reference design kit allows customers to create designs with or without a microprocessor.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. 1

Section 1
General Information RDK Installation
1.1 Features
The CompactPCI 9030RDK-LITE
Reference Design Kit (RDK) is a 6U
CompactPCI Bus Target Prototyping Kit,
which contains a six-layer, assembled PC
board with the dimensions of 6.30” L x 9.19”
W and the following features:
•PLX PCI 9030 SMARTarget™ I/O
Accelerator in 180-pin 0.8mm pitch
μBGA package.
•Socketed serial EEPROM for
configuring PCI 9030
•Supports both multiplexed and non-
multiplexed bus modes
•Thirty-three (33) surface mount
prototyping footprints and a 0.05” pitch
BGA landscape, which can be used
with different FPGAs, CPLDs,
SDRAMs, SRAMs, data transceivers
and general-purpose logic devices.
•Socketed 32-pin PLCC footprint
provides designers with a place for their
flash boot ROM.
•On-board, up to 32-bit synchronous
dual-port, SRAM plus a small 20-pin
programmable GAL demonstrating PCI
9030 continuous burst read/write
features. It allows the user to plug the
board into a PCI system and be
operational immediately.
•Four (4) green user defined
status/debug LEDs and one (1) red
power on LED.
•Built-in DB9 connector, RS232
transceiver, and UART for easy
addition of a serial port to the Local
bus.
•A push button switch and a reset
generator are capable of generating
reset signals to any device on the
board.
•Socketed oscillator for Local bus clock
and PLL, provide up to 60 MHz clock.
•The Hot Swap control circuit allows the
orderly insertion and removal of the
board without adversely affecting
system operation.
•Six logic analyzer headers with
standard HP footprints allow easy
probing of Local bus signals.
•PLX Multiplexed bus mode Option
Module (POM) connector provides
connection to other PLX POMs or
customer devices.
•A 25x25 0.1-inch grid through-hole area
allows easy prototyping with through-
hole components.
•By cutting the 6U front panel to 3U and
detaching the upper portion of the PC
board, the RDK can be converted to a
3U board
1.2 RDK Installation
1. Turn off the power of the
CompactPCI system.
2. Wear user-suitable grounding
straps.
3. Align the 6U board with the top and
bottom guide rails and slide the
board into an available single slot.
4. Make sure the board is completely
plugged in and lock both handles at
the front panel.
5. Plug the power cord into the power
receptacle again and turn on the
power switch of the CompactPCI
system.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
2© 2004 PLX Technology, Inc. All rights reserved.

2. System Architecture
CompactPCI BUS, 32-bit, 33MHz
PCI 9030
(µBGA)
LOCAL BUS
POM
Connector
Test
Headers Serial Port Reset Circuit
Flash ROM
Socket
Prototyping
Area &
Footprints
Users
Defined
LEDs
Synchronous
Dual-port
RAM
4Kx18
Synchronous
Dual-port
RAM
4Kx18
Separate Bus
Hot Swap
Control Circuit
Back End Power
up to 32-bit, 60MHz
Local
reset
Controls
Back End
Power
Early Power Ejector
Switch Blue LED
EEPROM
Figure 2-1. CompactPCI 9030RDK-LITE System Architecture
As shown in Figure 2-1, the RDK board
contains:
•A PCI 9030 SMARTarget™ I/O
Accelerator
•Four components (two 4Kx18
Synchronous Dual-Port RAMs, Test
Headers, and POM connector) that
connect to the PCI 9030 Local bus
•Four commonly used hardware
modules (Serial Port, Reset Circuit,
LEDs, and Flash ROM Socket)
•A Hot Swap control circuit
•Many carefully selected prototyping
footprints throughout 70% of the
board area.
The RDK is shipped with one Synchronous
Dual-Port RAM (DPRAM) on the board as
the default. A PCI master adapter card
residing on the PCI bus can perform single
memory read/write cycles, and continuous
burst memory read/write from/to the left port
of the DPRAM in direct slave mode.
Four hardware modules on the RDK provide
some basic hardware building blocks for
almost any PCI 9030 design.
The Hot Swap control circuit controls the
current rise when the components and
circuits receive power at the local bus,
providing backend power status to the
system controller and the local reset signal
to the PCI 9030 device.
The thirty-three (33) surface mount
footprints include many SOIC, SSOP and
TSOP footprints for common logic ICs and
many PLCC and PQFP footprints for
common FPGAs and CPLDs. Also, the BGA
landscape and the through-hole prototyping
area provide additional flexibility.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. 3

3. Hardware Architecture
This section provides a detailed description of the hardware of the CompactPCI 9030RDK-LITE.
Figure 3-1 shows the hardware block diagram of the RDK.
PCI 9030
Address Bus
Data Bus
Control Bus
Serial
EEPROM
Local Bus
Clock Circuit
60MHz
ADSL
LW/RL
CS0L
BLASTL
16V8
GAL
LOCAL BUS
Up to 32-bit, 60MHz
CompactPCI BUS
32-bit, 33MHz
CE0L
DPADSL
R/WL
Address Bus
Data bus
Control Bus
Resistor Networks to configure
16 or 32 bit address bus
Synchronous Dual-Port RAM
4Kx18
Left Port Right Port
Synchronous Dual-Port RAM
4Kx18
Left Port Right Port
Separate Bus
POM
Connector Test Headers
Hardware modules
Serial Port
Reset Circuit
Users defined LEDs
Flash ROM Socket
Prototyping
Area &
Footprints
Hot Swap Control
Circuit
BD_Select#
Healthy#
PCI_Reset#
Local_Reset#
3.3V Early Power
MOSFET
5 Volt Power
5V/3.3V
LDO
2A To Back
End
Circuits
Ejector
Switch
Blue
LED
ENUM#
Figure 3-1. CompactPCI 9030RDK-LITE Hardware Block Diagram
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. 5

Section 3
Hardware Architecture PCI 9030
3.1 Hardware Memory Map
Table 3-1. CompactPCI 9030RDK-LITE Memory Map
Address Range Device Chip Select Comments
FFF FFFF
Programmable Unused Can be assigned to
CS2#-CS3# Available
Programmable
000 4000 POM connector CS1# Programmable
000 3FFF
000 0000 Two DPRAM
(U11 and U12) CS0# 32-bit access
000 1FFF
000 0000 One DPRAM
(U11only) CS0# 16-bit access
Note: If two DPRAMs (U11 and U12) are used for 32-bit access, the address range will
be 000 0000 – 000 3FFFh.
3.2 PCI 9030
The PCI 9030, a 32-bit, 33MHz PCI Bus Target
Interface chip with SMARTarget™ technology, is
the most advanced feature rich, general-
purpose, bus target device available in the
market today.
•PCI v2.2 Compliant: The PCI 9030
enables up to 132 Mbytes/second in
PCI burst transfers and up to 240
Mbytes/second burst transfers on the
60MHz Local bus.
•PCI Target Read Ahead Mode: The
PCI 9030 will pre-fetch a programmable
amount of data from the Local bus. The
pre-fetched data can then be burst
transferred on the PCI bus from the PCI
9030 internal PCI Target Read FIFO.
The pre-fetched size can be
programmed to match the PCI master
burst length or can be used as PCI
Target Read Ahead mode data. This
feature allows for increased bandwidth
and reduced read latency.
•PCI Target Programmable Burst: The
PCI 9030 may be programmed for
several burst lengths, including
unlimited burst. This allows for
maximum transfer rates on both PCI
and Local buses.
•PCI Target Delay Write: The PCI 9030
supports PCI Target Delay Write mode
where the PCI target write data is
postponed in the PCI Target Write FIFO
to allow uninterrupted burst
transactions on the Local bus. This
allows for a higher throughput for
conditions in which the PCI clock
frequency is slower than the local clock
frequency or when Local bus bursting is
desirable.
•Posted Memory Write: A PCI memory
write can be posted to the PCI 9030 for
later transfer to the Local bus. This
allows for maximum PCI performance
and avoids potential deadlock
situations.
•Programmable Local bus operates up
to 60MHz and supports both non-
multiplexed and multiplexed 32-bit
address/data and Dynamic Local Bus
width control allowing slave accesses to
8-, 16-, or 32-bit devices.
•Supports 5 PCI to local address
spaces. These spaces (Space 0, 1, 2, 3
and Expansion ROM space) allow a
PCI Bus Master to access the local
memory spaces with individually
programmable wait states, bus widths,
and burst capabilities.
•Up to 9 programmable General
Purpose I/Os, which may be used for a
variety of purposes.
•Four programmable chip selects
eliminate external decode circuits.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
6 © 2004 PLX Technology, Inc. All rights reserved.

Section 3
Serial EEPROM Hardware Architecture
•CompactPCI Hot Swap Ready: The
PCI 9030 supports LEDon#, CPCISW,
BD_SEL# and ENUM# signals as well
as Hot Swap capabilities registers –
HS_CNTL, HS_NEXT, and HS_CSR.
•Supports automatic on-the-fly Big
Endian and Little Endian conversion for
all operations and data types.
•Interrupt Generator can assert PCI
interrupts from external and internal
sources
•Fully supports the Vital Product Data
(VPD) PCI v2.2 extension including
New Capabilities Structure. Provides an
alternate access method for user or
system-defined parameters or
configuration data.
3.3 Serial EEPROM
The CompactPCI 9030RDK-LITE board can
boot with or without the presence of the serial
EEPROM. The RDK is shipped with a 2K-bit,
3.3V serial EEPROM which is used for PCI 9030
initialization. The serial EEPROM directly
connects to the PCI 9030 through its four-pin
interface. A total of 136 bytes of data is
preprogrammed to the EEPROM to bring up the
RDK after the system reset. The data includes
the device and functional information for plug-
and-play (PnP), PCI memory resource allocation
and initial values of PCI 9030 internal registers.
Also, it includes the PCI 9030 chip select
programming, CS0L, which becomes active
when the DPRAM is selected at the address
range 0000000 to 0001FFFh and programs the
wait states of DPRAM read/write cycles. Once
the RDK initializes correctly, customers can
perform memory read/write with the DPRAM,
using PLXMon®to examine the serial EEPROM
contents or reprogram it with user defined data
files.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. 7

Hardware Architecture Serial EEPROM
Table 3-2. Contents of the Serial EEPROM
Serial
EEPROM
Offset
Register
Offset Register Description Register Bits Affected Register Values (Hex)
00h PCI 02h Device ID PCIIDR[31:16] 30C1
02h PCI 00h Vendor ID PCIIDR[15:0] 10B5
04h PCI 06h PCI Status PCISR[15:0] 0290
06h PCI 04h PCI Command Reserved 0000
08h PCI 0Ah Class Code PCICCR[23:8] 0680
0Ah PCI 08h Class Code / Revision PCICCR[7:0] / PCIREV[7:0] 0001
0Ch PCI 2Eh Subsystem ID PCISID[15:0] 9030
0Eh PCI 2Ch Subsystem Vendor ID PCISVID[15:0] 10B5
10h PCI 36h Reserved Reserved 0000
12h PCI 34h Reserved / New Capability Pointer Reserved / CAP_PTR[7:0] 0040
14h PCI 3Eh (Maximum Latency and Minimum Grant
are not loadable) Reserved 0000
16h PCI 3Ch Interrupt Pin /
(Interrupt Line Routing is not loadable) PCIIPR[7:0] / PCIILR [7:0] 0100
18h PCI 42h MSW of Power Management Capabilities PMC[14:11, 5, 3:0] 4802
1Ah PCI 40h Power Management Next Capability Pointer /
Power Management Capability ID PMNEXT[7:0] / PMCAPID[7:0] 4801
1Ch PCI 46h Power Management Data /
PMCSR Bridge Support Extension Reserved 0000
1Eh PCI 44h LSW of Power Management Control/Status PMCSR[14:8] 0000
20h PCI 4Ah Hot Swap Control/Status Reserved 0000
22h PCI 48h LSW of Hot Swap Next Capability Pointer /
Hot Swap Capability ID HS_NEXT[7:0] / HS_CNTL[7:0] 4C06
24h PCI 4Eh PCI Vital Product Data Address Reserved 0000
26h PCI 4Ch PCI Vital Product Data Next Capability Pointer/
PCI Vital Product Data Capability ID PVPD_NEXT[7:0] / PVPDCNTL[7:0] 0003
28h Local 02h MSW of Range for PCI-to-Local Address Space 0 LAS0RR[31:16] FFFF
2Ah Local 00h LSW of Range for PCI-to-Local Address Space 0 LAS0RR[15:0] E000
2Ch Local 06h MSW of Range for PCI-to-Local Address Space 1 LAS1RR[31:16] 0000
2Eh Local 04h LSW of Range for PCI-to-Local Address Space 1 LAS1RR[15:0] 0000
30h Local 0Ah MSW of Range for PCI-to-Local Address Space 2 LAS2RR[31:16] 0000
32h Local 08h LSW of Range for PCI-to-Local Address Space 2 LAS2RR[15:0] 0000
34h Local 0Eh MSW of Range for PCI-to-Local Address Space 3 LAS3RR[31:16] 0000
36h Local 0Ch LSW of Range for PCI-to-Local Address Space 3 LAS3RR[15:0] 0000
38h Local 12h MSW of Range for PCI-to-Local Expansion ROM EROMRR[31:16] 0000
3Ah Local 10h LSW of Range for PCI-to-Local Expansion ROM EROMRR[15:0] 0000
3Ch Local 16h MSW of Local Base Address (Remap) for
PCI-to-Local Address Space 0 LAS0BA[31:16] 0000
3Eh Local 14h LSW of Local Base Address (Remap) for
PCI-to-Local Address Space 0 LAS0BA[15:0] 0001
40h Local 1Ah MSW of Local Base Address (Remap) for
PCI-to-Local Address Space 1 LAS1BA[31:16] 0000
42h Local 18h LSW of Local Base Address (Remap) for
PCI-to-Local Address Space 1 LAS1BA[15:0] 0000
44h Local 1Eh MSW of Local Base Address (Remap) for
PCI-to-Local Address Space 2 LAS2BA[31:16] 0000
46h Local 1Ch LSW of Local Base Address (Remap) for
PCI-to-Local Address Space 2 LAS2BA[15:0] 0000
48h Local 22h MSW of Local Base Address (Remap) for
PCI-to-Local Address Space 3 LAS3BA[31:16] 0000
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
8 © 2004 PLX Technology, Inc. All rights reserved.

Section 3
SERIAL EEPROM Hardware Architecture
Serial Register Register Values
Register Description Register Bits Affected
EEPROM
Offset Offset (Hex)
4Ah Local 20h LSW of Local Base Address (Remap) for
PCI-to-Local Address Space 3 LAS3BA[15:0] 0000
4Ch Local 26h MSW of Local Base Address (Remap) for
PCI-to-Local Expansion ROM EROMBA[31:16] 0000
4Eh Local 24h LSW of Local Base Address (Remap) for
PCI-to-Local Expansion ROM EROMBA[15:0] 0000
50h Local 2Ah
MSW of Bus Region Descriptors for Local Address
Space 0 LAS0BRD[31:16] 0040
52h Local 28h
LSW of Bus Region Descriptors for Local Address
Space 0 LAS0BRD[15:0] 2081
54h Local 2Eh
MSW of Bus Region Descriptors for Local Address
Space 1 LAS1BRD[31:16] 0080
56h Local 2Ch
LSW of Bus Region Descriptors for Local Address
Space 1 LAS1BRD[15:0] 0000
58h Local 32h
MSW of Bus Region Descriptors for Local Address
Space 2 LAS2BRD[31:16] 0080
5Ah Local 30h
LSW of Bus Region Descriptors for Local Address
Space 2 LAS2BRD[15:0] 0000
5Ch Local 36h
MSW of Bus Region Descriptors for Local Address
Space 3 LAS3BRD[31:16] 0080
5Eh Local 34h
LSW of Bus Region Descriptors for Local Address
Space 3 LAS3BRD[15:0] 0000
60h Local 3Ah MSW of Bus Region Descriptors for
Expansion ROM EROMBRD[31:16] 0000
62h Local 38h LSW of Bus Region Descriptors for
Expansion ROM EROMBRD[15:0] 0000
64h Local 3Eh MSW of Chip Select (CS) 0 Base and Range CS0BASE[31:16] 0000
66h Local 3Ch LSW of Chip Select (CS) 0 Base and Range CS0BASE[15:0] 1001
68h Local 42h MSW of Chip Select (CS) 1 Base and Range CS1BASE[31:16] 0000
6Ah Local 40h LSW of Chip Select (CS) 1 Base and Range CS1BASE[15:0] 0000
6Ch Local 46h MSW of Chip Select (CS) 2 Base and Range CS2BASE[31:16] 0000
6Eh Local 44h LSW of Chip Select (CS) 2 Base and Range CS2BASE[15:0] 0000
70h Local 4Ah MSW of Chip Select (CS) 3 Base and Range CS3BASE[31:16] 0000
72h Local 48h LSW of Chip Select (CS) 3 Base and Range CS3BASE[15:0] 0000
74h Local 4Eh Serial EEPROM Write-Protected Address Boundary PROT_AREA[6:0] 0030
76h Local 4Ch Interrupt Control/Status Register INTCSR[15:0] 0000
78h Local 52h
MSW of PCI Target Response, Serial EEPROM,
and Initialization Control CNTRL[31:16] 807C
7Ah Local 50h
LSW of PCI Target Response, Serial EEPROM,
and Initialization Control CNTRL[15:0] 4000
7Ch Local 56h MSW of General Purpose I/O Control GPIOC[31:16] 0024
7Eh Local 54h LSW of General Purpose I/O Control GPIOC[15:0] 9000
80h Local 72h MSW of Hidden 1 Power Management Data Select PMDATA[7:0] hidden, D0 and D3hot
Power Dissipated 0000
82h Local 70h LSW of Hidden 1 Power Management Data Select PMDATA[7:0] hidden, D0 and D3hot
Power Consumed 0000
84h Local 76h MSW of Hidden 2 Power Management Data Scale Reserved 0000
86h Local 74h LSW of Hidden 2 Power Management Data Scale
PMCSR[14:13] hidden,
Bits [7:0] are used as follows:
[7:6] D3hot Power Dissipated,
[5:4] D0 Power Dissipated,
[3:2] D3hot Power Consumed,
[1:0] D0 Power Consumed
0000
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. 9

Section 3
Hardware Architecture PLX Option Module Connector
3.4 Synchronous Dual-Port RAM
(DPRAM)
The PCI 9030 is connected to (2) two
Synchronous Dual–Port RAMs, U11 and U12,
on the RDK board. These DPRAMs are 3.3V, 9
ns, 4Kx18 Cypress devices. However, the board
is assembled with one DPRAM (U11) on board
as a default.
The DPRAM serves two purposes on the RDK
board. First, the left port of DPRAM U11,
connects to the lower 16-bit data bus of the PCI
9030 with simple interface logic that resides in
the 5ns, 20-pin programmable GAL device. A
PCI bus master can perform 8- and 16-bit single
memory cycles with the DPRAM through the PCI
9030. If the PCI bus master supports bursting,
the PCI master can perform 16-bit continuous
burst memory cycles with the DPRAM also.
Second, the PCI 9030 is a PCI target chip with
an output only address bus. If a customer’s
design has a microprocessor or microcontroller,
they can place these devices on the separate
bus on the right port of the DPRAM. Also, if the
customer wants to have 32-bit DPRAM, they can
add the same Cypress chip to U12 and
rearrange the resistor networks RN34, RN36
and RN38. (See page 5 of the Schematics for
more details.)
The interface between the PCI 9030 and the
DPRAMs is very straightforward. The left port of
the DPRAM is configured in the pipelined mode.
Three control input signals, chip enable 1
(CE1L), counter enable (CNTENLL), and output
enable (OELL) are enabled and the counter
reset signal (CNTRSTL) is disabled with related
pull-up and pull-down resistors. Only two control
input signals, address strobe (ADSLL) and chip
enable (CE0L), are converted from PCI 9030
control signals. If the PCI 9030 local clock is
running at 60MHz, the PCI 9030 needs two wait
states for the single or the first data read of a
burst memory read cycle, and zero wait states
for the single or burst write cycle.
On the right port of the DPRAMs, all the input
control signals are preset to idle states. A 29x2
header, J3, provides access to address, data,
and control signals on the right port and nearby
prototyping pads provide the connections to the
customers’ designs in the separate bus on the
right port of the DPRAMs.
3.5 Hot Swap Control Circuit
The RDK is a full Hot Swap board that includes
both hardware connection control and software
connection control in accordance with the
CompactPCI Hot Swap specifications. It can
work on a range of systems from non-Hot Swap
systems to High Availability systems.
3.5.1 Hardware Connection Control
The BD_SEL# signal at the J1 CompactPCI
connector is connected to the BD_SELL input of
PCI 9030 chip and ON# signal input of the
Linear Technology LTC1643L Hot Swap
Controller. An external 1.2K ohm pull-up resistor
is connected to this signal pin and early VIO
power. When the board is hot plugged into a
CompactPCI system, before the J1 connector
makes contact with the BD_SEL# pin on the
backplane, the PCI 9030 chip is already
powered-up with early 3.3V. The 1.2K-ohm
external pull-up will activate the PCI 9030
internal pre-charge regulator and built-in 10K
ohm pull-up resistors to precharge all required
PCI I/O signals on the RDK to one Volt. This
prevents erroneous system operation during Hot
Swap insertion of the board.
The Board Healthy signal, HEALTHYL, is
generated by the LTC1643L as the Power Good
signal for the 5V power output. The Power-Good
Threshold voltage is 4.40 to 4.75V. As long as
the 5V power input reaches this range, the
Power-Good signal – HEALTHYL—will be
generated. Also the LTC1643L controls the
current limit and the power up rate. In this RDK,
the current limit is 3A (the capacity of the LDO of
the LT1587CM-3.3) and the power up rate would
be dv/dt = 50uA/0.1uF, or determined by the
current limit and the load capacitance,
whichever is slower.
With two logic gates, the Local PCI Reset signal,
LOCAL_RSRL, was driven from the Platform
Reset, PCIRSTL, from the system backplane
and the Healthy signal, HEALTHYL from the
LTC1643L to reset the PCI 9030.
3.5.2 Software Connection Control
A micro switch located at the lower ejector
handle of the 6U RDK board is used to signal
the insertion or impending extraction of the RDK.
When the handle is unlocked, the CPCISW is
pulled-up to 3.3V. That informs the PCI 9030
that the board is at the impending extraction
state. When the handle is locked, CPCISW is
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
10 © 2004 PLX Technology, Inc. All rights reserved.

Section 3
HARDWARE MODULES Hardware Architecture
pulled down to ground. This informs the PCI
9030 that the board is fully inserted. Also,
ENUML is generated to signal the status of the
handle to the system Host.
A blue LED is located near the bottom handle of
the 6U front panel. The anode is connected to a
5V power source through a 100-ohm series
resistor. The cathode is connected to the
LEDonL PCI 9030 pin. The blue LED lights up
for a moment at the RDK power up, after which
the blue LED is software driven.
3.6 Test Headers
Six logic analyzer headers are implemented with
a standard 0.1”, 2x10 Hewlett Packard
configuration. In this RDK, they serve two
different functions. One is for easy probing. All
PCI 9030 Local bus signals, configuration and
status signals are well arranged within these
headers. Headers LAH1 and LAH2 contain
Local bus address signals. Headers LAH3 and
LAH4 contain Local bus data signals (or
multiplexed address/data signals in the
multiplexed mode). Headers LAH5 and LAH6
carry Local bus control and status signals.
Designers can use these headers to connect to
a standard board for additional prototyping. The
headers do not provide any power source;
therefore, this must be connected separately for
prototyping daughterboards.
3.7 PLX Option Module Connector
The PLX Option Module Connector resides
directly on the 32-bit multiplexed mode Local
Bus. A slave device may be connected to this
connector. A programmable chip select, CS1L,
is used to select the option module. A hardware
interrupt, INTi1, is used for the option module to
generate an interrupt to the CompactPCI bus
master through the PCI 9030. The schematic
provides information for all of the 100-pin
connector signals. If desired, this connector can
be used for expansion and prototyping.
3.8 Hardware Modules
The RDK-LITE provides four hardware modules:
1) RS232 serial port, 2) debug and status LEDs,
3) reset circuitry, and 4) flash ROM socket.
These four modules are in addition to the clock
generator used to provide up to 60MHz Local
bus clock to the PCI 9030, synchronous Dual-
Port RAM, and POM connector.
3.8.1 RS232 Serial Port
The RS232 Serial Port combines a DB9 male
connector, a 3-output / 5 input DTE transceiver
and a UART. The serial port provides the
parallel interface to the PCI 9030 Local bus or
the separate bus at the dual-port memory.
3.8.2 Debug and Status LEDs
There are four green user-defined LEDs near
the top edge of the RDK board. Each LED
anode is connected to 3.3VDC through a 150-
ohm ¼ watt resistor. The LED cathode is
connected to a prototyping pad. As long as an
active low signal can sink 16 – 20 mA of current,
it can directly drive the LEDs without changing
the resistor value.
3.8.3 Reset Circuitry
3.8.3.1 Power-on-Reset
Power-on-reset is provided by an external
3.3V power supply supervisor. The valid
power-on-reset period is 1ms, which is
hardwired into the supply supervisor IC.
3.8.3.2 Reset Pushbutton Switch
The Reset Pushbutton switch allows the
user to reset the Local Bus side of the board
only. When this pushbutton switch is
pressed, a manual reset can be generated
to reset the devices on the PCI 9030 Local
bus.
3.8.4 Flash ROM Socket
A 32-pin PLCC footprint and related PLCC
socket is provided on the RDK. This can be
used to install a 3.3V, 512KB byte-wide flash
memory device. It can be used to store
microprocessor or DSP code for booting the
Local bus master devices. The flash ROM
footprint is pre-connected to power and ground.
The prototyping pads are provided for all control
signal pins as well as all address and data lines.
3.9 Prototyping Area
The RDK board contains a huge prototyping
area as mentioned before. To make the
prototyping area more user-friendly and cost
effective, three key features have been
implemented. The first is 30+ surface mount
footprints, the second is the 0.05” pitch common
BGA landscape and the last is a 25x25 0.1” grid
through-hole prototyping area.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
© 2004 PLX Technology, Inc. All rights reserved. 11

Section 3
Hardware Architecture Prototyping Area
3.9.1 Thirty-three (33) Surface Mount Footprints
Table 3-3. Prototyping Footprints and Prototyping Area on the
CompactPCI 9030RDK-LITE Board
Package Qty. Wide & Pitch Destination Remark
32-pin PLCC 1 0.05” pitch FP1
84-pin PLCC 1 0.05” pitch FP2
68-pin PLCC 1 0.05” pitch FP3
44-pin PLCC 1 0.05” pitch FB4
28-pin PLCC 1 0.05” pitch FP5
FP2 to FP5
co-exist at a 84-pin
PLCC area
20-pin PLCC 1 0.05” pitch FP6
16-pin SOIC narrow 4 .150”wide, 0.05” pitch FP7, 8, 15, 16
54-pin TSOP 2 0.8mm pitch FP9, 10
28-pin SOIC wide 2 .300” wide, 0.05” pitch FP11, 12
48-pin SSOP 4 .300”wide, 0.025” pitch FP13,14,23,24
20-pin SOIC wide 4 .300”wide, 0.05” pitch FP17,18,19,20
24-pin SSOP 2 .150”wide, 0.025” pitch FP21, 22
44-pin TQFP 1 0.8mm pitch FP25
16-Pin SSOP 2 .150” wide, 0.025” pitch FP26,27
208-pin PQFP 1 0.5mm pitch FP28
144-pin TQFP 1 0.5mm pitch FP29
80-pin TQFP 1 0.5mm pitch FP30
FP28, 29, 30
co-exist at a 208-
pin PQFP area
176-pin PQFP 1 0.5mm pitch FP31
100-pin TQFP 1 0.5mm pitch FP32
48-pin TQFP 1 0.5mm pitch FP33
FP31,32,33
co-exist at a 176-
pin PQFP area
26x26 BGA matrix 1 0.05” pitch
25x25 0.1” through hole area
2 @ 1x30 0.1” through hole rails for 3.3VCC
2 @ 1x30 0.1” through hole rails for GND
1 @ 1x30 0.1” through hole rail for 5VCC
As shown in Table 3-3, the surface-mount
footprints are carefully selected based on three
factors.
1) The footprints can be used for industry
standard, surface-mount logic devices.
2) The footprints accommodate current CPLDs
and FPGAs.
3) If the designer wants to build a complex
design on the Local bus or separate the bus
at the DPRAMs, there are enough footprints
for a CPU, memory, programmable control
logic, bus transceivers and discrete devices.
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2
12 © 2004 PLX Technology, Inc. All rights reserved.