Texas Instruments 2 Series User manual

BQ76905 2-Series to 5-Series High Accuracy Battery Monitor and Protector for Li-Ion,
Li-Polymer, LiFePO4 (LFP), and LTO Battery Packs
1 Features
• Battery monitoring capability for 2-series to 5-
series cells
• Integrated low-side drivers for NFET protection
with optional autonomous recovery
• Extensive protection suite including voltage,
temperature, current, and internal diagnostics
• 16-bit delta-sigma voltage ADC
– High-accuracy cell voltage measurement of 4
mV (typical)
• A dedicated simultaneous 16- and 24-bit delta-
sigma coulomb counter ADC
• – High-accuracy current measurement with low
input offset error
– Wide-range current applications (±200-mV
measurement range across sense resistor)
– 48-bit accumulated charge integrator with timer
• Host-controlled cell balancing
• Multiple power modes (typical battery pack
operating range conditions)
– NORMAL mode: 32 μA to 175 μA
– SLEEP mode: 6 μA
– DEEPSLEEP mode: 2.7 μA
– SHUTDOWN Mode: <1 μA
• High voltage tolerance of 45 V on cell connect and
select additional pins
• Support for temperature sensing using an internal
sensor and external thermistor
• Integrated one-time-programmable (OTP) memory
for device settings, programmed by TI
• 400-kHz I2C serial communications with optional
CRC support
• Programmable LDO for external system usage
• 20-pin QFN (RGR) package
2 Applications
•Cordless power tools and garden tools
•Vacuum cleaners
•Non-military drones
•Other industrial battery pack (2 series to 5 series)
3 Description
The Texas Instruments BQ76905 provides a
highly integrated, high-accuracy battery monitor and
protector for 2-series to 5-series Li-ion, Li-polymer,
LiFePO4 (LFP), and LTO battery packs. Each device
includes a high-accuracy monitoring system, a highly
configurable protection subsystem, and support for
host-controlled cell balancing. Integration includes
low-side protection NFET drivers, a programmable
LDO for external system use, and an I2C host
communication interface supporting up to 400-kHz
operation with optional CRC. The BQ76905 is
available in a 20-pin QFN package.
Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE (NOM)
BQ76905 RGR (20-pin QFN) 3.5 mm × 3.5 mm × 0.9
mm, 0.5-mm pitch
(1) See the orderable addendum at the end of the data sheet.
PACK-
VDD
SCL
INTP
SDA
VC3B
VC2
VC1
VC0
VC3A
VC5
REGSRC
VC4B
VC4A
BAT
TS CHG SRP SRN
DSG
SDA
SCL
REGOUT
ALERT
VSS
PACK+
TS
GND
MCU
+
+
+
+
+
Figure 3-1. Simplified Schematic
BQ76905
SLUSE97 – NOVEMBER 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Device Comparison Table...............................................3
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Supply Current............................................................ 7
6.6 Digital I/O.................................................................... 7
6.7 REGOUT LDO............................................................ 8
6.8 Voltage References.....................................................8
6.9 Coulomb Counter........................................................9
6.10 Coulomb Counter Digital Filter..................................9
6.11 Current Wake Detector............................................10
6.12 Analog-to-Digital Converter.....................................13
6.13 Cell Balancing......................................................... 15
6.14 Internal Temperature Sensor.................................. 15
6.15 Thermistor Measurement........................................15
6.16 Hardware Overtemperature Detector......................16
6.17 Internal Oscillator.................................................... 16
6.18 Charge and Discharge FET Drivers........................16
6.19 Comparator-Based Protection Subsystem..............17
6.20 Timing Requirements—I2C Interface, 100-kHz
Mode........................................................................... 19
6.21 Timing Requirements—I2C Interface, 400-kHz
Mode........................................................................... 20
6.22 Timing Diagram.......................................................20
6.23 Typical Characteristics............................................ 21
7 Detailed Description......................................................26
7.1 Overview................................................................... 26
7.2 Functional Block Diagram......................................... 26
7.3 Device Configuration.................................................27
7.3.1 Commands and Subcommands......................... 27
7.3.2 Configuration Using OTP or Registers .............. 27
7.3.3 Device Security.................................................. 27
7.4 Device Hardware Features....................................... 27
7.4.1 Voltage ADC.......................................................27
7.4.2 Coulomb Counter and Digital Filters.................. 28
7.4.3 Protection FET Drivers....................................... 28
7.4.4 Voltage References............................................ 29
7.4.5 Multiplexer.......................................................... 29
7.4.6 LDOs.................................................................. 29
7.4.7 Standalone Versus Host Interface......................29
7.4.8 ALERT Pin Operation.........................................30
7.4.9 Low Frequency Oscillator...................................30
7.4.10 I2C Serial Communications Interface............... 30
7.5 Measurement Subsystem......................................... 32
7.5.1 Voltage Measurement........................................ 32
7.5.2 Current Measurement and Charge Integration...33
7.5.3 Internal Temperature Measurement................... 34
7.5.4 Thermistor Temperature Measurement.............. 34
7.5.5 Factory Trim and Calibration.............................. 34
7.6 Protection Subsystem............................................... 35
7.6.1 Protections Overview......................................... 35
7.6.2 Primary Protections............................................ 35
7.6.3 CHG Detector.....................................................35
7.6.4 Cell Open-Wire Protection..................................36
7.6.5 Diagnostic Checks..............................................36
7.7 Cell Balancing........................................................... 37
7.8 Device Operational Modes........................................37
7.8.1 Overview of Operational Modes......................... 37
7.8.2 NORMAL Mode.................................................. 38
7.8.3 SLEEP Mode......................................................38
7.8.4 DEEPSLEEP Mode............................................ 39
7.8.5 SHUTDOWN Mode............................................ 39
7.8.6 CONFIG_UPDATE Mode................................... 40
8 Application and Implementation.................................. 41
8.1 Application Information............................................. 41
8.2 Typical Application.................................................... 41
8.2.1 Design Requirements.........................................44
8.2.2 Detailed Design Procedure................................ 45
8.2.3 Application Performance Plot............................. 46
8.2.4 Random Cell Connection Support......................46
8.2.5 Startup Timing.................................................... 47
8.2.6 FET Driver Turn-Off............................................48
8.2.7 Usage of Unused Pins........................................51
8.3 Power Supply Recommendations.............................51
8.4 Layout....................................................................... 52
8.4.1 Layout Guidelines...............................................52
8.4.2 Layout Example..................................................52
9 Device and Documentation Support............................54
9.1 Documentation Support............................................ 54
9.1.1 Related Documentation......................................54
9.2 Receiving Notification of Documentation Updates....54
9.3 Support Resources................................................... 54
9.4 Trademarks...............................................................54
9.5 Electrostatic Discharge Caution................................54
9.6 Glossary....................................................................54
10 Revision History.......................................................... 54
11 Mechanical, Packaging, and Orderable
Information.................................................................... 55
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4 Device Comparison Table
BQ76905 DEVICE FAMILY
PART NUMBER SETTINGS PROGRAMMABLE CELL COUNT SUPPORTED REGOUT STATUS
BQ76905 Y 2–5 Enabled, 3.3 V
BQ76905xy(1) Y 2–5 Enabled, 3.3 V
(1) PRODUCT PREVIEW
5 Pin Configuration and Functions
20 VC4B6SRP
1VC3A 15 REGOUT
19 VC4A7SRN
2VC3B 14 ALERT
18 VC58TS
3VC2 13 SDA
17 BAT9DSG
4VC1 12 SCL
16 REGSRC10CHG
5VC0 11 VSS
Not to scale
Figure 5-1. BQ76905 Pinout
Table 5-1. Pin Functions
PIN I/O TYPE DESCRIPTION
NO. NAME
1 VC3A I IA Sense voltage input pin for the negative terminal of the fourth cell from the bottom of
the stack, and return balance current for the fourth cell from the bottom of the stack
2 VC3B I IA Sense voltage input pin for the third cell from the bottom of the stack, and balance
current input for the third cell from the bottom of the stack.
1 VC2 I IA
Sense voltage input pin for the second cell from the bottom of the stack, balance
current input for the second cell from the bottom of the stack, and return balance
current for the third cell from the bottom of the stack
2 VC1 I IA
Sense voltage input pin for the first cell from the bottom of the stack, balance current
input for the first cell from the bottom of the stack, and return balance current for the
second cell from the bottom of the stack
3 VC0 I IA Sense voltage input pin for the negative terminal of the first cell from the bottom of the
stack, and return balance current for the first cell from the bottom of the stack
6 SRP I IA
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN, where SRP is the top of the sense resistor. A
charging current generates a positive voltage at SRP relative to SRN.
7 SRN I IA
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A
charging current generates a positive voltage at SRP relative to SRN.
8 TS I/O I/OA Thermistor or general-purpose ADC input and functions as wakeup from SHUTDOWN
9 DSG O OA NMOS Discharge FET drive output pin
10 CHG O OA NMOS Charge FET drive output pin
11 VSS — P Device ground
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Table 5-1. Pin Functions (continued)
PIN I/O TYPE DESCRIPTION
NO. NAME
12 SCL I/O I/OD I2C serial communication bus clock
13 SDA I/O I/OD I2 C serial communication bus data
14 ALERT O OD Digital interrupt output pin
15 REGOUT O OA LDO output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
16 REGSRC I IA Input pin for REGOUT LDO, also functions as supply for the CHG and DSG FET drivers
17 BAT I P Primary power supply input pin
18 VC5 I IA
Sense voltage input pin for the fifth cell from the bottom of the stack, balance current
input for the fifth cell from the bottom of the stack, and the top-of-stack measurement
point
19 VC4A I IA Sense voltage input pin for negative terminal of the fifth cell from the bottom of the
stack, and return balance current for the fifth cell from the bottom of the stack
20 VC4B I IA Sense voltage input pin for the fourth cell from the bottom of the stack, and balance
current input for the fourth cell from the bottom of the stack
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
DESCRIPTION PINS MIN MAX UNIT
Supply voltage range, VIN(DC) (2) BAT, REGSRC VSS–0.3 VSS+40 V
Short duration input voltage range,
VIN(short) (2) VC1 – VC5, BAT, REGSRC, CHG VSS+45 V
DC input voltage range, VIN(DC) ALERT, SCL, SDA VSS–0.3 VSS+6 V
DC input voltage range, VIN(DC) TS VSS–0.3 2.1 V
DC input voltage range, VIN(DC) (2) SRP, SRN VSS–0.3 2.1 V
DC input voltage range, VIN(DC) (2) VC5 Maximum of VSS–0.3
and VC4A–0.3 VSS+40 V
DC input voltage range, VIN(DC) (2) VC4A Maximum of VSS–0.3
and VC4B–0.3 VSS+40 V
DC input voltage range, VIN(DC) (2) VC4B Maximum of VSS–0.3
and VC3A–0.3 VSS+40 V
DC input voltage range, VIN(DC) (2) VC3A Maximum of VSS–0.3
and VC3B–0.3 VSS+40 V
DC input voltage range, VIN(DC) (2) VC3B Maximum of VSS–0.3
and VC2–0.3 VSS+40 V
DC input voltage range, VIN(DC) (2) VC2 Maximum of VSS–0.3
and VC1–0.3 VSS+40 V
DC input voltage range, VIN(DC) (2) VC1 Maximum of VSS–0.3
and VC0–0.3 VSS+40 V
DC input voltage range, VIN(DC) VC0 VSS–0.3 VSS+6 V
DC input voltage range, VIN(DC) (2) CHG VSS–30 VSS+40 V
Output voltage range, VODSG VSS–0.3 VSS+20 V
Output voltage range, VOREGOUT VSS–0.3 VSS+6 V
Maximum cell balancing current,
each cell VC0 – VC5 50 mA
Junction temperature, TJ–65 150 °C
Storage temperature, TSTG –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Stresses applied above VIN(DC) and below VIN(SHORT) should be limited to less than 100 hours over the lifetime of the device. These
stresses may occur during brief transient events but DC voltages in this range should not be applied.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1) ±1000 V
V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2) ±250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT Supply voltage Voltage on BAT pin (normal
operation) 3 27.5 V
VBAT(UVLO) Under voltage lockout level Falling voltage on BAT
causing device reset 2.5 V
VWAKEONTS Wake on TS voltage Voltage on BAT pin in valid
range 0.65 1.2 V
VWAKEONVC0 Wake on VC0 voltage Voltage on BAT pin in valid
range 0.65 1.2 V
VIN Input voltage range ALERT, SCL, SDA 0 5.5 V
VIN
Input voltage range (with ADC
measurements) TS –0.2 1.8 V
VIN Input voltage range SRP, SRN, SRP-SRN (while
measuring current) –0.2 0.2 V
VIN Input voltage range SRP, SRN (without
measuring current) –0.2 1.8 V
VIN Input voltage range(3) VVC0 –0.2 3.0 V
VIN Input voltage range VVC1
maximum of
VVC0 – 0.2 or
VSS – 0.2
VVC0 + 5.5 V
VIN Input voltage range VVC2
maximum of
VVC1 – 0.2 or
VSS – 0.2
minimum of
VVC1 + 5.5 or
VSS + 27.5
V
VIN Input voltage range VVC3B
maximum of
VVC2 – 0.2 or
VSS – 0.2
minimum of
VVC2 + 5.5 or
VSS + 27.5
V
VIN Input voltage range VVC3A
maximum of
VVC3B – 0.2 or
VSS – 0.2
minimum of
VVC3B + 0.1 or
VSS + 27.5
V
VIN Input voltage range VVC4B
maximum of
VVC3A – 0.2 or
VSS + 2.0
minimum of
VVC3A + 5.5 or
VSS + 27.5
V
VIN Input voltage range VVC4A
maximum of
VVC4B – 0.2 or
VSS + 2.0
minimum of
VVC4B + 0.1 or
VSS + 27.5
V
VIN Input voltage range VVC5
maximum of
VVC4A – 0.2 or
VSS + 2.0
minimum of
VVC4A + 5.5 or
VSS + 27.5
V
VOOutput voltage range CHG –25 27.5 V
VOOutput voltage range DSG –0.2 14 V
ICB
Cell balancing current (internal, per
cell)(3) 0 50 mA
RCExternal cell input resistance(2) (3) 10 1000 Ω
CCExternal cell input capacitance(2) (3) 0.1 10 µF
Rf
External supply filter resistance
(BAT pin)(3) 50 1000 Ω
Cf
External supply filter capacitance
(BAT pin)(3) 1 40 µF
Rfilt Sense resistor filter resistance(3) 100 200 Ω
CREGSRC REGSRC capacitance(3) 1 µF
RTS
External thermistor nominal
resistance at 25°C 10 kΩ
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6.3 Recommended Operating Conditions (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TOPR
Junction temperature during
operation(1) –40 110 °C
(1) Power dissipated within device should be limited to ensure junction temperature remains within specification during operation.
(2) External cell input resistance times external input capacitance should be limited to 200 µs or below.
(3) Specified by design
6.4 Thermal Information
THERMAL METRIC(1)
BQ76905
UNITRGR (QFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 47.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.9 °C/W
RθJC(bottom) Junction-to-case (bottom) thermal resistance 8.3 °C/W
RθJB Junction-to-board thermal resistance 23.4 °C/W
ΨJT Junction-to-top characterization parameter 1.4 °C/W
ΨJB Junction-to-board characterization parameter 23.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Supply Current
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INORMAL Normal Mode
Regular measurements and protections active,
REGOUT = 3.3 V with no load, CHG =
ON, DSG = ON, Settings:Configuration:Power
Config[IADCSPEED] =
0x0, Settings:Configuration:Power
Config[CVADCSPEED] = 0x0, no
communication
146 µA
ISLEEP SLEEP Mode
Periodic protections and monitoring, no pack
current, REGOUT = OFF, CHG = OFF, DSG
= ON, no communication, Power:Sleep:Voltage
Time = 5 s
5.9 µA
IDEEPSLEEP DEEPSLEEP Mode No monitoring or protections, REGOUT = 3.3 V
with no load, LFO = OFF, no communication 2.9 µA
ISHUTDOWN SHUTDOWN Mode All blocks powered down, no monitoring or
protections, no communication 1 2 µA
6.6 Digital I/O
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input SCL, SDA 1.23 5.5 V
VIL Low-level input SCL, SDA 0.53 V
VOL Output voltage low ALERT, SCL, SDA, VBAT ≥ 3 V, IOL = 5
mA, 10-pF load 0.4 V
CIN Input capacitance(1) ALERT, SCL, SDA 2 pF
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6.6 Digital I/O (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILKG Input leakage current ALERT, SCL, SDA, device in
SHUTDOWN mode 1 µA
(1) Specified by design
6.7 REGOUT LDO
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREGOUT_1.8_LOW
Regulator voltage (nominal 1.8-V
setting)
VBAT, VREGSRC = 3.0 V,
IREGOUT = 10 mA 1.62 1.8 1.92 V
VREGOUT_1.8
Regulator voltage (nominal 1.8-V
setting)(1)
VBAT ≥ 3.0 V, VREGSRC ≥ 3.8 V,
IREGOUT = 0 mA to 20 mA 1.62 1.8 1.92 V
VREGOUT_2.5_LOW
Regulator voltage (nominal 2.5-V
setting)(1)
VBAT, VREGSRC = 3.0 V,
IREGOUT = 10 mA 2.25 2.5 2.75 V
VREGOUT_2.5
Regulator voltage (nominal 2.5-V
setting)(1)
VBAT ≥ 3.0 V, VREGSRC ≥ 3.8 V,
IREGOUT = 0 mA to 20 mA 2.25 2.5 2.75 V
VREGOUT_3.0
Regulator voltage (nominal 3.0-V
setting)(1)
VBAT ≥ 3.0 V, VREGSRC ≥ 3.8 V,
IREGOUT = 0 mA to 20 mA 2.7 3.0 3.3 V
VREGOUT_3.3
Regulator voltage (nominal 3.3-V
setting)(1)
VBAT ≥ 3.0 V, VREGSRC ≥ 4.2 V,
IREGOUT = 0 mA to 20 mA 3 3.3 3.6 V
VREGOUT_5.0
Regulator voltage (nominal 5.0-V
setting)(1)
VBAT ≥ 3.0 V, VREGSRC ≥ 5.5 V,
IREGOUT = 0 mA to 20 mA 4.5 5.0 5.5 V
ΔVO(TEMP) Regulator output over temperature
ΔVREGOUT vs (VREGOUT at
25°C, IREGOUT = 20 mA, VBAT
= 5.5 V, VREGOUT set to
nominal 3.3-V setting)
±0.015% % / ℃
ΔVO(LINE) Line regulation(1)
ΔVREGOUT vs (VREGOUT at
25°C, VBAT = 4.2 V, IREGOUT
= 5 mA), as VBAT varies from
4.2 V to 27.5 V, VREGOUT set
to nominal 3.3-V setting
–1% 1%
ISC Regulator short-circuit current limit VREGOUT = 0 V 23 50 mA
CEXT
External capacitor REGOUT to
VSS(2) 1 µF
(1) Specified by a combination of characterization and production test
(2) Specified by design
6.8 Voltage References
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE 1
V(REF1) Internal reference voltage (1) TA = 25°C 1.1955 1.1962 1.1969 V
V(REF1DRIFT) Internal reference voltage drift (1) TA = –40°C to 110°C
±29 PPM/°C
VOLTAGE REFERENCE 2
V(REF2) Internal reference voltage (2) TA = 25°C 1.226 1.227 1.229 V
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6.8 Voltage References (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(REF2DRIFT) Internal reference voltage drift(2) TA = –40°C to 110°C ±52 PPM/°C
(1) V(REF1) is used for the ADC reference. Its effective value is determined through indirect measurement using the ADC.
(2) V(REF2) is used for the coulomb counter, LDOs, and comparator protection subsystem.
6.9 Coulomb Counter
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(CC_IN)
Input voltage range
for measurements(3) VSRP – VSRN –0.2 0.2 V
V(CC_IN)
Input voltage range
for measurements(3) VSRP, VSRN –0.2 0.2 V
B(CM_INL) Integral nonlinearity(2)
16-bit, best fit straight line over input voltage
range of –200 mV to 0 mV, using Current()
command data with Curr Gain = 32, such
that 1-LSB ≈ 7.52 µV, at 25℃
±0.42 ±1.23 LSB(1)
B(CM_INL) Integral nonlinearity(2)
16-bit, best fit straight line over input voltage
range of –200 mV to 100 mV, using Current()
command data with Curr Gain = 32, such
that 1-LSB ≈ 7.52 µV, at 25℃
±0.86 ±3.2 LSB(1)
V(CM_OFF) Offset error
16-bit, uncalibrated, using Current()
command data with Curr Gain = 32, such
that 1-LSB ≈ 7.52 µV
-1.37 0.033 1.49 µV
V(CM_OFF_DRIFT) Offset error drift(2)
16-bit, uncalibrated, using Current()
command data with Curr Gain = 32, such
that 1-LSB ≈ 7.52 µV
–0.032 0.032 µV/°C
B(CM_GAIN) Gain(2) Using 16-bit data from Current() command,
with Curr Gain = 32, VSRP – VSRN = ±0.2V 131949 132910 133981 LSB/V(1)
B(CM_GAIN) Gain drift (2) Using 16-bit data from Current() command,
with Curr Gain = 32, VSRP – VSRN = ±0.2V –19 0.72 16 LSB/V/ °C(1)
R(CM_IN)
Effective input
resistance(3) (4) 2 MΩ
(1) 1 LSB = VREF2 / (5 × 2N-1) ≈ 1.227 / (5 × 215) = 7.49 µV
(2) Specified by characterization
(3) Specified by design
(4) Average effective differential input resistance with device operating in NORMAL mode, 0.1-V differential input applied
6.10 Coulomb Counter Digital Filter
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CC1 Charge Integration Digital Filter
t(CC1_CONV) Conversion-time Single conversion 250 ms
B(CC1_RSL) Effective resolution(1) (2)
Single conversion, DC inputs from –
200 mV to 0 mV across VSRP – VSRN,
at 25℃.
15.5 bits
CC2 Current Measurement Digital Filter
t(CM_CONV) Conversion-time in slow mode
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x0
2.93 ms
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6.10 Coulomb Counter Digital Filter (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = –40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(CM_CONV_MEDSLOW)
Conversion-time in medium
slow mode
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x1
1.46 ms
t(CM_CONV_MEDFAST)
Conversion-time in medium
fast mode
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x2
732 µs
t(CM_CONV_FAST) Conversion-time in fast mode
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x3
366 µs
B(CM_RES)
Effective resolution in slow
mode(1) (2)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x0
15.5 16 bits
B(CM_RES_MEDSLOW)
Effective resolution in medium
slow mode(1)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x1
15.7 bits
B(CM_RES_MEDFAST)
Effective resolution in medium
fast mode(1)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x2
14.9 bits
B(CM_RES_FAST)
Effective resolution in fast
mode(1)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] = 0x3
12.9 bits
B(CM_LP_RES)
Effective resolution in slow
mode and low power
mode(1) (2)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] =
0x0, Settings:Configuration:DA
Config[CCMODE] = 0x2
15.5 16 bits
B(CM_LP_RES_MEDSLOW)
Effective resolution in medium
slow mode and low power
mode(1)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] =
0x1, Settings:Configuration:DA
Config[CCMODE] = 0x2
15.7 bits
B(CM_LP_RES_MEDFAST)
Effective resolution in medium
fast mode and low power
mode(1)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] =
0x2, Settings:Configuration:DA
Config[CCMODE] = 0x2
14.9 bits
B(CM_LP_RES_FAST)
Effective resolution in fast
mode and low power mode(1)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[IADCSPEED] =
0x3, Settings:Configuration:DA
Config[CCMODE] = 0x2
12.9 bits
(1) Effective resolution is defined as the resolution such that the data exhibits 1-sigma variation within ±1-LSB.
(2) Specified by characterization
6.11 Current Wake Detector
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 1, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 186 271 355 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 2, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 670 794 921 µV
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6.11 Current Wake Detector (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 3, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 1145 1317 1503 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 4, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 1594 1838 2089 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 5, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 2056 2364 2676 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 6, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 2516 2890 3276 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 7, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 3000 3419 3851 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 8, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 3460 3942 4443 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 9, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 3893 4466 5045 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 10, positive threshold
(charging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise 4386 4994 5627 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 1, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 88 275 462 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 2, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 581 794 978 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 3, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 1050 1317 1537 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 4, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 1527 1836 2106 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 5, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 1974 2360 2711 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 6, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 2483 2885 3290 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 7, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 2897 3412 3885 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 8, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise 3357 3933 4498 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 9, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise. 3793 4458 5062 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 10, positive threshold
(charging current) (1)
TA = –40°C to 110°C. Measured using
averaged data to remove effects of noise. 4261 4986 5654 µV
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6.11 Current Wake Detector (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 1, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -719 -635 -546 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 2, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -1234 -1118 -1005 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 3, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -1736 -1605 -1469 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 4, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -2262 -2088 -1917 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 5, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -2794 -2579 -2354 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 6, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -3324 -3067 -2805 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 7, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -3849 -3552 -3245 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 8, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -4369 -4037 -3704 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 9, negative threshold
(discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -4913 -4527 -4129 µV
VWAKE_THR
Wakeup voltage threshold (VSRP
– VSRN), setting = 10, negative
threshold (discharging current) (1)
TA = –20°C to 65°C. Measured using
averaged data to remove effects of noise -5425 -5012 -4577 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 1, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -862 -630 -369 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 2, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -1340 -1113 -865 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 3, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -1887 -1600 -1284 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 4, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -2387 -2087 -1765 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 5, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -2949 -2575 -2179 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 6, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -3487 -3064 -2622 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 7, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -3991 -3548 -3083 µV
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 8, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -4599 -4033 -3420 µV
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6.11 Current Wake Detector (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE_THR
Wakeup voltage threshold (VSRP –
VSRN), setting = 9, negative threshold
(discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -5067 -4521 -3918 µV
VWAKE_THR
Wakeup voltage threshold (VSRP
– VSRN), setting = 10, negative
threshold (discharging current) (1)
TA = -40°C to 110°C. Measured using
averaged data to remove effects of noise -5580 -5011 -4415 µV
tWAKE Measurement interval 2.44 ms
(1) Specified by a combination of characterization and production test
6.12 Analog-to-Digital Converter
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(ADC_IN_CELLS)
Input voltage range
(differential cell input
mode) (2) (4)
Internal reference (Vref = VREF1) –0.2 5.5 V
V(ADC_IN)
Input voltage ran ge
(ADCIN measurement
mode)(2) (6)
Internal reference (Vref =
VREF1, Settings:Configuration:DA
Config[TSMODE] = 1), applicable to ADCIN
measurements using the TS pin
–0.2 1.8 V
V(ADC_IN_TS)
Input voltage range
(external thermistor
measurement mode)
(2) (5)
Regulator reference (Vref =
VREG18, Settings:Configuration:DA
Config[TSMODE] = 0), applicable to external
thermistor measurement using the TS pin
–0.2 1.8 V
V(ADC_IN_DIV)
Input voltage range
(divider measurement
mode)(2) (7)
Internal reference (Vref = VREF1), applicable
to divider measurements using the VC5 pin
relative to VSS.
2.0 27.5 V
B(ADC_OFF_CELL)
Differential cell offset
error
16-bit, uncalibrated, with VC5 - VC4A = 0 V,
VC4A = 27 V, using raw ADC codes 2.4 LSB (4)
B(ADC_OFF_DRIFT_CELL)
Differential cell offset
error drift(3)
16-bit, uncalibrated, with VC5 - VC4A = 0 V,
VC4A = 27 V, using raw ADC codes, over
-20°C to +65°C
-0.26 0.26 LSB/°C (4)
16-bit, uncalibrated, with VC5 - VC4A = 0 V,
VC4A = 27 V, using raw ADC codes, over
-40°C to +110°C
-0.41 0.41 LSB/°C (4)
B(ADC_OFF) ADCIN offset error 16-bit, uncalibrated, using ADCIN mode on
TS pin -0.5 LSB(6)
B(ADC_OFF_DIV) Divider offset error 16-bit, uncalibrated, using divider mode on
VC5 -3.7 LSB(7)
G(ADC_TS_REG18)
Gain of ADC TS pin
measurement using
Vref = VREG18 (9)
Reported digital code = G(ADC_TS_REG18) ×
VTS / VREG18. 16-bit, uncalibrated, using TS
pin, input range from 0.1 V to 1.8 V.
19083 19405 19750 N/A (5)
G(ADC_TS_ADCIN)
Gain of ADC TS pin
measurement using
Vref = VREF1 (9)
Reported digital code = G(ADC_TS_ADCIN) ×
VTS. 16-bit, uncalibrated, using TS pin, input
range from 0.1 V to 1.8 V.
15768 16027 16261 LSB/V (6)
G(ADC_CELL_RAW)
Raw gain of ADC cell
voltage measurement
(9)
Gain measured 16-bit, over input voltage
range 1.0 V to 5.0 V, differential cell input
mode on VC5 - VC4A, uncalibrated, using
raw ADC codes.
5458 5479 5502 LSB/V (4)
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6.12 Analog-to-Digital Converter (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
B(ADC_GAIN_DRIFT) Gain drift(3)
Gain measured 16-bit using Cell 5, VC5 -
VC4A = 4.5 V. VC5 = 23 V, uncalibrated,
using raw ADC codes, over -20°C to +65°C
-0.17 0.23 LSB/V/
°C (4)
Gain measured 16-bit using Cell 5, VC5 -
VC4A = 4.5 V. VC4A = 23 V, uncalibrated,
using raw ADC codes, over -40°C to +110°C
-0.32 0.23 LSB/V/
°C (4)
R(ADC_IN_CELL)
Effective input
resistance(8) Differential cell input mode on VC5 - VC4A 4 MΩ
R(ADC_IN_TOS)
Effective input
resistance
Divider measurement on VC5 pin (only active
while the pin is being measured) 600 kΩ
I(LEAKAGE) Pin leakage current (3)
Input current per pin into VC1 ~ VC5, BAT,
REGSRC, with no conversions, stack biased
with 5 V / cell, VBAT = 27.5 V, device in
SHUTDOWN mode.
2 µA
B(ADC_RES_SLOW)
Effective resolution
with slow speed
setting(1) (3)
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] = 0x0, using TS
input in ADCIN mode.
14 16 bits
B(ADC_RES_MEDSLOW)
Effective resolution
with medium slow
speed setting(1)
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] = 0x1, using TS
input in ADCIN mode.
15.5 bits
B(ADC_RES_MEDFAST)
Effective resolution
with medium fast
speed setting(1)
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] = 0x2, using TS
input in ADCIN mode.
14.5 bits
B(ADC_RES_FAST)
Effective resolution
with fast speed
setting(1)
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] = 0x3, using TS
input in ADCIN mode.
12 bits
t(ADC_CONV_SLOW) Conversion-time
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] and [IADCSPEED]
= 0x0
2.93 ms
t(ADC_CONV_MEDSLOW)
Conversion-time in
medium slow mode
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] and [IADCSPEED]
= 0x1
1.46 ms
t(ADC_CONV_MEDFAST)
Conversion-time in
medium fast mode
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] and [IADCSPEED]
= 0x2
732 µs
t(ADC_CONV_FAST)
Conversion-time in
fast mode
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[CVADCSPEED] and [IADCSPEED]
= 0x3
366 µs
VCELL(ACC)
Cell voltage
measurement
accuracy (9)
-0.2 V < VVC(x) - VVC(x-1) < 4.5 V, TA = 25°C, 1
≤ x ≤ 5 -3.8 3.9 mV
-0.2 V < VVC(x) - VVC(x-1) < 4.5 V, TA = –20°C
to 65°C, 1 ≤ x ≤ 5 -7.6 6.5 mV
–0.2 V < VVC(x) - VVC(x-1) < 4.5 V, TA = -40°C
to 110°C, 1 ≤ x ≤ 5 -9.8 9.8 mV
–0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C
to 110°C, 1 ≤ x ≤ 5 -12.1 11.8 mV
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6.12 Analog-to-Digital Converter (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSTACK(ACC)
Stack voltage (VVC5 -
VVSS) measurement
accuracy (9)
3 V ≤ VVC5 - VVSS ≤ 27.5 V, TA = -40°C to
110°C –220 180 mV
(1) Effective resolution is defined as the resolution such that the data exhibits 1-sigma variation within ±1-LSB.
(2) Specified by design
(3) Specified by characterization
(4) The 16-bit LSB size of the differential cell voltage raw codes measurement is given by 1 LSB = 1 V / G(ADC_CELL_RAW) ≈ 1 V / 5479
LSB/V = 182.5 µV
(5) Assuming a nominal value of VREG18 = 1.8 V, the 16-bit LSB size of the TS pin voltage measurement in thermistor mode is given by 1
LSB = VREG18 / G(ADC_TS_REG18) ≈ 1.8 V / 19405 = 93 µV
(6) The 16-bit LSB size of the TS pin voltage measurement in ADCIN mode is given by 1 LSB = VREG18 / G(ADC_TS_ADCIN) ≈ 1 V / 16027 =
62 µV
(7) The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 50 x VREF1 / 2N-1 ≈ 50 x 1.1962 / 215 = 1.825 mV
(8) Average effective differential input resistance with device operating in NORMAL mode, cell balancing disabled, and a 5 V differential
voltage applied.
(9) Specified by a combination of characterization and production test
6.13 Cell Balancing
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R(CB) Internal cell balancing resistance(1) RDS(ON) for internal FET switch at VVC(n) -
VVC(n-1) = 1.5 V, 1 ≤ n ≤ 5 53 93 200 Ω
(1) Cell balancing must be controlled to limit the current based on the absolute maximum allowed current, and to avoid exceeding the
recommended device operating temperature. This can be accomplished by appropriate sizing of the offchip cell input resistors and
limiting the number of cells that can be balanced simultaneously.
6.14 Internal Temperature Sensor
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(TEMP) Internal temperature sensor voltage drift ΔVBE measurement 0.410 mV/°C
6.15 Thermistor Measurement
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R(TS_PU)
Internal pullup
resistance at 25°C(1) 19.75 20 20.25 kΩ
R(TS_PU_DRIFT)
Internal pullup
resistance change
over temperature (1)
(2)
Change over -20°C/+65°C vs value at 25°C
for nominal 20-kΩ –36 28 Ω
R(TS_PU_DRIFT)
Internal pullup
resistance change
over temperature (1)
(2)
Change over -40°C/+110°C vs value at 25°C
for nominal 20-kΩ –53 98 Ω
(1) The internal pullup resistance includes only the resistance between the REG18 internal LDO and the point where the voltage is sensed
by the ADC.
(2) Specified by characterization
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6.16 Hardware Overtemperature Detector
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(OTSD)
Hardware overtemperature detector
threshold(1) 118 132 °C
(1) Specified by design
6.17 Internal Oscillator
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-frequency Oscillator
fLFO Operating frequency Full speed setting 262.277 kHz
Low speed setting 32.770 kHz
fLFOF(ERR
)
Frequency drift, full speed mode(1)
Change in frequency vs value at 25°C, TA
= –20°C to +65°C –1.2 ±0.55 1.2 %
Change in frequency vs value at 25°C, TA
= –40°C to +110°C. –2.1 ±1.0 2.3 %
fLFOS(ERR
)
Frequency drift, low speed mode(1) Change in frequency vs value at 25°C, TA
= –20°C to +65°C. -1.0 ±0.33 1.0 %
fLFOS(ERR
)
Frequency drift, low speed mode(1) Change in frequency vs value at 25°C, TA
= –40°C to +110°C. -1.6 ±0.67 1.9 %
fLFO(FAIL) Failure detection frequency
Refers to the LFO frequency if
in low speed mode, or the LFO
frequency divided by 8 if in full speed
mode. Detects oscillator failure if the
frequency falls below this level.
11 14.1 18 kHz
(1) Specified by characterization
6.18 Charge and Discharge FET Drivers
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(FETON_DSG) DSG driver enabled VREGSRC ≥ 12 V, CL= 20 nF 10.5 11.5 13 V
V(FETON_CHG) CHG driver enabled VREGSRC ≥ 12 V, CL= 20 nF 10 11 12 V
V(FETON_LOBAT_DSG) DSG driver enabled VREGSRC < 12 V, CL = 20 nF VREGSRC
– 1.0 VREGSRC V
V(FETON_LOBAT_CHG) CHG driver enabled VREGSRC < 12 V, CL = 20 nF VREGSRC
– 1.75 VREGSRC V
t(CHG_ON)
CHG FET driver rise
time
CHG CL = 20 nF, RGATE = 100 Ω, VREGSRC =
12 V, 0.5 V to 5 V 50 85 µs
t(DSG_ON)
DSG FET driver rise
time
DSG CL = 20 nF, RGATE = 100 Ω, VREGSRC =
12 V, 0.5 V to 5 V 35 55 µs
t(CHG_OFF)
CHG FET driver fall
time
CHG CL = 20 nF, RGATE = 100 Ω, VREGSRC =
12 V, 80% to 20% of V(FETON_CHG)
24 35 µs
t(DSG_OFF)
DSG FET driver fall
time
DSG CL = 20 nF, RGATE = 100 Ω, VREGSRC =
12 V, 80% to 20% of V(FETON_DSG)
2 3 µs
I(CHG_ON)
CHG FET driver
output current
CHG enabled and pin held at 8 V, VREGSRC =
12 V 1 mA
I(DSG_ON)
DSG FET driver
output current
DSG enabled and pin held at 8 V, VREGSRC =
12 V 1.56 mA
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6.18 Charge and Discharge FET Drivers (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R(DSG_OFF)
DSG FET driver off
resistance DSG off and pin held at 100 mV 15 30 Ω
V(CHG_DETECT)
CHG detector
threshold CHG pin voltage rising 1.2 1.8 V
V(CHG_DET_HYS)
CHG detector
hysteresis 0.95 V
6.19 Comparator-Based Protection Subsystem
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(SCD)
Short circuit in discharge voltage
threshold range
Nominal settings, threshold based on
VSRP – VSRN
–10,
–20,
–40,
–60,
–80,
–100,
–125,
–150,
–175,
–200,
–250,
–300,
–350,
–400,
–450,
–500
mV
V(SCD_ACC)
Short circuit in discharge voltage
threshold detection accuracy (2)
–10 mV setting –36 22
% of
nominal
threshold
–20 mV setting –19 12
% of
nominal
threshold
–40 mV setting –14 6
% of
nominal
threshold
Settings –60 mV to -500 mV –11 6
% of
nominal
threshold
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6.19 Comparator-Based Protection Subsystem (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(SCD_DLY)
Short circuit in discharge detection
delay(1)
Fastest setting (with 3 mV overdrive) 8 µs
Fastest setting (with 25 mV overdrive) 0.6 µs
Setting for 15 µs (with 3 mV overdrive) 20 28 µs
Setting for 15 µs (with 25 mV overdrive) 20 µs
Settings for 31 µs (with 25 mV overdrive) 14 35 µs
Settings for 61 µs (with 25 mV overdrive) 42 66 µs
Settings for 122 µs (with 25 mV
overdrive) 102 130 µs
Settings for 244 µs (with 25 mV
overdrive) 218 258 µs
Settings for 488 µs (with 25 mV
overdrive) 452 510 µs
Settings for 977 µs (with 25 mV
overdrive) 920 1018 µs
Settings for 1953 µs (with 25 mV
overdrive) 1860 2034 µs
Settings for 3906 µs (with 25 mV
overdrive) 3735 4065 µs
Setting for 7797 µs (with 25 mV
overdrive) 7470 8112 µs
V(OCC)
Overcurrent in charge (OCC) voltage
threshold range
Nominal settings, threshold based on
VSRP – VSRN
3 mV to
123 mV
in 2 mV
steps
mV
V(OCC_ACC)
Overcurrent in charge (OCC) voltage
threshold accuracy (2) Settings 3 mV to 19 mV –1.17 1.32 mV
V(OCC_ACC)
Overcurrent in charge (OCC) voltage
threshold accuracy (2) Settings 21 mV to 55 mV -1.68 2.99 mV
V(OCC_ACC)
Overcurrent in charge (OCC) voltage
threshold accuracy (2) Settings 57 mV to 123 mV -1.61 4.10 mV
V(OCD)
Overcurrent in discharge (OCD1,
OCD2) voltage threshold ranges
Nominal settings, thresholds based on
VSRP – VSRN
–4 mV to
–200 mV
in 2 mV
steps
mV
V(OCD_ACC)
Overcurrent (OCD1, OCD2) detection
voltage threshold accuracy (2)
Settings -4 mV to -18 mV –1.23 0.84 mV
Settings -20 mV to -56 mV –2.84 1.59 mV
Settings -58 mV to -100 mV -2.15 2.58 mV
Settings -102 mV to -200 mV -2,86 4,19 mV
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6.19 Comparator-Based Protection Subsystem (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(OC_DLY)
Overcurrent (OCC, OCD1, OCD2)
detection delay (independent delay
setting for each protection)
Fastest setting 0.46 ms
Nominal settings, low range
1.22 ms
to 20.435
ms in
0.305 ms
steps
ms
Nominal settings, medium low range
22.875
ms to
176.595
ms in
2.441 ms
steps
ms
Nominal settings, medium high range
181.475
ms to
488.915
ms in
4.883 ms
steps
ms
Nominal settings, high range
498.675
ms to
1103.795
ms in
9.766 ms
steps
ms
V(OC_DLY)
Overcurrent (OCC, OCD1, OCD2)
detection delay accuracy(1)
Fastest setting -0.35 0.35 ms
Nominal settings, low range -1.2 0.90 ms
Nominal settings, medium low range -7.5 7.2 ms
Nominal settings, medium high range -20 20 ms
Nominal settings, high range -45 45 ms
(1) Specified by design
(2) Specified by a combination of characterization and production test
6.20 Timing Requirements—I2C Interface, 100-kHz Mode
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL Clock operating frequency(1) SCL duty cycle = 50% 100 kHz
tHD:STA START condition hold time(1) 4.0 µs
tLOW Low period of the SCL clock(1) 4.7 µs
tHIGH High period of the SCL clock(1) 4.0 µs
tSU:STA Setup repeated START(1) 4.7 µs
tHD:DAT Data hold time (SDA input)(1) 0 ns
tSU:DAT Data setup time (SDA input)(1) 250 ns
trClock rise time(1) 10% to 90% 1000 ns
tfClock fall time(1) 90% to 10% 300 ns
tSU:STO Setup time STOP condition(1) 4.0 µs
tBUF Bus free time STOP to START(1) 4.7 µs
tRST I2C bus reset(1) Bus interface is reset if SCL is detected
low for this duration 1.9 2.1 s
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6.20 Timing Requirements—I2C Interface, 100-kHz Mode (continued)
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RPULLUP Pullup resistor(1) Pullup voltage rail ≤ 5 V 1.1 kΩ
(1) Specified by design
6.21 Timing Requirements—I2C Interface, 400-kHz Mode
Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 110°C and VBAT = 3 V
to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL Clock operating frequency(1) SCL duty cycle = 50% 400 kHz
tHD:STA START condition hold time(1) 0.6 µs
tLOW Low period of the SCL clock(1) 1.3 µs
tHIGH High period of the SCL clock(1) 600 ns
tSU:STA Setup repeated START(1) 600 ns
tHD:DAT Data hold time (SDA input)(1) 0 ns
tSU:DAT Data setup time (SDA input)(1) 100 ns
trClock rise time(1) 10% to 90% 300 ns
tfClock fall time(1) 90% to 10% 300 ns
tSU:STO Setup time STOP condition(1) 0.6 µs
tBUF Bus free time STOP to START(1) 1.3 µs
tRST I2C bus reset(1) Bus interface is reset if SCL is detected
low for this duration 1.9 2.1 s
RPULLUP Pullup resistor(1) Pullup voltage rail ≤ 5 V 1.1 kΩ
(1) Specified by design
6.22 Timing Diagram
SCL
SDA
tHD;STA
tLOW
tr
tHD;DAT
tHIGH
tf
tSU;DAT
tSU;STA tSU;STO
tf
START REPEATED
START
STOP
tHD;STA
START
tSP
tr
tBUF
Figure 6-1. I2C Communications Interface Timing
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