Texas Instruments AM1808 Product manual

AM1808/AM1810
Sitara ARM Microprocessor
Technical Reference Manual
Literature Number: SPRUH82C
April 2013–Revised September 2016

2SPRUH82C–April 2013–Revised September 2016
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Contents
Contents
Preface....................................................................................................................................... 80
1 Overview........................................................................................................................... 81
1.1 Introduction.................................................................................................................. 82
1.2 ARM Subsystem............................................................................................................ 82
2 ARM Subsystem................................................................................................................. 83
2.1 Introduction.................................................................................................................. 84
2.2 Operating States/Modes................................................................................................... 85
2.3 Processor Status Registers............................................................................................... 85
2.4 Exceptions and Exception Vectors....................................................................................... 86
2.5 The 16-BIS/32-BIS Concept .............................................................................................. 87
2.6 16-BIS/32-BIS Advantages ............................................................................................... 87
2.7 Co-Processor 15 (CP15) .................................................................................................. 88
2.7.1 Addresses in an ARM926EJ-S System ........................................................................ 88
2.7.2 Memory Management Unit (MMU).............................................................................. 88
2.7.3 Caches and Write Buffer ........................................................................................ 89
3 System Interconnect........................................................................................................... 90
3.1 Introduction.................................................................................................................. 91
3.2 System Interconnect Block Diagram..................................................................................... 92
4 System Memory ................................................................................................................. 93
4.1 Introduction.................................................................................................................. 94
4.2 ARM Memories ............................................................................................................. 94
4.3 Peripherals .................................................................................................................. 94
5 Memory Protection Unit (MPU)............................................................................................. 95
5.1 Introduction.................................................................................................................. 96
5.1.1 Purpose of the MPU .............................................................................................. 96
5.1.2 Features ............................................................................................................ 96
5.1.3 Block Diagram ..................................................................................................... 96
5.1.4 MPU Default Configuration....................................................................................... 97
5.2 Architecture ................................................................................................................. 97
5.2.1 Privilege Levels.................................................................................................... 97
5.2.2 Memory Protection Ranges...................................................................................... 98
5.2.3 Permission Structures ............................................................................................ 99
5.2.4 Protection Check................................................................................................. 100
5.2.5 MPU Register Protection ....................................................................................... 100
5.2.6 Invalid Accesses and Exceptions.............................................................................. 100
5.2.7 Reset Considerations ........................................................................................... 100
5.2.8 Interrupt Support................................................................................................. 101
5.2.9 Emulation Considerations ...................................................................................... 101
5.3 MPU Registers............................................................................................................ 102
5.3.1 Revision Identification Register (REVID) ..................................................................... 104
5.3.2 Configuration Register (CONFIG) ............................................................................. 104
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................ 105
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT).......................................................... 106
5.3.5 Interrupt Enable Set Register (IENSET)...................................................................... 107

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5.3.6 Interrupt Enable Clear Register (IENCLR) ................................................................... 107
5.3.7 Fixed Range Start Address Register (FXD_MPSAR)....................................................... 108
5.3.8 Fixed Range End Address Register (FXD_MPEAR)........................................................ 108
5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)............................... 109
5.3.10 Programmable Range nStart Address Registers (PROGn_MPSAR)................................... 110
5.3.11 Programmable Range nEnd Address Registers (PROGn_MPEAR).................................... 111
5.3.12 Programmable Range nMemory Protection Page Attributes Register (PROGn_MPPA)............. 112
5.3.13 Fault Address Register (FLTADDRR)........................................................................ 113
5.3.14 Fault Status Register (FLTSTAT)............................................................................. 114
5.3.15 Fault Clear Register (FLTCLR) ............................................................................... 115
6 Device Clocking................................................................................................................ 116
6.1 Overview................................................................................................................... 117
6.2 Frequency Flexibility...................................................................................................... 119
6.3 Peripheral Clocking....................................................................................................... 120
6.3.1 USB Clocking..................................................................................................... 120
6.3.2 DDR2/mDDR Memory Controller Clocking................................................................... 122
6.3.3 EMIFA Clocking.................................................................................................. 124
6.3.4 EMAC Clocking .................................................................................................. 125
6.3.5 uPP Clocking..................................................................................................... 127
6.3.6 McASP Clocking ................................................................................................. 128
6.3.7 I/O Domains ...................................................................................................... 129
7 Phase-Locked Loop Controller (PLLC) ................................................................................ 130
7.1 Introduction ................................................................................................................ 131
7.2 PLL Controllers............................................................................................................ 131
7.2.1 Device Clock Generation ....................................................................................... 133
7.2.2 Steps for Programming the PLLs.............................................................................. 134
7.3 PLLC Registers ........................................................................................................... 136
7.3.1 PLLC0 Revision Identification Register (REVID) ............................................................ 137
7.3.2 PLLC1 Revision Identification Register (REVID) ............................................................ 138
7.3.3 Reset Type Status Register (RSTYPE)....................................................................... 138
7.3.4 PLLC0 Reset Control Register (RSCTRL) ................................................................... 139
7.3.5 PLLC0 Control Register (PLLCTL) ............................................................................ 140
7.3.6 PLLC1 Control Register (PLLCTL) ............................................................................ 141
7.3.7 PLLC0 OBSCLK Select Register (OCSEL) .................................................................. 142
7.3.8 PLLC1 OBSCLK Select Register (OCSEL) .................................................................. 143
7.3.9 PLL Multiplier Control Register (PLLM)....................................................................... 144
7.3.10 PLLC0 Pre-Divider Control Register (PREDIV)............................................................. 144
7.3.11 PLLC0 Divider 1 Register (PLLDIV1) ........................................................................ 145
7.3.12 PLLC1 Divider 1 Register (PLLDIV1) ........................................................................ 145
7.3.13 PLLC0 Divider 2 Register (PLLDIV2) ........................................................................ 146
7.3.14 PLLC1 Divider 2 Register (PLLDIV2) ........................................................................ 146
7.3.15 PLLC0 Divider 3 Register (PLLDIV3) ........................................................................ 147
7.3.16 PLLC1 Divider 3 Register (PLLDIV3) ........................................................................ 147
7.3.17 PLLC0 Divider 4 Register (PLLDIV4) ........................................................................ 148
7.3.18 PLLC0 Divider 5 Register (PLLDIV5) ........................................................................ 148
7.3.19 PLLC0 Divider 6 Register (PLLDIV6) ........................................................................ 149
7.3.20 PLLC0 Divider 7 Register (PLLDIV7) ........................................................................ 149
7.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)............................................................. 150
7.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)............................................................. 150
7.3.23 PLL Post-Divider Control Register (POSTDIV)............................................................. 151
7.3.24 PLL Controller Command Register (PLLCMD) ............................................................. 151
7.3.25 PLL Controller Status Register (PLLSTAT) ................................................................. 152
7.3.26 PLLC0 Clock Align Control Register (ALNCTL) ............................................................ 153

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7.3.27 PLLC1 Clock Align Control Register (ALNCTL) ............................................................ 154
7.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)............................................. 155
7.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)............................................. 156
7.3.30 PLLC0 Clock Enable Control Register (CKEN)............................................................. 157
7.3.31 PLLC1 Clock Enable Control Register (CKEN)............................................................. 157
7.3.32 PLLC0 Clock Status Register (CKSTAT).................................................................... 158
7.3.33 PLLC1 Clock Status Register (CKSTAT).................................................................... 159
7.3.34 PLLC0 SYSCLK Status Register (SYSTAT)................................................................ 160
7.3.35 PLLC1 SYSCLK Status Register (SYSTAT)................................................................ 161
7.3.36 Emulation Performance Counter 0 Register (EMUCNT0)................................................. 162
7.3.37 Emulation Performance Counter 1 Register (EMUCNT1)................................................. 162
8 Power and Sleep Controller (PSC) ...................................................................................... 163
8.1 Introduction ................................................................................................................ 164
8.2 Power Domain and Module Topology.................................................................................. 164
8.2.1 Power Domain States........................................................................................... 166
8.2.2 Module States.................................................................................................... 167
8.3 Executing State Transitions ............................................................................................. 169
8.3.1 Power Domain State Transitions .............................................................................. 169
8.3.2 Module State Transitions ....................................................................................... 169
8.4 IcePick Emulation Support in the PSC................................................................................. 170
8.5 PSC Interrupts............................................................................................................. 170
8.5.1 Interrupt Events .................................................................................................. 170
8.5.2 Interrupt Registers............................................................................................... 171
8.5.3 Interrupt Handling................................................................................................ 172
8.6 PSC Registers............................................................................................................. 173
8.6.1 Revision Identification Register (REVID) ..................................................................... 174
8.6.2 Interrupt Evaluation Register (INTEVAL) ..................................................................... 174
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)................................... 175
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)................................... 175
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ...................................... 176
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ...................................... 176
8.6.7 Power Error Pending Register (PERRPR) ................................................................... 177
8.6.8 Power Error Clear Register (PERRCR)....................................................................... 177
8.6.9 Power Domain Transition Command Register (PTCMD)................................................... 178
8.6.10 Power Domain Transition Status Register (PTSTAT)...................................................... 179
8.6.11 Power Domain 0 Status Register (PDSTAT0).............................................................. 180
8.6.12 Power Domain 1 Status Register (PDSTAT1).............................................................. 181
8.6.13 Power Domain 0 Control Register (PDCTL0)............................................................... 182
8.6.14 Power Domain 1 Control Register (PDCTL1)............................................................... 183
8.6.15 Power Domain 0 Configuration Register (PDCFG0)....................................................... 184
8.6.16 Power Domain 1 Configuration Register (PDCFG1)....................................................... 185
8.6.17 Module Status nRegister (MDSTATn)....................................................................... 186
8.6.18 PSC0 Module Control nRegister (modules 0-15) (MDCTLn)............................................ 187
8.6.19 PSC1 Module Control nRegister (modules 0-31) (MDCTLn)............................................ 188
9 Power Management........................................................................................................... 189
9.1 Introduction ................................................................................................................ 190
9.2 Power Consumption Overview.......................................................................................... 190
9.3 PSC and PLLC Overview................................................................................................ 190
9.4 Features.................................................................................................................... 191
9.5 Clock Management....................................................................................................... 192
9.5.1 Module Clock ON/OFF.......................................................................................... 192
9.5.2 Module Clock Frequency Scaling.............................................................................. 192
9.5.3 PLL Bypass and Power Down ................................................................................. 192

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9.6 ARM Sleep Mode Management ........................................................................................ 193
9.6.1 ARM Wait-For-Interrupt Sleep Mode.......................................................................... 193
9.6.2 ARM Clock OFF.................................................................................................. 194
9.6.3 ARM Subsystem Clock ON..................................................................................... 194
9.7 RTC-Only Mode........................................................................................................... 195
9.8 Dynamic Voltage and Frequency Scaling (DVFS) ................................................................... 195
9.8.1 Frequency Scaling Considerations............................................................................ 195
9.8.2 Voltage Scaling Considerations................................................................................ 196
9.9 Deep Sleep Mode......................................................................................................... 196
9.9.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up .............................. 197
9.9.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up..................................... 198
9.9.3 Deep Sleep Sequence .......................................................................................... 199
9.9.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ........................................ 200
9.10 Additional Peripheral Power Management Considerations.......................................................... 200
9.10.1 USB PHY Power Down Control .............................................................................. 200
9.10.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode................................ 201
9.10.3 SATA PHY Power Down....................................................................................... 201
9.10.4 LVCMOS I/O Buffer Receiver Disable ....................................................................... 201
9.10.5 Pull-Up/Pull-Down Disable..................................................................................... 202
10 System Configuration (SYSCFG) Module............................................................................. 203
10.1 Introduction ................................................................................................................ 204
10.2 Protection .................................................................................................................. 204
10.2.1 Privilege Mode Protection ..................................................................................... 204
10.2.2 Kicker Mechanism Protection ................................................................................. 205
10.3 Master Priority Control ................................................................................................... 205
10.4 Interrupt Support.......................................................................................................... 207
10.4.1 Interrupt Events and Requests................................................................................ 207
10.4.2 Interrupt Multiplexing........................................................................................... 207
10.5 SYSCFG Registers....................................................................................................... 207
10.5.1 Revision Identification Register (REVID) .................................................................... 209
10.5.2 Device Identification Register 0 (DEVIDR0)................................................................. 209
10.5.3 Boot Configuration Register (BOOTCFG)................................................................... 210
10.5.4 Chip Revision Identification Register (CHIPREVIDR) ..................................................... 210
10.5.5 Kick Registers (KICK0R-KICK1R)............................................................................ 211
10.5.6 Host 0 Configuration Register (HOST0CFG) ............................................................... 212
10.5.7 Interrupt Registers.............................................................................................. 213
10.5.8 Fault Registers.................................................................................................. 216
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)............................................................ 218
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)............................................. 221
10.5.11 Suspend Source Register (SUSPSRC) .................................................................... 262
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................ 265
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) .............................................................. 266
10.5.14 Chip Configuration 0 Register (CFGCHIP0)............................................................... 267
10.5.15 Chip Configuration 1 Register (CFGCHIP1)............................................................... 268
10.5.16 Chip Configuration 2 Register (CFGCHIP2)............................................................... 271
10.5.17 Chip Configuration 3 Register (CFGCHIP3)............................................................... 273
10.5.18 Chip Configuration 4 Register (CFGCHIP4)............................................................... 274
10.5.19 VTP I/O Control Register (VTPIO_CTL) ................................................................... 275
10.5.20 DDR Slew Register (DDR_SLEW).......................................................................... 277
10.5.21 Deep Sleep Register (DEEPSLEEP)....................................................................... 278
10.5.22 Pullup/Pulldown Enable Register (PUPD_ENA) .......................................................... 279
10.5.23 Pullup/Pulldown Select Register (PUPD_SEL)............................................................ 279
10.5.24 RXACTIVE Control Register (RXACTIVE)................................................................. 281

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10.5.25 Power Down Control Register (PWRDN) .................................................................. 281
11 ARM Interrupt Controller (AINTC) ....................................................................................... 282
11.1 Introduction ................................................................................................................ 283
11.2 Interrupt Mapping......................................................................................................... 283
11.3 AINTC Methodology...................................................................................................... 286
11.3.1 Interrupt Processing............................................................................................ 286
11.3.2 Interrupt Enabling............................................................................................... 287
11.3.3 Interrupt Status Checking...................................................................................... 287
11.3.4 Interrupt Channel Mapping .................................................................................... 287
11.3.5 Host Interrupt Mapping Interrupts ............................................................................ 287
11.3.6 Interrupt Prioritization .......................................................................................... 288
11.3.7 Interrupt Nesting ................................................................................................ 288
11.3.8 Interrupt Vectorization ......................................................................................... 289
11.3.9 Interrupt Status Clearing....................................................................................... 290
11.3.10 Interrupt Disabling............................................................................................. 290
11.4 AINTC Registers.......................................................................................................... 290
11.4.1 Revision Identification Register (REVID) .................................................................... 291
11.4.2 Control Register (CR) .......................................................................................... 292
11.4.3 Global Enable Register (GER)................................................................................ 293
11.4.4 Global Nesting Level Register (GNLR) ...................................................................... 293
11.4.5 System Interrupt Status Indexed Set Register (SISR)..................................................... 294
11.4.6 System Interrupt Status Indexed Clear Register (SICR) .................................................. 294
11.4.7 System Interrupt Enable Indexed Set Register (EISR) .................................................... 295
11.4.8 System Interrupt Enable Indexed Clear Register (EICR).................................................. 295
11.4.9 Host Interrupt Enable Indexed Set Register (HIEISR)..................................................... 296
11.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR)................................................. 296
11.4.11 Vector Base Register (VBR)................................................................................. 297
11.4.12 Vector Size Register (VSR).................................................................................. 297
11.4.13 Vector Null Register (VNR) .................................................................................. 298
11.4.14 Global Prioritized Index Register (GPIR)................................................................... 298
11.4.15 Global Prioritized Vector Register (GPVR) ................................................................ 299
11.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1)................................................... 299
11.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2)................................................... 300
11.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3)................................................... 300
11.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4)................................................... 301
11.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1)............................................ 301
11.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2)............................................ 302
11.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3)............................................ 302
11.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4)............................................ 303
11.4.24 System Interrupt Enable Set Register 1 (ESR1).......................................................... 303
11.4.25 System Interrupt Enable Set Register 2 (ESR2).......................................................... 304
11.4.26 System Interrupt Enable Set Register 3 (ESR3).......................................................... 304
11.4.27 System Interrupt Enable Set Register 4 (ESR4).......................................................... 305
11.4.28 System Interrupt Enable Clear Register 1 (ECR1) ....................................................... 305
11.4.29 System Interrupt Enable Clear Register 2 (ECR2) ....................................................... 306
11.4.30 System Interrupt Enable Clear Register 3 (ECR3) ....................................................... 306
11.4.31 System Interrupt Enable Clear Register 4 (ECR4) ....................................................... 307
11.4.32 Channel Map Registers (CMR0-CMR25) .................................................................. 307
11.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1)...................................................... 308
11.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2)...................................................... 308
11.4.35 Host Interrupt Nesting Level Register 1 (HINLR1)........................................................ 309
11.4.36 Host Interrupt Nesting Level Register 2 (HINLR2)........................................................ 309
11.4.37 Host Interrupt Enable Register (HIER) ..................................................................... 310

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11.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1) ................................................... 311
11.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2) ................................................... 311
12 Boot Considerations ......................................................................................................... 312
12.1 Introduction ................................................................................................................ 313
13 Programmable Real-Time Unit Subsystem (PRUSS).............................................................. 314
13.1 Overview................................................................................................................... 315
13.2 Description................................................................................................................. 317
13.3 Constants Table........................................................................................................... 318
13.4 PRU Module Interface.................................................................................................... 319
13.4.1 Event Out Mapping (R31): PRU System Events ........................................................... 319
13.4.2 Status Mapping (R31): Interrupt Events Input .............................................................. 319
13.4.3 General Purpose Inputs (R31)................................................................................ 319
13.4.4 General Purpose Outputs (R30).............................................................................. 319
13.5 Instruction Set............................................................................................................. 320
13.6 Instruction Formats ....................................................................................................... 323
13.7 PRU Interrupt Controller ................................................................................................. 341
13.7.1 Introduction...................................................................................................... 341
13.7.2 Interrupt Mapping............................................................................................... 341
13.7.3 PRUSS System Events........................................................................................ 342
13.7.4 ARM and DSP Interrupt Controller Mapping................................................................ 344
13.7.5 INTC Methodology.............................................................................................. 345
13.8 Registers................................................................................................................... 348
13.8.1 PRUSS Memory Map .......................................................................................... 349
13.8.2 INTC Registers.................................................................................................. 356
14 DDR2/mDDR Memory Controller......................................................................................... 367
14.1 Introduction ................................................................................................................ 368
14.1.1 Purpose of the Peripheral ..................................................................................... 368
14.1.2 Features.......................................................................................................... 368
14.1.3 Functional Block Diagram ..................................................................................... 369
14.1.4 Supported Use Case Statement.............................................................................. 369
14.1.5 Industry Standard(s) Compliance Statement................................................................ 369
14.2 Architecture................................................................................................................ 370
14.2.1 Clock Control.................................................................................................... 370
14.2.2 Signal Descriptions............................................................................................. 371
14.2.3 Protocol Description(s)......................................................................................... 372
14.2.4 Memory Width and Byte Alignment .......................................................................... 380
14.2.5 Address Mapping ............................................................................................... 381
14.2.6 DDR2/mDDR Memory Controller Interface.................................................................. 386
14.2.7 Refresh Scheduling............................................................................................. 389
14.2.8 Self-Refresh Mode.............................................................................................. 389
14.2.9 Partial Array Self Refresh for Mobile DDR .................................................................. 390
14.2.10 Power-Down Mode............................................................................................ 390
14.2.11 Reset Considerations......................................................................................... 391
14.2.12 VTP IO Buffer Calibration .................................................................................... 392
14.2.13 Auto-Initialization Sequence ................................................................................. 392
14.2.14 Interrupt Support .............................................................................................. 395
14.2.15 DMA Event Support........................................................................................... 395
14.2.16 Power Management .......................................................................................... 396
14.2.17 Emulation Considerations.................................................................................... 397
14.3 Supported Use Cases.................................................................................................... 398
14.4 Registers................................................................................................................... 403
14.4.1 SDRAM Status Register (SDRSTAT)........................................................................ 404
14.4.2 SDRAM Configuration Register (SDCR) .................................................................... 405

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14.4.3 SDRAM Refresh Control Register (SDRCR)................................................................ 408
14.4.4 SDRAM Timing Register 1 (SDTIMR1)...................................................................... 409
14.4.5 SDRAM Timing Register 2 (SDTIMR2)...................................................................... 410
14.4.6 SDRAM Configuration Register 2 (SDCR2)................................................................. 411
14.4.7 Peripheral Bus Burst Priority Register (PBBPR)............................................................ 412
14.4.8 Performance Counter 1 Register (PC1) ..................................................................... 413
14.4.9 Performance Counter 2 Register (PC2) ..................................................................... 413
14.4.10 Performance Counter Configuration Register (PCC)..................................................... 414
14.4.11 Performance Counter Master Region Select Register (PCMRS)....................................... 416
14.4.12 DDR PHY Reset Control Register (DRPYRCR) .......................................................... 417
14.4.13 Interrupt Raw Register (IRR) ................................................................................ 418
14.4.14 Interrupt Masked Register (IMR)............................................................................ 418
14.4.15 Interrupt Mask Set Register (IMSR) ........................................................................ 419
14.4.16 Interrupt Mask Clear Register (IMCR)...................................................................... 420
14.4.17 DDR PHY Control Register (DRPYC1R)................................................................... 421
15 Enhanced Capture (eCAP) Module...................................................................................... 422
15.1 Introduction ................................................................................................................ 423
15.1.1 Purpose of the Peripheral ..................................................................................... 423
15.1.2 Features.......................................................................................................... 423
15.2 Architecture................................................................................................................ 424
15.2.1 Capture and APWM Operating Mode........................................................................ 425
15.2.2 Capture Mode Description..................................................................................... 426
15.3 Applications ............................................................................................................... 433
15.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example ......................................... 434
15.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ........................... 436
15.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example ....................................... 438
15.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example ......................... 440
15.3.5 Application of the APWM Mode.............................................................................. 442
15.4 Registers................................................................................................................... 449
15.4.1 Time-Stamp Counter Register (TSCTR)..................................................................... 449
15.4.2 Counter Phase Control Register (CTRPHS)................................................................ 450
15.4.3 Capture 1 Register (CAP1).................................................................................... 450
15.4.4 Capture 2 Register (CAP2).................................................................................... 451
15.4.5 Capture 3 Register (CAP3).................................................................................... 451
15.4.6 Capture 4 Register (CAP4).................................................................................... 452
15.4.7 ECAP Control Register 1 (ECCTL1) ......................................................................... 452
15.4.8 ECAP Control Register 2 (ECCTL2) ......................................................................... 454
15.4.9 ECAP Interrupt Enable Register (ECEINT) ................................................................. 455
15.4.10 ECAP Interrupt Flag Register (ECFLG).................................................................... 457
15.4.11 ECAP Interrupt Clear Register (ECCLR)................................................................... 458
15.4.12 ECAP Interrupt Forcing Register (ECFRC)................................................................ 459
15.4.13 Revision ID Register (REVID) ............................................................................... 460
16 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 461
16.1 Introduction ................................................................................................................ 462
16.1.1 Introduction...................................................................................................... 462
16.1.2 Submodule Overview .......................................................................................... 462
16.1.3 Register Mapping............................................................................................... 466
16.2 Architecture................................................................................................................ 467
16.2.1 Overview......................................................................................................... 467
16.2.2 Proper Interrupt Initialization Procedure..................................................................... 470
16.2.3 Time-Base (TB) Submodule................................................................................... 471
16.2.4 Counter-Compare (CC) Submodule.......................................................................... 480
16.2.5 Action-Qualifier (AQ) Submodule............................................................................. 485

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16.2.6 Dead-Band Generator (DB) Submodule..................................................................... 503
16.2.7 PWM-Chopper (PC) Submodule.............................................................................. 507
16.2.8 Trip-Zone (TZ) Submodule .................................................................................... 511
16.2.9 Event-Trigger (ET) Submodule ............................................................................... 515
16.2.10 High-Resolution PWM (HRPWM) Submodule............................................................. 519
16.3 Applications to Power Topologies ...................................................................................... 526
16.3.1 Overview of Multiple Modules ................................................................................ 526
16.3.2 Key Configuration Capabilities................................................................................ 527
16.3.3 Controlling Multiple Buck Converters With Independent Frequencies................................... 528
16.3.4 Controlling Multiple Buck Converters With Same Frequencies........................................... 531
16.3.5 Controlling Multiple Half H-Bridge (HHB) Converters...................................................... 534
16.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................ 537
16.3.7 Practical Applications Using Phase Control Between PWM Modules ................................... 541
16.3.8 Controlling a 3-Phase Interleaved DC/DC Converter...................................................... 542
16.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter...................................... 547
16.4 Registers................................................................................................................... 550
16.4.1 Time-Base Submodule Registers ............................................................................ 550
16.4.2 Counter-Compare Submodule Registers.................................................................... 554
16.4.3 Action-Qualifier Submodule Registers....................................................................... 557
16.4.4 Dead-Band Generator Submodule Registers............................................................... 561
16.4.5 PWM-Chopper Submodule Register......................................................................... 564
16.4.6 Trip-Zone Submodule Registers.............................................................................. 565
16.4.7 Event-Trigger Submodule Registers ......................................................................... 569
16.4.8 High-Resolution PWM Submodule Registers............................................................... 572
17 Enhanced Direct Memory Access (EDMA3) Controller........................................................... 575
17.1 Introduction ................................................................................................................ 576
17.1.1 Overview......................................................................................................... 576
17.1.2 Features.......................................................................................................... 576
17.1.3 Functional Block Diagram ..................................................................................... 579
17.1.4 Terminology Used in This Document ........................................................................ 579
17.2 Architecture................................................................................................................ 581
17.2.1 Functional Overview............................................................................................ 581
17.2.2 Types of EDMA3 Transfers ................................................................................... 584
17.2.3 Parameter RAM (PaRAM)..................................................................................... 587
17.2.4 Initiating a DMA Transfer ...................................................................................... 597
17.2.5 Completion of a DMA Transfer................................................................................ 600
17.2.6 Event, Channel, and PaRAM Mapping ...................................................................... 601
17.2.7 EDMA3 Channel Controller Regions......................................................................... 604
17.2.8 Chaining EDMA3 Channels ................................................................................... 606
17.2.9 EDMA3 Interrupts............................................................................................... 606
17.2.10 Event Queue(s)................................................................................................ 613
17.2.11 EDMA3 Transfer Controller (EDMA3TC)................................................................... 615
17.2.12 Event Dataflow ................................................................................................ 618
17.2.13 EDMA3 Prioritization.......................................................................................... 619
17.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................ 621
17.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................ 622
17.2.16 Reset Considerations......................................................................................... 622
17.2.17 Power Management .......................................................................................... 622
17.2.18 Emulation Considerations.................................................................................... 623
17.3 Transfer Examples........................................................................................................ 623
17.3.1 Block Move Example........................................................................................... 623
17.3.2 Subframe Extraction Example ................................................................................ 625
17.3.3 Data Sorting Example.......................................................................................... 626

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17.3.4 Peripheral Servicing Example................................................................................. 628
17.4 Registers................................................................................................................... 640
17.4.1 Parameter RAM (PaRAM) Entries............................................................................ 640
17.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................ 647
17.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers........................................................ 686
17.5 Tips ......................................................................................................................... 707
17.5.1 Debug Checklist ................................................................................................ 707
17.5.2 Miscellaneous Programming/Debug Tips ................................................................... 708
17.6 Setting Up a Transfer .................................................................................................... 709
18 EMAC/MDIO Module.......................................................................................................... 710
18.1 Introduction ................................................................................................................ 711
18.1.1 Purpose of the Peripheral ..................................................................................... 711
18.1.2 Features.......................................................................................................... 711
18.1.3 Functional Block Diagram ..................................................................................... 712
18.1.4 Industry Standard(s) Compliance Statement................................................................ 713
18.1.5 Terminology ..................................................................................................... 713
18.2 Architecture................................................................................................................ 714
18.2.1 Clock Control.................................................................................................... 714
18.2.2 Memory Map .................................................................................................... 715
18.2.3 Signal Descriptions............................................................................................. 715
18.2.4 Ethernet Protocol Overview ................................................................................... 718
18.2.5 Programming Interface......................................................................................... 719
18.2.6 EMAC Control Module ......................................................................................... 730
18.2.7 MDIO Module ................................................................................................... 731
18.2.8 EMAC Module................................................................................................... 736
18.2.9 MAC Interface................................................................................................... 738
18.2.10 Packet Receive Operation ................................................................................... 742
18.2.11 Packet Transmit Operation .................................................................................. 747
18.2.12 Receive and Transmit Latency .............................................................................. 748
18.2.13 Transfer Node Priority ........................................................................................ 748
18.2.14 Reset Considerations......................................................................................... 749
18.2.15 Initialization..................................................................................................... 750
18.2.16 Interrupt Support .............................................................................................. 752
18.2.17 Power Management .......................................................................................... 756
18.2.18 Emulation Considerations.................................................................................... 756
18.3 Registers................................................................................................................... 757
18.3.1 EMAC Control Module Registers............................................................................. 757
18.3.2 MDIO Registers................................................................................................. 771
18.3.3 EMAC Module Registers....................................................................................... 784
19 External Memory Interface A (EMIFA).................................................................................. 834
19.1 Introduction ................................................................................................................ 835
19.1.1 Purpose of the Peripheral ..................................................................................... 835
19.1.2 Features.......................................................................................................... 835
19.1.3 Functional Block Diagram ..................................................................................... 835
19.2 Architecture................................................................................................................ 835
19.2.1 Clock Control.................................................................................................... 836
19.2.2 EMIFA Requests................................................................................................ 836
19.2.3 Pin Descriptions................................................................................................. 836
19.2.4 SDRAM Controller and Interface ............................................................................. 838
19.2.5 Asynchronous Controller and Interface...................................................................... 850
19.2.6 Data Bus Parking............................................................................................... 869
19.2.7 Reset and Initialization Considerations ...................................................................... 869
19.2.8 Interrupt Support................................................................................................ 870

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19.2.9 EDMA Event Support .......................................................................................... 871
19.2.10 Pin Multiplexing................................................................................................ 871
19.2.11 Memory Map................................................................................................... 871
19.2.12 Priority and Arbitration........................................................................................ 872
19.2.13 System Considerations....................................................................................... 873
19.2.14 Power Management .......................................................................................... 874
19.2.15 Emulation Considerations.................................................................................... 875
19.3 Example Configuration................................................................................................... 876
19.3.1 Hardware Interface ............................................................................................. 876
19.3.2 Software Configuration......................................................................................... 876
19.4 Registers................................................................................................................... 898
19.4.1 Module ID Register (MIDR) ................................................................................... 899
19.4.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 899
19.4.3 SDRAM Configuration Register (SDCR) .................................................................... 901
19.4.4 SDRAM Refresh Control Register (SDRCR)................................................................ 903
19.4.5 Asynchronous nConfiguration Registers (CE2CFG-CE5CFG) .......................................... 904
19.4.6 SDRAM Timing Register (SDTIMR).......................................................................... 906
19.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 907
19.4.8 EMIFA Interrupt Raw Register (INTRAW)................................................................... 908
19.4.9 EMIFA Interrupt Masked Register (INTMSK) ............................................................... 909
19.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET)....................................................... 910
19.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR).................................................... 911
19.4.12 NAND Flash Control Register (NANDFCR) ............................................................... 912
19.4.13 NAND Flash Status Register (NANDFSR)................................................................. 914
19.4.14 NAND Flash nECC Registers (NANDF1ECC-NANDF4ECC) .......................................... 915
19.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)....................................... 916
19.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) .................................................. 917
19.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) .................................................. 917
19.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) .................................................. 918
19.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) .................................................. 918
19.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1)................................. 919
19.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2)................................. 919
19.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)..................................... 920
19.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)..................................... 920
20 General-Purpose Input/Output (GPIO) ................................................................................. 921
20.1 Introduction ................................................................................................................ 922
20.1.1 Purpose of the Peripheral ..................................................................................... 922
20.1.2 Features.......................................................................................................... 922
20.1.3 Functional Block Diagram ..................................................................................... 922
20.1.4 Industry Standard(s) Compliance Statement................................................................ 922
20.2 Architecture................................................................................................................ 923
20.2.1 Clock Control.................................................................................................... 923
20.2.2 Signal Descriptions............................................................................................. 923
20.2.3 Pin Multiplexing ................................................................................................. 923
20.2.4 Endianness Considerations ................................................................................... 923
20.2.5 GPIO Register Structure....................................................................................... 924
20.2.6 Using a GPIO Signal as an Output........................................................................... 927
20.2.7 Using a GPIO Signal as an Input............................................................................. 928
20.2.8 Reset Considerations .......................................................................................... 928
20.2.9 Initialization ...................................................................................................... 929
20.2.10 Interrupt Support .............................................................................................. 929
20.2.11 EDMA Event Support......................................................................................... 930
20.2.12 Power Management .......................................................................................... 930

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20.2.13 Emulation Considerations.................................................................................... 930
20.3 Registers................................................................................................................... 931
20.3.1 Revision ID Register (REVID)................................................................................. 932
20.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN)...................................................... 933
20.3.3 GPIO Direction Registers (DIRn)............................................................................. 934
20.3.4 GPIO Output Data Registers (OUT_DATAn)............................................................... 936
20.3.5 GPIO Set Data Registers (SET_DATAn).................................................................... 938
20.3.6 GPIO Clear Data Registers (CLR_DATAn)................................................................. 940
20.3.7 GPIO Input Data Registers (IN_DATAn).................................................................... 942
20.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn)........................................... 944
20.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn)........................................ 946
20.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn)........................................ 948
20.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn)..................................... 950
20.3.12 GPIO Interrupt Status Registers (INTSTATn)............................................................. 952
21 Host Port Interface (HPI).................................................................................................... 954
21.1 Introduction ................................................................................................................ 955
21.1.1 Purpose of the Peripheral ..................................................................................... 955
21.1.2 Features.......................................................................................................... 955
21.1.3 Functional Block Diagram ..................................................................................... 956
21.1.4 Industry Standard(s) Compliance Statement................................................................ 957
21.1.5 Terminology Used in This Document ........................................................................ 957
21.2 Architecture................................................................................................................ 958
21.2.1 Clock Control.................................................................................................... 958
21.2.2 Memory Map .................................................................................................... 958
21.2.3 Signal Descriptions............................................................................................. 958
21.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks................................................ 959
21.2.5 Protocol Description............................................................................................ 960
21.2.6 Operation ........................................................................................................ 960
21.2.7 Reset Considerations .......................................................................................... 975
21.2.8 Initialization ...................................................................................................... 975
21.2.9 Interrupt Support................................................................................................ 976
21.2.10 EDMA Event Support......................................................................................... 977
21.2.11 Power Management .......................................................................................... 977
21.2.12 Emulation Considerations.................................................................................... 978
21.3 Registers................................................................................................................... 978
21.3.1 Revision Identification Register (REVID) .................................................................... 979
21.3.2 Power and Emulation Management Register (PWREMU_MGMT) ...................................... 979
21.3.3 GPIO Enable Register (GPIO_EN) .......................................................................... 980
21.3.4 GPIO Direction 1 Register (GPIO_DIR1).................................................................... 981
21.3.5 GPIO Data 1 Register (GPIO_DAT1)........................................................................ 981
21.3.6 GPIO Direction 2 Register (GPIO_DIR2).................................................................... 982
21.3.7 GPIO Data 2 Register (GPIO_DAT2)........................................................................ 983
21.3.8 Host Port Interface Control Register (HPIC) ................................................................ 984
21.3.9 Host Port Interface Write Address Register (HPIAW) ..................................................... 986
21.3.10 Host Port Interface Read Address Register (HPIAR) .................................................... 986
22 Inter-Integrated Circuit (I2C) Module ................................................................................... 987
22.1 Introduction ................................................................................................................ 988
22.1.1 Purpose of the Peripheral ..................................................................................... 988
22.1.2 Features.......................................................................................................... 988
22.1.3 Functional Block Diagram ..................................................................................... 989
22.1.4 Industry Standard(s) Compliance Statement................................................................ 989
22.2 Architecture................................................................................................................ 990
22.2.1 Bus Structure.................................................................................................... 990

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22.2.2 Clock Generation ............................................................................................... 991
22.2.3 Clock Synchronization ......................................................................................... 992
22.2.4 Signal Descriptions............................................................................................. 992
22.2.5 START and STOP Conditions ................................................................................ 993
22.2.6 Serial Data Formats............................................................................................ 994
22.2.7 Operating Modes ............................................................................................... 996
22.2.8 NACK Bit Generation........................................................................................... 997
22.2.9 Arbitration........................................................................................................ 998
22.2.10 Reset Considerations......................................................................................... 999
22.2.11 Initialization..................................................................................................... 999
22.2.12 Interrupt Support............................................................................................. 1000
22.2.13 DMA Events Generated by the I2C Peripheral .......................................................... 1001
22.2.14 Power Management......................................................................................... 1001
22.2.15 Emulation Considerations .................................................................................. 1001
22.3 Registers ................................................................................................................. 1002
22.3.1 I2C Own Address Register (ICOAR) ....................................................................... 1003
22.3.2 I2C Interrupt Mask Register (ICIMR) ....................................................................... 1004
22.3.3 I2C Interrupt Status Register (ICSTR)..................................................................... 1005
22.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) ..................................................... 1008
22.3.5 I2C Data Count Register (ICCNT) .......................................................................... 1009
22.3.6 I2C Data Receive Register (ICDRR) ....................................................................... 1010
22.3.7 I2C Slave Address Register (ICSAR)....................................................................... 1011
22.3.8 I2C Data Transmit Register (ICDXR)....................................................................... 1012
22.3.9 I2C Mode Register (ICMDR)................................................................................. 1013
22.3.10 I2C Interrupt Vector Register (ICIVR)..................................................................... 1017
22.3.11 I2C Extended Mode Register (ICEMDR) ................................................................. 1018
22.3.12 I2C Prescaler Register (ICPSC)........................................................................... 1019
22.3.13 I2C Revision Identification Register (REVID1)........................................................... 1020
22.3.14 I2C Revision Identification Register (REVID2) .......................................................... 1020
22.3.15 I2C DMA Control Register (ICDMAC)..................................................................... 1021
22.3.16 I2C Pin Function Register (ICPFUNC) ................................................................... 1022
22.3.17 I2C Pin Direction Register (ICPDIR) ..................................................................... 1023
22.3.18 I2C Pin Data In Register (ICPDIN) ....................................................................... 1024
22.3.19 I2C Pin Data Out Register (ICPDOUT) .................................................................. 1025
22.3.20 I2C Pin Data Set Register (ICPDSET) ................................................................... 1026
22.3.21 I2C Pin Data Clear Register (ICPDCLR) ................................................................ 1027
23 Liquid Crystal Display Controller (LCDC)........................................................................... 1028
23.1 Introduction............................................................................................................... 1029
23.1.1 Purpose of the Peripheral.................................................................................... 1029
23.1.2 Features........................................................................................................ 1030
23.1.3 Terminology.................................................................................................... 1030
23.2 Architecture .............................................................................................................. 1030
23.2.1 Clocking ........................................................................................................ 1030
23.2.2 LCD External I/O Signals..................................................................................... 1032
23.2.3 DMA Engine ................................................................................................... 1033
23.2.4 LIDD Controller................................................................................................ 1034
23.2.5 Raster Controller .............................................................................................. 1036
23.3 Registers ................................................................................................................. 1046
23.3.1 LCD Revision Identification Register (REVID) ............................................................ 1046
23.3.2 LCD Control Register (LCD_CTRL) ........................................................................ 1047
23.3.3 LCD Status Register (LCD_STAT).......................................................................... 1049
23.3.4 LCD LIDD Control Register (LIDD_CTRL)................................................................. 1052
23.3.5 LCD LIDD CSnConfiguration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF) .............. 1054

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23.3.6 LCD LIDD CSnAddress Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR) ...... 1055
23.3.7 LCD LIDD CSnData Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA) ........... 1056
23.3.8 LCD Raster Control Register (RASTER_CTRL).......................................................... 1057
23.3.9 LCD Raster Timing Register 0 (RASTER_TIMING_0)................................................... 1064
23.3.10 LCD Raster Timing Register 1 (RASTER_TIMING_1) ................................................. 1066
23.3.11 LCD Raster Timing Register 2 (RASTER_TIMING_2) ................................................. 1070
23.3.12 LCD Raster Subpanel Display Register (RASTER_SUBPANEL)..................................... 1074
23.3.13 LCD DMA Control Register (LCDDMA_CTRL).......................................................... 1076
23.3.14 LCD DMA Frame Buffer nBase Address Registers
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE)....................................................... 1077
23.3.15 LCD DMA Frame Buffer nCeiling Address Registers
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING)................................................ 1077
24 Multichannel Audio Serial Port (McASP) ............................................................................ 1078
24.0.16 Features ...................................................................................................... 1079
24.0.17 Protocols Supported ........................................................................................ 1080
24.0.18 Functional Block Diagram .................................................................................. 1081
24.0.19 Definition of Terms .......................................................................................... 1089
24.0.20 Overview ..................................................................................................... 1092
24.0.21 Clock and Frame Sync Generators ....................................................................... 1092
24.0.22 Reset Considerations ....................................................................................... 1133
24.0.23 EDMA Event Support ....................................................................................... 1133
24.0.24 Power Management......................................................................................... 1133
24.1 Registers ................................................................................................................. 1134
24.1.1 Register Bit Restrictions...................................................................................... 1137
24.1.2 Revision Identification Register (REV) ..................................................................... 1138
24.1.3 Pin Function Register (PFUNC)............................................................................. 1139
24.1.4 Pin Direction Register (PDIR) ............................................................................... 1141
24.1.5 Pin Data Output Register (PDOUT) ........................................................................ 1143
24.1.6 Pin Data Input Register (PDIN).............................................................................. 1145
24.1.7 Pin Data Set Register (PDSET)............................................................................. 1147
24.1.8 Pin Data Clear Register (PDCLR) .......................................................................... 1149
24.1.9 Global Control Register (GBLCTL) ......................................................................... 1151
24.1.10 Audio Mute Control Register (AMUTE)................................................................... 1153
24.1.11 Digital Loopback Control Register (DLBCTL)............................................................ 1155
24.1.12 Digital Mode Control Register (DITCTL).................................................................. 1156
24.1.13 Receiver Global Control Register (RGBLCTL)........................................................... 1157
24.1.14 Receive Format Unit Bit Mask Register (RMASK) ...................................................... 1158
24.1.15 Receive Bit Stream Format Register (RFMT)............................................................ 1159
24.1.16 Receive Frame Sync Control Register (AFSRCTL)..................................................... 1161
24.1.17 Receive Clock Control Register (ACLKRCTL)........................................................... 1162
24.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL)..................................... 1163
24.1.19 Receive TDM Time Slot Register (RTDM) ............................................................... 1164
24.1.20 Receiver Interrupt Control Register (RINTCTL) ......................................................... 1165
24.1.21 Receiver Status Register (RSTAT)........................................................................ 1166
24.1.22 Current Receive TDM Time Slot Registers (RSLOT)................................................... 1167
24.1.23 Receive Clock Check Control Register (RCLKCHK).................................................... 1168
24.1.24 Receiver DMA Event Control Register (REVTCTL)..................................................... 1169
24.1.25 Transmitter Global Control Register (XGBLCTL)........................................................ 1170
24.1.26 Transmit Format Unit Bit Mask Register (XMASK)...................................................... 1171
24.1.27 Transmit Bit Stream Format Register (XFMT) ........................................................... 1172
24.1.28 Transmit Frame Sync Control Register (AFSXCTL) .................................................... 1174
24.1.29 Transmit Clock Control Register (ACLKXCTL) .......................................................... 1175
24.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) .................................... 1176
24.1.31 Transmit TDM Time Slot Register (XTDM)............................................................... 1177

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24.1.32 Transmitter Interrupt Control Register (XINTCTL) ...................................................... 1178
24.1.33 Transmitter Status Register (XSTAT)..................................................................... 1179
24.1.34 Current Transmit TDM Time Slot Register (XSLOT).................................................... 1180
24.1.35 Transmit Clock Check Control Register (XCLKCHK)................................................... 1181
24.1.36 Transmitter DMA Event Control Register (XEVTCTL).................................................. 1182
24.1.37 Serializer Control Registers (SRCTLn)................................................................... 1183
24.1.38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5).......................................... 1184
24.1.39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)........................................ 1184
24.1.40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)..................................... 1185
24.1.41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ................................... 1185
24.1.42 Transmit Buffer Registers (XBUFn)....................................................................... 1186
24.1.43 Receive Buffer Registers (RBUFn)........................................................................ 1186
24.1.44 AFIFO Revision Identification Register (AFIFOREV) ................................................... 1187
24.1.45 Write FIFO Control Register (WFIFOCTL) ............................................................... 1188
24.1.46 Write FIFO Status Register (WFIFOSTS)................................................................ 1189
24.1.47 Read FIFO Control Register (RFIFOCTL)................................................................ 1190
24.1.48 Read FIFO Status Register (RFIFOSTS)................................................................. 1191
25 Multichannel Buffered Serial Port (McBSP) ........................................................................ 1192
25.1 Introduction............................................................................................................... 1193
25.1.1 Purpose of the Peripheral.................................................................................... 1193
25.1.2 Features........................................................................................................ 1193
25.1.3 Functional Block Diagram.................................................................................... 1194
25.1.4 Industry Standard Compliance Statement ................................................................. 1194
25.2 Architecture .............................................................................................................. 1195
25.2.1 Clock Control .................................................................................................. 1195
25.2.2 Signal Descriptions............................................................................................ 1195
25.2.3 Pin Multiplexing................................................................................................ 1195
25.2.4 Endianness Considerations.................................................................................. 1195
25.2.5 Clock, Frames, and Data..................................................................................... 1196
25.2.6 McBSP Buffer FIFO (BFIFO) ................................................................................ 1210
25.2.7 McBSP Standard Operation ................................................................................. 1210
25.2.8 μ-Law/A-Law Companding Hardware Operation.......................................................... 1224
25.2.9 Multichannel Selection Modes............................................................................... 1226
25.2.10 SPI Operation Using the Clock Stop Mode .............................................................. 1234
25.2.11 Resetting the Serial Port: RRST, XRST, GRST, and RESET ......................................... 1234
25.2.12 McBSP Initialization Procedure............................................................................ 1235
25.2.13 Interrupt Support............................................................................................. 1239
25.2.14 EDMA Event Support ....................................................................................... 1240
25.2.15 Power Management......................................................................................... 1241
25.2.16 Emulation Considerations .................................................................................. 1241
25.3 Registers ................................................................................................................. 1242
25.3.1 Data Receive Register (DRR) ............................................................................... 1243
25.3.2 Data Transmit Register (DXR)............................................................................... 1243
25.3.3 Serial Port Control Register (SPCR)........................................................................ 1244
25.3.4 Receive Control Register (RCR) ............................................................................ 1246
25.3.5 Transmit Control Register (XCR)............................................................................ 1248
25.3.6 Sample Rate Generator Register (SRGR)................................................................. 1250
25.3.7 Multichannel Control Register (MCR) ...................................................................... 1251
25.3.8 Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) .................................. 1255
25.3.9 Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3).................................. 1257
25.3.10 Pin Control Register (PCR)................................................................................. 1259
25.3.11 BFIFO Revision Identification Register (BFIFOREV) ................................................... 1261
25.3.12 Write FIFO Control Register (WFIFOCTL) ............................................................... 1262

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25.3.13 Write FIFO Status Register (WFIFOSTS)................................................................ 1263
25.3.14 Read FIFO Control Register (RFIFOCTL)................................................................ 1264
25.3.15 Read FIFO Status Register (RFIFOSTS)................................................................. 1265
26 Multimedia Card (MMC)/Secure Digital (SD) Card Controller................................................. 1266
26.1 Introduction............................................................................................................... 1267
26.1.1 Purpose of the Peripheral.................................................................................... 1267
26.1.2 Features........................................................................................................ 1267
26.1.3 Functional Block Diagram.................................................................................... 1267
26.1.4 Supported Use Case Statement ............................................................................ 1267
26.1.5 Industry Standard(s) Compliance Statement.............................................................. 1268
26.2 Architecture .............................................................................................................. 1268
26.2.1 Clock Control .................................................................................................. 1269
26.2.2 Signal Descriptions............................................................................................ 1270
26.2.3 Protocol Descriptions ......................................................................................... 1271
26.2.4 Data Flow in the Input/Output FIFO ........................................................................ 1272
26.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ........................................... 1274
26.2.6 FIFO Operation During Card Read Operation............................................................. 1275
26.2.7 FIFO Operation During Card Write Operation............................................................. 1277
26.2.8 Reset Considerations......................................................................................... 1277
26.2.9 Initialization..................................................................................................... 1279
26.2.10 Interrupt Support............................................................................................. 1282
26.2.11 DMA Event Support ......................................................................................... 1283
26.2.12 Power Management......................................................................................... 1283
26.2.13 Emulation Considerations .................................................................................. 1283
26.3 Procedures for Common Operations ................................................................................. 1284
26.3.1 Card Identification Operation ................................................................................ 1284
26.3.2 MMC/SD Mode Single-Block Write Operation Using CPU .............................................. 1287
26.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA........................................ 1289
26.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU.......................................... 1289
26.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ............................................ 1291
26.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU............................................. 1291
26.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA........................................... 1293
26.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................ 1293
26.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA .......................................... 1295
26.3.10 SDIO Card Function......................................................................................... 1295
26.4 Registers ................................................................................................................. 1296
26.4.1 MMC Control Register (MMCCTL).......................................................................... 1297
26.4.2 MMC Memory Clock Control Register (MMCCLK) ....................................................... 1298
26.4.3 MMC Status Register 0 (MMCST0)......................................................................... 1299
26.4.4 MMC Status Register 1 (MMCST1)......................................................................... 1301
26.4.5 MMC Interrupt Mask Register (MMCIM) ................................................................... 1302
26.4.6 MMC Response Time-Out Register (MMCTOR).......................................................... 1304
26.4.7 MMC Data Read Time-Out Register (MMCTOD)......................................................... 1305
26.4.8 MMC Block Length Register (MMCBLEN)................................................................. 1306
26.4.9 MMC Number of Blocks Register (MMCNBLK) ........................................................... 1307
26.4.10 MMC Number of Blocks Counter Register (MMCNBLC)............................................... 1307
26.4.11 MMC Data Receive Register (MMCDRR)................................................................ 1308
26.4.12 MMC Data Transmit Register (MMCDXR) ............................................................... 1308
26.4.13 MMC Command Register (MMCCMD) ................................................................... 1309
26.4.14 MMC Argument Register (MMCARGHL)................................................................. 1311
26.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ................................................... 1312
26.4.16 MMC Data Response Register (MMCDRSP)............................................................ 1314
26.4.17 MMC Command Index Register (MMCCIDX)............................................................ 1314

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26.4.18 SDIO Control Register (SDIOCTL)........................................................................ 1315
26.4.19 SDIO Status Register 0 (SDIOST0)....................................................................... 1316
26.4.20 SDIO Interrupt Enable Register (SDIOIEN).............................................................. 1317
26.4.21 SDIO Interrupt Status Register (SDIOIST)............................................................... 1317
26.4.22 MMC FIFO Control Register (MMCFIFOCTL) ........................................................... 1318
27 Real-Time Clock (RTC)..................................................................................................... 1319
27.1 Introduction............................................................................................................... 1320
27.1.1 Purpose of the Peripheral.................................................................................... 1320
27.1.2 Features........................................................................................................ 1320
27.1.3 Block Diagram................................................................................................. 1320
27.2 Architecture .............................................................................................................. 1321
27.2.1 Clock Source................................................................................................... 1321
27.2.2 Signal Descriptions............................................................................................ 1321
27.2.3 Isolated Power Supply........................................................................................ 1321
27.2.4 Operation....................................................................................................... 1322
27.2.5 Interrupt Requests ............................................................................................ 1324
27.2.6 Register Protection Against Spurious Writes.............................................................. 1325
27.2.7 General-Purpose Scratch Registers........................................................................ 1326
27.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) .............................. 1326
27.2.9 Emulation Modes of the Real-Time Clock ................................................................. 1326
27.2.10 Reset Considerations ....................................................................................... 1326
27.3 Registers ................................................................................................................. 1327
27.3.1 Second Register (SECOND)................................................................................. 1328
27.3.2 Minute Register (MINUTE)................................................................................... 1328
27.3.3 Hour Register (HOUR) ....................................................................................... 1329
27.3.4 Day of the Month Register (DAY)........................................................................... 1330
27.3.5 Month Register (MONTH).................................................................................... 1330
27.3.6 Year Register (YEAR) ........................................................................................ 1331
27.3.7 Day of the Week Register (DOTW)......................................................................... 1331
27.3.8 Alarm Second Register (ALARMSECOND) ............................................................... 1332
27.3.9 Alarm Minute Register (ALARMMINUTE).................................................................. 1332
27.3.10 Alarm Hour Register (ALARMHOUR)..................................................................... 1333
27.3.11 Alarm Day of the Month Register (ALARMDAY) ........................................................ 1334
27.3.12 Alarm Month Register (ALARMMONTH) ................................................................. 1335
27.3.13 Alarm Year Register (ALARMYEAR)...................................................................... 1335
27.3.14 Control Register (CTRL).................................................................................... 1336
27.3.15 Status Register (STATUS) ................................................................................. 1337
27.3.16 Interrupt Register (INTERRUPT) .......................................................................... 1338
27.3.17 Compensation (LSB) Register (COMPLSB) ............................................................. 1339
27.3.18 Compensation (MSB) Register (COMPMSB)............................................................ 1340
27.3.19 Oscillator Register (OSC)................................................................................... 1341
27.3.20 Scratch Registers (SCRATCH0-SCRATCH2) ........................................................... 1342
27.3.21 Kick Registers (KICK0R, KICK1R) ........................................................................ 1342
28 Serial ATA (SATA) Controller............................................................................................ 1343
28.1 Introduction............................................................................................................... 1344
28.1.1 Purpose of the Peripheral.................................................................................... 1344
28.1.2 Features Supported........................................................................................... 1344
28.1.3 Features Not Supported...................................................................................... 1345
28.1.4 Functional Block Diagram.................................................................................... 1345
28.1.5 Terminology Used in this Document........................................................................ 1346
28.1.6 Industry Standard(s) Compliance ........................................................................... 1347
28.2 Architecture .............................................................................................................. 1348
28.2.1 Clock Control .................................................................................................. 1348

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28.2.2 Signal Description............................................................................................. 1349
28.2.3 Pin Multiplexing................................................................................................ 1349
28.2.4 Interfacing to Single and Multiple Devices................................................................. 1349
28.2.5 DMA............................................................................................................. 1350
28.2.6 Transport Layer................................................................................................ 1350
28.2.7 Link Layer ...................................................................................................... 1350
28.2.8 Phy.............................................................................................................. 1351
28.2.9 Reset............................................................................................................ 1351
28.2.10 Initialization ................................................................................................... 1351
28.2.11 Interrupt Support............................................................................................. 1352
28.2.12 EDMA Event Support ....................................................................................... 1353
28.2.13 Power Management......................................................................................... 1353
28.3 Use Cases................................................................................................................ 1353
28.3.1 General Utilities: Structures and Subroutines Sample Program Uses ................................ 1354
28.3.2 Example on Initialization and Spinning Up Device........................................................ 1368
28.3.3 Example of DMA Write Transfer ............................................................................ 1370
28.3.4 Example of DMA Read Transfer ............................................................................ 1371
28.4 Registers ................................................................................................................. 1373
28.4.1 HBA Capabilities Register (CAP) ........................................................................... 1375
28.4.2 Global HBA Control Register (GHC)........................................................................ 1375
28.4.3 Interrupt Status Register (IS) ................................................................................ 1377
28.4.4 Ports Implemented Register (PI)............................................................................ 1378
28.4.5 AHCI Version Register (VS) ................................................................................. 1378
28.4.6 Command Completion Coalescing Control Register (CCC_CTL) ...................................... 1379
28.4.7 Command Completion Coalescing Ports Register (CCC_PORTS) .................................... 1380
28.4.8 BIST Active FIS Register (BISTAFR)....................................................................... 1381
28.4.9 BIST Control Register (BISTCR)............................................................................ 1381
28.4.10 BIST FIS Count Register (BISTFCTR).................................................................... 1384
28.4.11 BIST Status Register (BISTSR)............................................................................ 1384
28.4.12 BIST DWORD Error Count Register (BISTDECR)...................................................... 1385
28.4.13 BIST DWORD Error Count Register (TIMER1MS)...................................................... 1385
28.4.14 Global Parameter 1 Register (GPARAM1R) ............................................................. 1386
28.4.15 Global Parameter 2 Register (GPARAM2R) ............................................................. 1387
28.4.16 Port Parameter Register (PPARAMR).................................................................... 1388
28.4.17 Test Register (TESTR)...................................................................................... 1389
28.4.18 Version Register (VERSIONR) ............................................................................ 1390
28.4.19 ID Register (IDR) ............................................................................................ 1390
28.4.20 Port Command List Base Address Register (P0CLB) .................................................. 1391
28.4.21 Port FIS Base Address Register (P0FB) ................................................................. 1391
28.4.22 Port Interrupt Status Register (P0IS)...................................................................... 1392
28.4.23 Port Interrupt Enable Register (P0IE)..................................................................... 1394
28.4.24 Port Command Register (P0CMD)........................................................................ 1395
28.4.25 Port Task File Data Register (P0TFD).................................................................... 1398
28.4.26 Port Signature Register (P0SIG) .......................................................................... 1398
28.4.27 Port Serial ATA Status (SStatus) Register (P0SSTS) .................................................. 1399
28.4.28 Port Serial ATA Control (SControl) Register (P0SCTL) ................................................ 1400
28.4.29 Port Serial ATA Error (SError) Register (P0SERR)..................................................... 1401
28.4.30 Port Serial ATA Active (SActive) Register (P0SACT)................................................... 1403
28.4.31 Port Command Issue Register (P0CI) .................................................................... 1403
28.4.32 Port Serial ATA Notification Register (P0SNTF)......................................................... 1404
28.4.33 Port DMA Control Register (P0DMACR) ................................................................. 1405
28.4.34 Port PHY Control Register (P0PHYCR) .................................................................. 1407
28.4.35 Port PHY Status Register (P0PHYSR) ................................................................... 1411

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29 Serial Peripheral Interface (SPI) ........................................................................................ 1412
29.1 Introduction............................................................................................................... 1413
29.1.1 Purpose of the Peripheral.................................................................................... 1413
29.1.2 Features........................................................................................................ 1413
29.1.3 Functional Block Diagram.................................................................................... 1414
29.1.4 Industry Standard(s) Compliance Statement.............................................................. 1414
29.2 Architecture .............................................................................................................. 1415
29.2.1 Clock............................................................................................................ 1415
29.2.2 Signal Descriptions............................................................................................ 1415
29.2.3 Operation Modes.............................................................................................. 1415
29.2.4 Programmable Registers..................................................................................... 1416
29.2.5 Master Mode Settings ........................................................................................ 1417
29.2.6 Slave Mode Settings.......................................................................................... 1419
29.2.7 SPI Operation: 3-Pin Mode .................................................................................. 1420
29.2.8 SPI Operation: 4-Pin with Chip Select Mode ............................................................. 1421
29.2.9 SPI Operation: 4-Pin with Enable Mode ................................................................... 1423
29.2.10 SPI Operation: 5-Pin Mode................................................................................. 1425
29.2.11 Data Formats................................................................................................. 1427
29.2.12 Interrupt Support............................................................................................. 1430
29.2.13 DMA Events Support........................................................................................ 1431
29.2.14 Robustness Features ....................................................................................... 1431
29.2.15 Reset Considerations ....................................................................................... 1433
29.2.16 Power Management......................................................................................... 1433
29.2.17 General-Purpose I/O Pin.................................................................................... 1434
29.2.18 Emulation Considerations .................................................................................. 1434
29.2.19 Initialization ................................................................................................... 1434
29.2.20 Timing Diagrams............................................................................................. 1435
29.3 Registers ................................................................................................................. 1441
29.3.1 SPI Global Control Register 0 (SPIGCR0)................................................................. 1441
29.3.2 SPI Global Control Register 1 (SPIGCR1)................................................................. 1442
29.3.3 SPI Interrupt Register (SPIINT0)............................................................................ 1444
29.3.4 SPI Interrupt Level Register (SPILVL)...................................................................... 1446
29.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1447
29.3.6 SPI Pin Control Register 0 (SPIPC0) ...................................................................... 1449
29.3.7 SPI Pin Control Register 1 (SPIPC1)....................................................................... 1450
29.3.8 SPI Pin Control Register 2 (SPIPC2)....................................................................... 1451
29.3.9 SPI Pin Control Register 3 (SPIPC3)....................................................................... 1452
29.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1453
29.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1454
29.3.12 SPI Transmit Data Register 0 (SPIDAT0)................................................................ 1455
29.3.13 SPI Transmit Data Register 1 (SPIDAT1)................................................................ 1456
29.3.14 SPI Receive Buffer Register (SPIBUF)................................................................... 1457
29.3.15 SPI Emulation Register (SPIEMU) ........................................................................ 1459
29.3.16 SPI Delay Register (SPIDELAY) .......................................................................... 1460
29.3.17 SPI Default Chip Select Register (SPIDEF).............................................................. 1463
29.3.18 SPI Data Format Registers (SPIFMTn)................................................................... 1464
29.3.19 SPI Interrupt Vector Register 1 (INTVEC1) .............................................................. 1466
30 64-Bit Timer Plus ............................................................................................................ 1467
30.1 Introduction............................................................................................................... 1468
30.1.1 Purpose of the Peripheral.................................................................................... 1468
30.1.2 Features........................................................................................................ 1468
30.1.3 Block Diagram................................................................................................. 1469
30.1.4 Industry Standard Compatibility Statement................................................................ 1469

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30.1.5 Architecture – General-Purpose Timer Mode ............................................................. 1469
30.1.6 Architecture – Watchdog Timer Mode...................................................................... 1481
30.1.7 Reset Considerations......................................................................................... 1483
30.1.8 Interrupt Support .............................................................................................. 1483
30.1.9 DMA Event Support........................................................................................... 1483
30.1.10 TM64P_OUT Event Support ............................................................................... 1484
30.1.11 Interrupt/DMA Event Generation Control and Status ................................................... 1485
30.1.12 Power Management......................................................................................... 1485
30.1.13 Emulation Considerations .................................................................................. 1485
30.2 Registers ................................................................................................................. 1486
30.2.1 Revision ID Register (REVID) ............................................................................... 1488
30.2.2 Emulation Management Register (EMUMGT)............................................................. 1488
30.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN)............................................ 1489
30.2.4 GPIO Data and Direction Register (GPDATGPDIR) ..................................................... 1490
30.2.5 Timer Counter Registers (TIM12 and TIM34) ............................................................. 1491
30.2.6 Timer Period Registers (PRD12 and PRD34)............................................................. 1492
30.2.7 Timer Control Register (TCR) ............................................................................... 1493
30.2.8 Timer Global Control Register (TGCR)..................................................................... 1495
30.2.9 Watchdog Timer Control Register (WDTCR).............................................................. 1496
30.2.10 Timer Reload Register 12 (REL12) ....................................................................... 1497
30.2.11 Timer Reload Register 34 (REL34) ....................................................................... 1497
30.2.12 Timer Capture Register 12 (CAP12)...................................................................... 1498
30.2.13 Timer Capture Register 34 (CAP34)...................................................................... 1498
30.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) .......................................... 1499
31 Universal Asynchronous Receiver/Transmitter (UART) ....................................................... 1501
31.1 Introduction............................................................................................................... 1502
31.1.1 Purpose of the Peripheral.................................................................................... 1502
31.1.2 Features........................................................................................................ 1502
31.1.3 Functional Block Diagram.................................................................................... 1502
31.1.4 Industry Standard(s) Compliance Statement.............................................................. 1502
31.2 Peripheral Architecture ................................................................................................. 1504
31.2.1 Clock Generation and Control............................................................................... 1504
31.2.2 Signal Descriptions............................................................................................ 1506
31.2.3 Pin Multiplexing................................................................................................ 1506
31.2.4 Protocol Description .......................................................................................... 1506
31.2.5 Operation....................................................................................................... 1508
31.2.6 Reset Considerations......................................................................................... 1512
31.2.7 Initialization..................................................................................................... 1512
31.2.8 Interrupt Support .............................................................................................. 1512
31.2.9 DMA Event Support........................................................................................... 1514
31.2.10 Power Management......................................................................................... 1514
31.2.11 Emulation Considerations .................................................................................. 1514
31.2.12 Exception Processing ....................................................................................... 1514
31.3 Registers ................................................................................................................. 1515
31.3.1 Receiver Buffer Register (RBR)............................................................................. 1516
31.3.2 Transmitter Holding Register (THR)........................................................................ 1517
31.3.3 Interrupt Enable Register (IER) ............................................................................. 1518
31.3.4 Interrupt Identification Register (IIR)........................................................................ 1519
31.3.5 FIFO Control Register (FCR)................................................................................ 1520
31.3.6 Line Control Register (LCR) ................................................................................. 1522
31.3.7 Modem Control Register (MCR)............................................................................. 1524
31.3.8 Line Status Register (LSR) .................................................................................. 1525
31.3.9 Modem Status Register (MSR).............................................................................. 1528