Texas Instruments DRA821 User manual

User’s Guide
Powering DRA821 with TPS6594-Q1 and LP8764-Q1
ABSTRACT
This user’s guide can be used as a guide for integrating the TPS6594-Q1 and LP8764-Q1 power management
integrated circuits (PMICs) into a system powering the DRA821 processor.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Device Versions...................................................................................................................................................................... 2
3 Processor Connections..........................................................................................................................................................3
4 Supporting Functional Safety Systems................................................................................................................................9
4.1 Achieving ASIL-B System Requirements...........................................................................................................................9
4.2 Achieving up to ASIL-D System Requirements................................................................................................................10
5 Static NVM Settings..............................................................................................................................................................10
5.1 Application-Based Configuration Settings........................................................................................................................10
5.2 Device Identification Settings........................................................................................................................................... 11
5.3 BUCK Settings..................................................................................................................................................................11
5.4 LDO Settings....................................................................................................................................................................13
5.5 VCCA Settings................................................................................................................................................................. 14
5.6 GPIO Settings.................................................................................................................................................................. 15
5.7 Finite State Machine (FSM) Settings............................................................................................................................... 17
5.8 Interrupt Settings..............................................................................................................................................................18
5.9 POWERGOOD Settings...................................................................................................................................................21
5.10 Miscellaneous Settings.................................................................................................................................................. 22
5.11 Interface Settings............................................................................................................................................................23
5.12 Multi-Device Settings..................................................................................................................................................... 23
5.13 Watchdog Settings......................................................................................................................................................... 24
6 Pre-Configurable Finite State Machine (PFSM) Settings.................................................................................................. 24
6.1 Configured States............................................................................................................................................................ 24
6.2 PFSM Triggers................................................................................................................................................................. 27
6.3 Power Sequences............................................................................................................................................................ 29
7 Application Examples.......................................................................................................................................................... 47
7.1 Moving Between States: ACTIVE, MCU, and RETENTION............................................................................................ 47
7.2 Entering and Exiting Standby...........................................................................................................................................48
7.3 Entering and Existing LP_STANDBY............................................................................................................................... 48
7.4 GPIO8 and Watchdog...................................................................................................................................................... 49
8 Additional Resources...........................................................................................................................................................50
9 Revision History................................................................................................................................................................... 50
Trademarks
Jacinto™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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1 Introduction
This user’s guide defines the power distribution network (PDN) between the TPS6594-Q1 and LP8764-Q1
devices and the DRA821 processor. This document describes the platform power resource connections, digital
control connections, and PMIC sequencing settings to support the different processor state transitions. The
PMIC default non-volatile memory (NVM) settings, internal state transitions, and power sequences are also
defined in this document. This user's guide does not provide information about the electrical characteristics,
external components, package, or the functionality of the PMICs or processor. For such information and the full
register maps, refer to the data sheet for each device. In the event of any inconsistency between the official
specification and any user's guide, application report, or other referenced material, the data sheet specification is
the definitive source.
2 Device Versions
There are different versions of the TPS6594-Q1 and LP8764-Q1 devices available with unique NVM settings
to support different processor solutions. The unique NVM settings for each PMIC device are optimized per
PDN design to support different processors, processing loads, SDRAM types, system functional safety levels,
and end product features - such as low power modes, processor interface levels, SD Card, and so forth. The
NVM settings can be distinguished using the TI_NVM_ID register. In this user guide, each PMIC device is
distinguished by the TI orderable part number, TI_NVM_ID, and TI_NVM_REV values listed in Table 2-1.
Table 2-1. TPS6594-Q1 and LP8764-Q1 NVM Settings and Orderable Part Numbers
PDN USE CASE Orderable Part Number Device Mode TI_NVM_ID TI_NVM_REV
• Up to 4.25 A(1) on the CORE rail
• Up to 4.25 A(1) on the CPU rails
• Up to 3.4 A(1) on the SDRAM, with support for
LPDDR4
• Supports Functional Safety up to ASIL-D level
• Supports low power modes, including MCU-
only, GPIO Retention, and DDR Retention
states
• Supports I/O level of 3.3 V or 1.8 V
• Supports use of SD card
TPS6594141B Primary 0x1B 0x01
LP876441B1 Secondary 0xB1 0x01
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC
output rail.
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3 Processor Connections
This section details how the TPS6594-Q1 and LP8764-Q1 power resources and GPIO signals are connected to
the processor and other peripheral components to support the PDN use case.
Figure 3-1 shows the detailed power mapping between the processor and the TPS6594-Q1 and LP8764-Q1
PMICs. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there
is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage
monitoring of the input supply to the PMICs.
The VCCA voltage must be the first voltage applied to the PMIC devices. VIO_IN of the PMICs must be supplied
after VCCA. In this configuration, VIO_IN is supplied by the load switch that also supplies the VDDSHVx_MCU
voltage domain of the processor to allow the digital components of the PMIC devices (such as GPIOs) to remain
supplied in MCU-only mode. Additionally, by controlling VIO_IN of both PMICs through this load switch, the
system can also reduce power consumption in GPIO Retention or DDR Retention modes, since the load switch
is disabled.
This PDN supports the use of either a single dual load switch (TPS22966-Q1) with an AEC-100 Grade 2 (-40
to +105°C) temperature rating or two single load switches (TPS22965-Q1) with an AEC-100 Grade 1 (-40 to
+125°C) rating if a higher ambient temperature range is desired. The PDN diagrams of this section also include
a few optional discrete power components to support additional system functions that may be needed. The
TLV70033-Q1 LDO is used to support compliant USB data eye performance by supplying a low noise 3.3 V
for USB 2.0 interface integration. The TLV70018-Q1 LDO is available to support on-board EFUSE programming
on high security SoC PNs. Alternative LDOs can be chosen for SD card dual-voltage I/O support (3.3 V and
1.8 V), TLV7103318-Q1 dual-voltage LDO can be used to enable compliant, dual voltage, high-speed SD card
operations.
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TPS6594-Q1
BUCK2
(3.5A max)
BUCK3
(3.5A max)
BUCK4
(4A max)
BUCK5
(2A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
LP8764-Q1
BUCK1
(5A max)
Primary PMICSecondary PMIC
Processor Supplies
MAIN PROCESSOR
VDD_CORE
VDDAR_CPU/CORE
VDD_WAKE0
VDDS_DDR_BIAS
1.1V
0.8V
0.85V
MAIN ANALOG
VDDA_1P8_PHYs
VDDA_0P8_PHYs
VDDA_0P8_PLLs/DLLs
VDDA_1P8_PLLs
0.8V
VDDA_3P3_USB
MAIN DIGITAL
VDDSHV0
VDDSHV2
VDDS_MMC0
1.8V
1.8V
MCU SAFETY ISLAND
VDD_MCU
VDDAR_MCU
VDDSHVx_MCU (1.8V)
System
1.8V
3.3V
VPP_x (EFUSE)
0.85V
1.8V
VDDSHVx_MCU (3.3V)
0.8V
TPS22965-Q1
(load switch, 4A max)
3.3V
1.8V
1.8V
LPDDR4
VDD1
VDD2
3.3V
VDD_CPU (AVS)
VCCA
OVPGDRV
VCCA
VIO_IN
VIO_IN
BUCK1
(3.5A max)
1.8V
BUCK2
(5A max)
BUCK3
(5A max)
BUCK4
(5A max)
0.8V
VDDSHV5
TLV70033-Q1
(LDO, 200mA max)
TLV70018-Q1
(LDO, 300mA max)
TLV7103318-Q1
(dual-LDO, 200mA max)
3.3V
3.3V
3.3V
1.8V
1.8V/3.3V
5V
VDDA_x
VDDS_DDR_IO
VDDQ
Octal SPI FLASH
Hyper FLASH
EMMC
VCCQ
VCC
PDN OPTIONS
MCU-only
DDR Retention
GPIO Retention
TPS22965-Q1
(load switch, 4A max)
TPS22965-Q1
(load switch, 4A max)
Figure 3-1. TPS6594-Q1 and LP8764-Q1 Power Connections
The power resource assignments shown in Figure 3-1 enable the support for different processor low-power
modes, including MCU-only mode, GPIO Retention, and DDR Retention. Please use Table 3-1 as a guide to
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understand which power resources are required to support different system features. If the system feature listed
is not required, the power resource connection can be removed.
Table 3-1. Power Resources by System Power States
Device PMIC
Resource Processor Domains Power States
Active SoC MCU - only GPIO Retention DDR Retention
TPS6594-Q1
BUCK1 VDDA_x Required Required
BUCK2 VDDSHVx_MCU (1.8V) Required Required
BUCK3 VDD_MCU, VDDAR_MCU Required Required
BUCK4 VDDS_DDR_BIAS,
VDDS_DDR_IO Required Required
BUCK5 VDDA_1P8_PHYs Required
LDO1 N/A Required Required
LDO2 VDDA_0P8_PLLs/DLLs Required
LDO3 VDD_WAKE0 Required Required
LDO4 VDDA_1P8_PLLs Required
LP8764-Q1
BUCK1 VDD_CPU Required
BUCK2 VDDAR_CPU/CORE Required
BUCK3 VDD_CORE,
VDDA_0P8_PHYs Required
BUCK4 VDDS_MMC0 Required
TPS22965-Q1 Load Switch VDDSHVx_MCU (3.3 V) Required Required
TPS22966-Q1 Load Switch 1 VDDSHV0(1) Required
Load Switch 2 VDDSHV2 Required
(1) VDDSHV5 can also be powered by this rail if an SD card is not required in the system.
Figure 3-2 shows the digital control signal mapping between the processor and the PMIC devices. For the two
PMIC devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication
channel. The SPMI bus allows the TPS6594-Q1 and LP8764-Q1 to synchronize their internal Pre-Configurable
State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. The GPIO_5
and GPIO_6 pins on the TPS6594-Q1 and GPIO_8 and GPIO_9 pins on LP8764-Q1 are assigned for this
functionality. In addition, the LDOVINT pin of the primary PMIC must be connected to the ENABLE input
(GPIO_4 of LP8764-Q1) of the secondary PMIC to correctly initiate the PFSM.
Other digital connections from the TPS6594-Q1 devices to the processor allow support for error monitoring,
processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to
key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain
operational.
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To support DDR retention low power mode, the following PMIC GPIO functions are required:
1. GPIO_2 and GPIO_3 of LP8764-Q1 connected to an external, low voltage latch to create a sustained control
signal to DDR_RET of the processor. The latch is needed since the PMIC VIO_IN power rail supplying
GPIO_2 and 3 is disabled during DDR Retention state.
2. Sustained GPIO_9 of TPS6594-Q1 connected to the enable input of a 3.3V in-line load switch to the MCU.
3. Sustained GPIO_4 of TPS6594-Q1 with NVM default function set as LP_WKUP1 and mask bit set high to
avoid false triggering until CAN wakeup signal is armed. SW must properly arm CAN PHY so that wakeup
signal is set high and unmask GPIO_4 before entering GPIO Retention state.
GPIO_4 of TPS6594-Q1 is powered by the VRTC internal voltage domain of the PMIC. The LDOVRTC regulator
supplies always-on functions, such as the wake-up function of GPIO_4. This enables GPIO_4 to be used as a
wake-up source in LP_STANDBY when LDO_VINT is turned off.
To support GPIO retention low power mode, the following PMIC GPIO functions are required:
1. Sustained GPIO_7 of LP8764-Q1 connected to the enable input of an in-line load switch to control the 3.3 V
GPIO retention domain.
Additional digital options also include GPIO_10 of TPS6594-Q1, which can be configured by software as a 32
kHz clock output for the processor oscillator input (LFOSC ). There is also the option to disable the watchdog
timer using hardware, by pulling GPIO_8 of TPS6594-Q1 high. Lastly, GPIO_1 of LP8764-Q1 is included in the
power up sequence to enable external regulators, for options such as DDR I/O.
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TPS6594-Q1
ENABLE
INTn
nRSTOUT
GPIO_1 (SCL_I2C2)
LP8764-Q1
Primary PMIC
Processor
SoC MAIN CONTROLS
PMIC_WAKE0
MMC1 IO
DDR_RET
SAFETY MCU CONTROLS
Safety MCU GPIO
WKUP_I2C0_SCL/SDA
MCU_PORz
Board
SOC_SAFETY_ERRORn
TPS22965-Q1
Warm Reset
ON REQUEST
SCL_I2C1
SDA_I2C1
GPIO_2 (SDA_I2C2)
GPIO_3 (nERR_SOC)
GPIO_4 (LP_WKUP1)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_7 (nERR_MCU)
GPIO_8 (DISABLE_WDOG)
GPIO_9 (GPO)
GPIO_10 (CLK32OUT)
GPIO_11 (nRSTOUT_SoC)
INTn
GPIO_1 (GPO)
Secondary PMIC
SCL_I2C1
SDA_I2C1
GPIO_2 (GPO)
GPIO_3 (GPO)
GPIO_4 (ENABLE)
GPIO_5 (GPO)
GPIO_6 (GPI)
GPIO_7 (GPO)
GPIO_8 (SCLK_SPMI)
GPIO_9 (SDATA_SPMI)
GPIO_10 (GPO)
LDOVINT VOUT_LDO
MCU_I2C0_SCL/SDA
ENABLE MCU I/O
MCU_SAFETY_ERRORn
PORz
PMIC VOLTAGE DOMAINS
VRTC – 1.8V
VINT – 1.8V
VIO – 1.8V or 3.3V
RESETSTATz
Disable Watchdog
CAN Wakeup
PDN OPTIONS
MCU-only
DDR Retention
GPIO Retention
TLV70033-Q1
TLV70018-Q1
TLV7103318-Q1
EN1
EN2
Q
Q
SET
CLR
D
TPS6594-Q1, BUCK4
Enable DDR I/O (Optional)
ENABLE MAIN I/O
EN_GPIO_RET
ENABLE USB
ENABLE
EFUSE
ENABLE
3.3V SD
ENABLE 1.8V SD
GPIO_DDR_RET_VAL
GPIO_DDR_RET_CLK
TPS22965-Q1
TPS22965-Q1
Figure 3-2. TPS6594-Q1 and LP8764-Q1 Digital Connections
The digital connections shown in Figure 3-2 allow system features including MCU-only mode, GPIO retention
mode, DDR retention mode, and functional safety systems capable of supporting up to ASIL-D. Please use Table
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3-2 as a guide to understand GPIO assignments required for these features. If the feature listed is not required,
the digital connection can be removed. For details on how functional safety related connections help achieve
functional safety system-level goals, see Section 4.
Table 3-2. Digital Connections by System Feature
Device PMIC Digital
Signal System Digital Signal
System Features
Active SoC Functional
Safety MCU - only GPIO Retention
DDR
Retention
TPS6594-Q1
nPWRON/
ENABLE System ON Request Required
INT(1) Safety MCU GPIO Required
nRSTOUT(1) MCU_PORz Required Required
SCL_I2C1 WKUP_I2C0_SCL Required
SDA_I2C1 WKUP_I2C0_SDA Required
GPIO_1 MCU_I2C0_SCL Required
GPIO_2 MCU_I2C0_SCL Required
GPIO_3 SOC_SAFETY_ERRORn Optional
GPIO_4(2) CAN Wakeup Required Required
GPIO_5 PMIC SPMI CLK Required
GPIO_6 PMIC SPMI DATA Required
GPIO_7 MCU_SAFETY_ERRORn Optional
GPIO_8 (5) Disable Watchdog (3) (3)
GPIO_9 ENABLE MCU I/O Required
GPIO_10(4) WKUP_LFOSC0 Required
GPIO_11(1) SOC_PORz Required Required
LP8764-Q1
INT(1) Safety MCU GPIO Required
SCL_I2C1 WKUP_I2C0_SCL Required
SDA_I2C1 WKUP_I2C0_SDA Required
GPIO_1 Enable DDR I/O (Optional)
GPIO_2(5) External Latch Data Input Required
GPIO_3(5) External Latch Clock Input Required
GPIO_4 TPS6594-Q1 LDOVINT Required
GPIO_5(5) Enable EFUSE
GPIO_6 (5) N/A
GPIO_7 EN_GPIO_RET Required Required
GPIO_8 PMIC SPMI CLK Required
GPIO_9 PMIC SPMI DATA Required
GPIO_10 Enable Main I/O Required Required Required
(1) This pin is open-drain to enable voltage translation to correct voltage level for processor interface.
(2) Software must unmask GPIO_4 before the system expects to trigger a wakeup on this pin.
(3) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high.
After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(4) GPIO_10 is set as a general purpose input (GPI) by default to allow processor to boot up before sourcing the 32 kHz to the processor,
since both bootmode and low frequency clock inputs to the processor utilize the same pin.
(5) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if
desired.
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4 Supporting Functional Safety Systems
By using the TPS6594-Q1 and LP8764-Q1 solution to power the DRA821 processor, the system can leverage
the following PMIC functional safety features:
• Independent Power Control of MCU and Main Rails
• Independent Monitoring and Reset for MCU and Main Rails
• Input Supply Monitoring
• Output Voltage and Current Monitoring
• Question & Answer Watchdog
• Fault Reporting Interrupts
• Enable Drive Pin that provides an independent path to disable system actuators
• Error Pin Monitoring
• Internal Diagnostics including voltage monitoring, temperature monitoring, and Built-In Self-Test
Refer to the Safety Manuals of the TPS6594-Q1 and LP8764-Q1 devices for full descriptions and analysis of
the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-D rating
for a system. Additionally, these features help in achieving the functional safety assumptions utilized by the
processor to achieve up to ASIL-D rating. See the DRA821 Safety Manual for Jacinto™ 7 Processors for a
complete list of functional safety system assumptions.
4.1 Achieving ASIL-B System Requirements
To achieve a system functional safety level of ASIL-B, the following PDN features are available:
• PMIC over voltage and under voltage monitoring on the power resource voltage outputs
• PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
• Watchdog monitoring of safety processor
• MCU error monitoring
• MCU reset
• I2C communication
• Error indicator, EN_DRV, for driving external circuitry (optional)
• Read-back of EN_DRV pin
The PDN has an in-line, external power FET between the input supply and PMICs. This FET can quickly isolate
the PMICs when an over-voltage event greater than 6 V is detected on the input supply to protect the system
from being damaged, as shown in Figure 3-1. Note that any power rail connected after the FET can be protected
from an over voltage event. Any power connected upstream from the FET is not protected from over voltage
events. In Figure 3-1 the load switches that supply power to the MCU and Main I/O domains and the discrete
buck supplying the DDR are all connected after the FET to extend the over voltage protection to these processor
domains and discrete power resources.
The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels
can be enabled through I2C after startup. To monitor the load switch voltage that supplies the MCU I/O of the
processor, it is recommended to use the processor POK monitor built into the VDDSHV0_MCU voltage domain.
The PMIC Internal Q&A Watchdog is enabled by default on the TPS6594-Q1 device. Once the device is in
ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C in the device.
The steps for configuring the watchdog settings can be found in the TPS6594-Q1 data sheet. Setting the
DISABLE_WDOG signal high on TPS6594-Q1 GPIO_8 disables the watchdog timer if this feature needs to be
suspended or is not required in the system.
GPIO_7 of the TPS6594-Q1 PMIC is configured as the MCU error signal monitoring, and must be enabled
though the ESM_MCU_EN register bit. MCU reset is supported through the connection between the primary
PMIC nRSTOUT pin and the MCU_PORz of the processor. Lastly, there are 2 I2C ports between the TPS6594-
Q1 and the processor. The first is used for all non-watchdog communication, such as voltage level control, and
the second allows the watchdog monitoring to be on an independent communication channel.
There is an option to use the EN_DRV of theTPS6594-Q1 PMIC to indicate an error has been detected and the
system is entering SAFE state. This signal can be utilized if the system has some additional external circuitry
that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed.
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4.2 Achieving up to ASIL-D System Requirements
For ASIL-C or ASIL-D systems, there are additional features to the ones described in Section 4.1 that can be
utilized. These features include:
• PMIC current monitoring on all output power rails
• Isolation of the MCU and Main power domains of the processor
• SoC reset
The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594-Q1 and LP8764-Q1
devices. Additionally, Figure 3-1 shows that the MCU domain of the processor is powered by different power
resources of the PMICs than the main power domain of the processor. SoC reset functionality is supported
through the connection of GPIO_11 on TPS6594-Q1, configured as nRSTOUT_SoC, to the PORz pin of the
processor.
Note
Residual voltage checking is available on the PMICs to prevent startup when output rails are not
discharged below 100 mV as may happen under a fault condition. However, this feature is not
enabled in the NVM settings of this PDN to support repetitive power cycling during system software
development.
5 Static NVM Settings
The TPS6594-Q1 and LP8764-Q1 devices consist of fixed registers and configurable registers that are loaded
from the NVM. For all NVM registers, the initial NVM settings that load into the registers are provided in this
section. Note that these initial NVM settings can be changed during state transitions, such as moving from
STANDBY to ACTIVE mode. The full register map, including default values of fixed registers, is located in the
corresponding PMIC data sheet. Empty values indicate that the device does not have the register included. For
example, LP8764-Q1 does not have BUCK5 registers at all and therefore the values for it are empty.
5.1 Application-Based Configuration Settings
In the LP876441B1-Q1 and TPS6594141B-Q1 data sheet, there are multiple application-based configurations
for each BUCK to operate within. Table 5-1 includes the different configurations available:
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Table 5-1. LP876441B1-Q1 and TPS6594141B-Q1 Use Cases
TPS6594141B-Q1 LP876441B1-Q1
2.2 MHz Single Phase for DDR Termination 2.2MHz Single-Phase for DDR Termination
4.4 MHz VOUT Less than 1.9 V, Multiphase 4.4MHz Single-Phase and Multi-Phase
4.4 MHz VOUT Less than 1.9 V, Single Phase 4.4MHz Single-Phase, Low Output Voltage
4.4 MHz VOUT Greater than 1.7 V, Single Phase 4.4MHz Single-Phase, High Output Voltage
2.2 MHz VOUT Less than 1.9 V, Multiphase or Single Phase 2.2MHz Single-Phase Configuration with 5.0V VIN
2.2 MHz Full VOUT Range with 5.0 V VIN, Single Phase 2.2MHz Single-Phase and Multi-Phase Configuration
2.2 MHz Full VOUT and Full VIN Range, Single Phase 2.2MHz Single-Phase Generic Configuration
The seven configurations also have optimal output inductance values that optimize the performance of each
buck under these various conditions. Table 5-2 shows the default configurations for the BUCKs. These settings
cannot be changed after device startup.
Table 5-2. Application Use Case Settings
Device BUCK Rail Default Application Use Case Recommended Inductor Value
TPS6594141B-Q1
BUCK1 4.4 MHz VOUT Less than 1.9 V, Single Phase 220 nH
BUCK2 4.4 MHz VOUT Less than 1.9 V, Single Phase 220 nH
BUCK3 4.4 MHz VOUT Less than 1.9 V, Single Phase 220 nH
BUCK4 4.4 MHz VOUT Less than 1.9 V, Single Phase 220 nH
BUCK5 4.4 MHz VOUT Less than 1.9 V, Single Phase 220 nH
LP876441B1-Q1
BUCK1 4.4MHz Single-Phase, Low Output Voltage 220 nH
BUCK2 4.4MHz Single-Phase, Low Output Voltage 220 nH
BUCK3 4.4MHz Single-Phase, Low Output Voltage 220 nH
BUCK4 4.4MHz Single-Phase, Low Output Voltage 220 nH
5.2 Device Identification Settings
These settings are used to distinguish which device is detected in a system. These settings cannot be changed
after device startup.
Table 5-3. Device Identification NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
DEV_REV DEVICE_ID 0x82 0x82 0x86 0x86
NVM_CODE_1 TI_NVM_ID 0x1B 0x1B 0xb1 0xb1
NVM_CODE_2 TI_NVM_REV 0x1 0x1 0x1 0x1
PHASE_CONFIG MP_CONFIG 0x1 1+1+1+1+1 0x1 1+1+1+1
5.3 BUCK Settings
These settings detail the default voltages, configurations, and monitoring of the BUCK rails. All these settings
can be changed though I2C after startup.
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Table 5-4. BUCK NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
BUCK1_CTRL BUCK1_EN(1) 0x0 Disabled; BUCK1 regulator 0x0 Disabled; BUCK1 regulator
BUCK1_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK1_FPWM_MP 0x0 Automatic phase adding
and shedding.
0x0 Automatic phase adding
and shedding.
BUCK1_VMON_EN(1) 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK1_VSEL 0x0 BUCK1_VOUT_1 0x0 BUCK1_VOUT_1
BUCK1_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK1_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK1_ILIM 0x5 5.5 A 0x7 7.5 A
BUCK2_CTRL BUCK2_EN(1) 0x0 Disabled; BUCK2 regulator 0x0 Disabled; BUCK2 regulator
BUCK2_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK2_VMON_EN(1) 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK2_VSEL 0x0 BUCK2_VOUT_1 0x0 BUCK2_VOUT_1
BUCK2_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK2_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK2_ILIM 0x5 5.5 A 0x7 7.5 A
BUCK3_CTRL BUCK3_EN(1) 0x0 Disabled; BUCK3 regulator 0x0 Disabled; BUCK3 regulator
BUCK3_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK3_FPWM_MP 0x0 Automatic phase adding
and shedding.
0x0 Automatic phase adding
and shedding.
BUCK3_VMON_EN(1) 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK3_VSEL 0x0 BUCK3_VOUT_1 0x0 BUCK3_VOUT_1
BUCK3_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK3_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK3_CONF BUCK3_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK3_ILIM 0x5 5.5 A 0x7 7.5 A
BUCK4_CTRL BUCK4_EN(1) 0x0 Disabled; BUCK4 regulator 0x0 Disabled; BUCK4 regulator
BUCK4_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK4_VMON_EN(1) 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK4_VSEL 0x0 BUCK4_VOUT_1 0x0 BUCK4_VOUT_1
BUCK4_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK4_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK4_ILIM 0x5 5.5 A 0x7 7.5 A
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Table 5-4. BUCK NVM Settings (continued)
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
BUCK5_CTRL BUCK5_EN(1) 0x0 Disabled; BUCK5 regulator
BUCK5_FPWM 0x0 PFM and PWM operation
(AUTO mode).
BUCK5_VMON_EN(1) 0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK5_VSEL 0x0 BUCK5_VOUT_1
BUCK5_PLDN 0x1 Enable Pull-down resistor
BUCK5_RV_SEL 0x1 Enabled
BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs
BUCK5_ILIM 0x3 3.5 A
BUCK1_VOUT_1 BUCK1_VSET1 0xb2 1.80 V 0x37 0.800 V
BUCK1_VOUT_2 BUCK1_VSET2 0x0 0.3 V 0x0 0.3 V
BUCK2_VOUT_1 BUCK2_VSET1 0xb2 1.80 V 0x41 0.850 V
BUCK2_VOUT_2 BUCK2_VSET2 0x0 0.3 V 0x0 0.3 V
BUCK3_VOUT_1 BUCK3_VSET1 0x41 0.850 V 0x37 0.800 V
BUCK3_VOUT_2 BUCK3_VSET2 0x0 0.3 V 0x0 0.3 V
BUCK4_VOUT_1 BUCK4_VSET1 0x73 1.10 V 0xb2 1.80 V
BUCK4_VOUT_2 BUCK4_VSET2 0x0 0.3 V 0x0 0.3 V
BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V
BUCK5_VOUT_2 BUCK5_VSET2 0x0 0.3 V
BUCK1_PG_WINDOW BUCK1_OV_THR 0x2 +4% / +40 mV 0x2 +4% / +40 mV
BUCK1_UV_THR 0x2 -4% / -40 mV 0x2 -4% / -40 mV
BUCK2_PG_WINDOW BUCK2_OV_THR 0x2 +4% / +40 mV 0x2 +4% / +40 mV
BUCK2_UV_THR 0x2 -4% / -40 mV 0x2 -4% / -40 mV
BUCK3_PG_WINDOW BUCK3_OV_THR 0x2 +4% / +40 mV 0x2 +4% / +40 mV
BUCK3_UV_THR 0x2 -4% / -40 mV 0x2 -4% / -40 mV
BUCK4_PG_WINDOW BUCK4_OV_THR 0x2 +4% / +40 mV 0x2 +4% / +40 mV
BUCK4_UV_THR 0x2 -4% / -40 mV 0x2 -4% / -40 mV
BUCK5_PG_WINDOW BUCK5_OV_THR 0x2 +4% / +40 mV
BUCK5_UV_THR 0x2 -4% / -40 mV
VMON1_PG_WINDOW VMON1_RANGE 0x0 0.3 - 3.34 V
VMON1_UV_THR 0x0 -3% / -30 mV / (-150 mV)
VMON1_OV_THR 0x0 +3% / +30 mV / (+150 mV)
VMON1_PG_LEVEL VMON1_PG_SET 0x0 0x0
VMON2_PG_WINDOW VMON2_RANGE 0x0 0.3 - 3.34 V
VMON2_UV_THR 0x0 -3% / -30 mV / (-150 mV)
VMON2_OV_THR 0x0 +3% / +30mV / (+150 mV)
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.
5.4 LDO Settings
These settings detail the default voltages, configurations, and monitoring of the LDO rails. All these settings can
be changed though I2C after startup. Note that only TPS6594141B-Q1 device contains LDO outputs.
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Table 5-5. LDO NVM Settings
Register Name Field Name TPS6594141B-Q1
Value Description
LDO1_CTRL LDO1_EN(1) 0x0 Disabled; LDO1 regulator.
LDO1_PLDN 0x2 250 Ohm
LDO1_VMON_EN(1) 0x0 Disable OV and UV comparators.
LDO1_RV_SEL 0x1 Enabled
LDO2_CTRL LDO2_EN(1) 0x0 Disabled; LDO2 regulator.
LDO2_PLDN 0x1 125 Ohm
LDO2_VMON_EN(1) 0x0 Disabled; OV and UV comparators.
LDO2_RV_SEL 0x1 Enabled
LDO3_CTRL LDO3_EN(1) 0x0 Disabled; LDO3 regulator.
LDO3_PLDN 0x1 125 Ohm
LDO3_VMON_EN(1) 0x0 Disabled; OV and UV comparators.
LDO3_RV_SEL 0x1 Enabled
LDO4_CTRL LDO4_EN(1) 0x0 Disabled; LDO4 regulator.
LDO4_PLDN 0x1 125 Ohm
LDO4_VMON_EN(1) 0x0 Disabled; OV and UV comparators.
LDO4_RV_SEL 0x1 Enabled
LDO1_VOUT LDO1_VSET 0x1c 1.80 V
LDO1_BYPASS 0x0 Linear regulator mode.
LDO2_VOUT LDO2_VSET 0x8 0.80 V
LDO2_BYPASS 0x0 Linear regulator mode.
LDO3_VOUT LDO3_VSET 0x8 0.80 V
LDO3_BYPASS 0x0 Linear regulator mode.
LDO4_VOUT LDO4_VSET 0x38 1.800 V
LDO1_PG_WINDOW LDO1_OV_THR 0x2 +4% / +40 mV
LDO1_UV_THR 0x2 -4% / -40 mV
LDO2_PG_WINDOW LDO2_OV_THR 0x2 +4% / +40 mV
LDO2_UV_THR 0x2 -4% / -40 mV
LDO3_PG_WINDOW LDO3_OV_THR 0x2 +4% / +40 mV
LDO3_UV_THR 0x2 -4% / -40 mV
LDO4_PG_WINDOW LDO4_OV_THR 0x2 +4% / +40 mV
LDO4_UV_THR 0x2 -4% / -40 mV
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.
5.5 VCCA Settings
These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C
after startup.
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Table 5-6. VCCA NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
VCCA_VMON_CTRL VMON_DEGLITCH_SE
L
0x1 20 us 0x1 VCCA 20us, VMON/BUCK
20us
VMON2_RV_SEL 0x0 Disabled
VMON2_EN 0x0 Disabled; OV and UV
comparators.
VMON1_RV_SEL 0x0 Disabled
VMON1_EN 0x0 Disabled; OV and UV
comparators.
VCCA_VMON_EN 0x1 Enabled; OV and UV
comparators.
0x1 Enabled; OV and UV
comparators.
VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% 0x7 +10%
VCCA_UV_THR 0x7 -10% 0x7 -10%
VCCA_PG_SET 0x0 3.3 V 0x0 3.3 V
5.6 GPIO Settings
These settings detail the default configurations of the GPIO rails. All these settings can be changed though I2C
after startup. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF
and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option,
see the Digital Signal Descriptions section in TPS6594-Q1 and LP8764-Q1 data sheets.
Table 5-7. GPIO NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
GPIO1_CONF GPIO1_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO1_DIR 0x0 Input 0x1 Output
GPIO1_SEL 0x1 SCL_I2C2/CS_SPI 0x0 GPIO1
GPIO1_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO1_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
GPIO2_CONF GPIO2_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO2_DIR 0x0 Input 0x0 Input
GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI 0x0 GPIO2
GPIO2_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO2_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x1 8 us deglitch time.
GPIO3_CONF GPIO3_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO3_DIR 0x0 Input 0x0 Input
GPIO3_SEL 0x2 NERR_SOC 0x0 GPIO3
GPIO3_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO3_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO3_DEGLITCH_EN 0x1 8 us deglitch time. 0x1 8 us deglitch time.
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Table 5-7. GPIO NVM Settings (continued)
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
GPIO4_CONF GPIO4_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO4_DIR 0x0 Input 0x0 Input
GPIO4_SEL 0x6 LP_WKUP1 0x0 GPIO4
GPIO4_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO4_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO4_DEGLITCH_EN 0x1 8 us deglitch time. 0x1 8 us deglitch time.
GPIO5_CONF GPIO5_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO5_DIR 0x0 Input 0x0 Input
GPIO5_SEL 0x1 SCLK_SPMI 0x0 GPIO5
GPIO5_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO5_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x1 8 us deglitch time.
GPIO6_CONF GPIO6_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO6_DIR 0x0 Input 0x0 Input
GPIO6_SEL 0x1 SDATA_SPMI 0x0 GPIO6
GPIO6_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO6_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x1 8 us deglitch time.
GPIO7_CONF GPIO7_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO7_DIR 0x0 Input 0x1 Output
GPIO7_SEL 0x1 NERR_MCU 0x0 GPIO7
GPIO7_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO7_DEGLITCH_EN 0x1 8 us deglitch time. 0x0 No deglitch, only
synchronization.
GPIO8_CONF GPIO8_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO8_DIR 0x0 Input 0x0 Input
GPIO8_SEL 0x3 DISABLE_WDOG 0x1 SCLK_SPMI
GPIO8_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO8_DEGLITCH_EN 0x1 8 us deglitch time. 0x0 No deglitch, only
synchronization.
GPIO9_CONF GPIO9_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO9_DIR 0x1 Output 0x0 Input
GPIO9_SEL 0x0 GPIO9 0x1 SDATA_SPMI
GPIO9_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO9_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO9_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
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Table 5-7. GPIO NVM Settings (continued)
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
GPIO10_CONF GPIO10_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO10_DIR 0x0 Input 0x1 Output
GPIO10_SEL 0x0 GPIO10 0x0 GPIO10
GPIO10_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO10_DEGLITCH_E
N
0x1 8 us deglitch time. 0x0 No deglitch, only
synchronization.
GPIO11_CONF GPIO11_OD 0x1 Open-drain output
GPIO11_DIR 0x1 Output
GPIO11_SEL 0x2 NRSTOUT_SOC
GPIO11_PU_SEL 0x0 Pull-down resistor selected
GPIO11_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
GPIO11_DEGLITCH_E
N
0x0 No deglitch, only
synchronization.
NPWRON_CONF NPWRON_SEL 0x0 ENABLE
ENABLE_PU_SEL 0x0 Pull-down resistor selected
ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
ENABLE_DEGLITCH_E
N
0x1 8 us deglitch time when
ENABLE, 50 ms deglitch time
when NPWRON.
ENABLE_POL 0x0 Active high 0x0 Active high
NRSTOUT_OD 0x1 Open-drain output
GPIO_OUT_1 GPIO1_OUT(1) 0x0 Low 0x0 Low
GPIO2_OUT(1) 0x0 Low 0x0 Low
GPIO3_OUT(1) 0x0 Low 0x0 Low
GPIO4_OUT(1) 0x0 Low 0x0 Low
GPIO5_OUT(1) 0x0 Low 0x0 Low
GPIO6_OUT(1) 0x0 Low 0x0 Low
GPIO7_OUT(1) 0x0 Low 0x0 Low
GPIO8_OUT(1) 0x0 Low 0x0 Low
GPIO_OUT_2 GPIO9_OUT(1) 0x0 Low 0x0 Low
GPIO10_OUT(1) 0x0 Low 0x0 Low
GPIO11_OUT(1) 0x0 Low
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.
5.7 Finite State Machine (FSM) Settings
These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default
trigger for each system-level state is described. All these settings can be changed though I2C after startup.
Table 5-8. FSM NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
BUCK2_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
BUCK3_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
BUCK4_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
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Table 5-8. FSM NVM Settings (continued)
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
RAIL_SEL_2 BUCK5_GRP_SEL 0x2 SOC rail group
LDO1_GRP_SEL 0x1 MCU rail group
LDO2_GRP_SEL 0x2 SOC rail group
LDO3_GRP_SEL 0x1 MCU rail group
RAIL_SEL_3 VMON2_GRP_SEL 0x0 No group assigned
VMON1_GRP_SEL 0x0 No group assigned
LDO4_GRP_SEL 0x2 SOC rail group
VCCA_GRP_SEL 0x1 MCU rail group 0x1 MCU rail group
FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x2 MCU power error 0x2 MCU power error
SOC_RAIL_TRIG 0x3 SOC power error 0x3 SOC power error
OTHER_RAIL_TRIG 0x3 SOC power error 0x3 SOC power error
SEVERE_ERR_TRIG 0x0 Immediate shutdown 0x0 Immediate shutdown
FSM_TRIG_SEL_2 MODERATE_ERR_TRI
G
0x1 Orderly shutdown 0x1 Orderly shutdown
5.8 Interrupt Settings
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be
changed though I2C after startup.
Table 5-9. Interrupt NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked 0x1 Masked
GPIO1_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO2_FSM_MASK 0x1 Masked 0x1 Masked
GPIO2_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO3_FSM_MASK 0x1 Masked 0x1 Masked
GPIO3_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO4_FSM_MASK 0x1 Masked 0x1 Masked
GPIO4_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
FSM_TRIG_MASK_2 GPIO5_FSM_MASK 0x1 Masked 0x1 Masked
GPIO5_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO6_FSM_MASK 0x1 Masked 0x1 Masked
GPIO6_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO7_FSM_MASK 0x1 Masked 0x1 Masked
GPIO7_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO8_FSM_MASK 0x1 Masked 0x1 Masked
GPIO8_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
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Table 5-9. Interrupt NVM Settings (continued)
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
FSM_TRIG_MASK_3 GPIO9_FSM_MASK 0x1 Masked 0x1 Masked
GPIO9_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO10_FSM_MASK 0x1 Masked 0x1 Masked
GPIO10_FSM_MASK_
POL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO11_FSM_MASK 0x1 Masked
GPIO11_FSM_MASK_
POL
0x0 Low; Masking sets signal
value to '0'
MASK_BUCK1_2 BUCK1_ILIM_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK1_OV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK1_UV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK2_ILIM_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK2_OV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK2_UV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
MASK_BUCK3_4 BUCK3_ILIM_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK3_OV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK3_UV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK4_OV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK4_UV_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BUCK4_ILIM_MASK 0x0 Interrupt generated 0x0 Interrupt generated
MASK_BUCK5 BUCK5_ILIM_MASK 0x0 Interrupt generated
BUCK5_OV_MASK 0x0 Interrupt generated
BUCK5_UV_MASK 0x0 Interrupt generated
MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated
LDO1_UV_MASK 0x0 Interrupt generated
LDO2_OV_MASK 0x0 Interrupt generated
LDO2_UV_MASK 0x0 Interrupt generated
LDO1_ILIM_MASK 0x0 Interrupt generated
LDO2_ILIM_MASK 0x0 Interrupt generated
MASK_LDO3_4 LDO3_OV_MASK 0x0 Interrupt generated
LDO3_UV_MASK 0x0 Interrupt generated
LDO4_OV_MASK 0x0 Interrupt generated
LDO4_UV_MASK 0x0 Interrupt generated
LDO3_ILIM_MASK 0x0 Interrupt generated
LDO4_ILIM_MASK 0x0 Interrupt generated
MASK_VMON VMON2_UV_MASK 0x1 Interrupt not generated.
VMON2_OV_MASK 0x1 Interrupt not generated.
VMON1_UV_MASK 0x1 Interrupt not generated.
VMON1_OV_MASK 0x1 Interrupt not generated.
VCCA_OV_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
VCCA_UV_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
www.ti.com Static NVM Settings
SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022
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Powering DRA821 with TPS6594-Q1 and LP8764-Q1 19
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Table 5-9. Interrupt NVM Settings (continued)
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
MASK_GPIO1_8_FALL GPIO1_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO2_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO3_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO4_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO5_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO6_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO7_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO8_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
MASK_GPIO1_8_RISE GPIO1_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO2_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO3_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO4_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO5_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO6_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO7_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO8_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
MASK_GPIO9_11 /
MASK_GPIO9_10
GPIO9_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO9_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO10_FALL_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO11_FALL_MASK 0x1 Interrupt not generated.
GPIO10_RISE_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
GPIO11_RISE_MASK 0x1 Interrupt not generated.
MASK_STARTUP NPWRON_START_MA
SK
0x1 Interrupt not generated.
ENABLE_MASK 0x0 Interrupt generated 0x1 Interrupt not generated.
FSD_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
MASK_MISC TWARN_MASK 0x0 Interrupt generated 0x0 Interrupt generated
BIST_PASS_MASK 0x0 Interrupt generated 0x0 Interrupt generated
EXT_CLK_MASK 0x1 Interrupt not generated. 0x1 Interrupt not generated.
MASK_MODERATE_E
RR
BIST_FAIL_MASK 0x0 Interrupt generated 0x0 Interrupt generated
REG_CRC_ERR_MAS
K
0x0 Interrupt generated 0x0 Interrupt generated
SPMI_ERR_MASK 0x0 Interrupt generated 0x0 Interrupt generated
NPWRON_LONG_MAS
K
0x1 Interrupt not generated.
PFSM_ERR_MASK 0x0 Interrupt generated 0x0 Interrupt generated
MASK_FSM_ERR WD_MASK 0x1 Interrupt not generated.
IMM_SHUTDOWN_MA
SK
0x0 Interrupt generated 0x0 Interrupt generated
MCU_PWR_ERR_MAS
K
0x0 Interrupt generated 0x0 Interrupt generated
SOC_PWR_ERR_MAS
K
0x0 Interrupt generated 0x0 Interrupt generated
ORD_SHUTDOWN_MA
SK
0x0 Interrupt generated 0x0 Interrupt generated
Static NVM Settings www.ti.com
20 Powering DRA821 with TPS6594-Q1 and LP8764-Q1 SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022
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