Texas Instruments TPS40193EVM-001 User manual

User's GuideSLUU274 – May 2007
Using the TPS40193EVM-001
The TPS40193EVM-001 evaluation module is a 12V to 1.8V synchronous buckconverter built around the TPS40193 synchronous buck controller. This moduleprovides a convenient test platform for both evaluating the TPS40193 controller in areal application and prototyping synchronous buck converters using the TPS40193controller.
Contents1 Introduction .......................................................................................... 22 TPS40193EVM-001 Electrical Performance Specifications ................................... 33 Schematic ........................................................................................... 44 General Configuration and Description .......................................................... 55 Test Setup ........................................................................................... 86 TPS40193EVM-001 Typical Performance Data and Characteristic Curves............... 117 EVM Assembly Drawings and Layout .......................................................... 148 Bill of Materials .................................................................................... 18
List of Figures
1 TPS40193EVM-001 Schematic ................................................................... 42 TPS40193EVM-001 Recommended Test Setup ............................................... 93 TPS40193EVM-001 Output Ripple Measurement—Tip and Barrel Using TP15 andTP16 .................................................................................................. 94 TPS40193EVM-001 Control Loop Measurement Setup ..................................... 105 TPS40193EVM-001 Efficiency vs Load Current .............................................. 116 TPS40193EVM-001 Output Voltage vs Load Current ( ±0.5% Window Shown) .......... 127 TPS40193EVM-001 Output Voltage Ripple ................................................... 128 TPS40193EVM-001 Switching Waveforms (V
IN
= 8V, I
OUT
= 10A) ......................... 139 TPS40193EVM-001 Switching Waveforms (V
IN
= 14V, I
OUT
= 10A) ....................... 1310 TPS40193EVM-001 Gain and Phase vs Frequency ......................................... 1411 TPS40193EVM-001 Gain and Phase vs Frequency ......................................... 1412 TPS40193EVM-001 Component Placement .................................................. 1513 TPS40193EVM-001 Silkscreen ................................................................. 1514 TPS40193EVM-001 Top Copper Layer ........................................................ 1615 TPS40193EVM-001 Bottom Copper Layer ................................................... 1616 TPS40193EVM-001 Internal Layer 1 ........................................................... 1717 TPS40193EVM-001 Internal Layer 2 ........................................................... 17
List of Tables
1 TPS40193EVM-001 Electrical and Performance Specifications ............................. 32 Adjusting V
OUT
with R7 ............................................................................. 53 Adjusting V
SCP
with R9 ............................................................................. 54 Test Point Descriptions ............................................................................ 65 Bill of Materials .................................................................................... 18
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1 Introduction
1.1 Description
1.2 Applications
1.3 Features
Introduction
The TPS40193EVM-001 evaluation module (EVM) is a synchronous buck converter that provides a fixed1.8V output at up to 10A from a 12V input bus. The EVM is designed to power up from a single supply, sono additional bias voltage is required for start-up. The demonstration module uses the TPS40193 reducedpin count mid-voltage synchronous buck controller.
The TPS40193EVM-001 is designed to use a regulated 12V (8V–14V) bus to produce a regulated 1.8Voutput at up to 10A of load current. The EVM is designed to demonstrate the capabilities of the TPS40193in a typical 12V bus to low-voltage application while providing a number of test points for evaluating theTPS40193 in a given application. The EVM can be modified to support output voltages from 0.9V to 3.3Vby changing a single set resistor.
•Non-isolated medium current point-of-load and low voltage bus converters•Networking equipment•Telecommunications equipment•Computer peripherals•Digital set-top box
•8V–14V input range•1.8V fixed output, adjustable with single resistor•10A dc steady state output current•300kHz switching frequency (fixed by TPS40193)•Single SO-8 MOSFETs for both main switch and synchronous rectifier•Double-sided, two active layer printed circuit board (PCB) with all components on top side– Test point signals routed on internal layers•Active converter area of less than 1.2in
2
(<1.54in ×0.76in)•Convenient test points for probing switching waveforms and non-invasive loop response testing
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2 TPS40193EVM-001 Electrical Performance Specifications
TPS40193EVM-001 Electrical Performance Specifications
Table 1 summarizes the electrical specifications of the TPS40193EVM-001.
Table 1. TPS40193EVM-001 Electrical and Performance Specifications
PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNITS
Input Characteristics
Input Voltage V
IN
8 12 14 VInput Current I
IN
V
IN
= Min, I
OUT
= Max 2.7 2.85 ANo Load Input Current V
IN
= Min, I
OUT
= 0A 48 60 mAInput UVLO V
IN_UVLO
I
OUT
= Min to Max 3.9 4.2 4.4 VInput OV V
IN_OV
I
OUT
= Min to Max N/A V
Output Characteristics
Output Voltage V
OUT
V
IN
= NOM, I
OUT
= NOM 1.86 1.8 1.84 VLine Regulation V
IN
= Min to Max, I
OUT
= NOM 0.5 %Load Regulation V
IN
= NOM, I
OUT
= Min to Max 0.5 %Output Voltage Ripple V
OUT_Ripple
V
IN
= NOM, I
OUT
= MAX 40 mV
PP
Output Current I
OUT
V
IN
= Min to Max 0 6 10 AOutput Over Current
I
OCP
V
IN
= NOM, V
OUT
= (V
OUT
– 5%) 19 AInception PointOutput OVP V
OVP
I
OUT
= Min to Max N/A VTransient Response
Load Step ∆I 0.75 x I
OUT_Max
to 0.25 ×I
OUT _Max
5 ALoad Slew Rate 5 A/ µsOvershoot 50 mVSettling Time ms
System Characteristics
Switching Frequency F
SW
250 300 350 kHzPeak Efficiency η
PK
V
IN
= NOM, I
OUT
= Min to Max 95 %Full Load Efficiency ηV
IN
= NOM, I
OUT
= Max 92 %Operating Temperature
T
OP
V
IN
= Min to Max, I
OUT
= Min to Max –40 +25 +60 °CRange
Mechanical
Characteristics
W Width 1.54 inDimensions
(Active Area)
L Length 0.76 in
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3 Schematic
1
Schematic
Figure 1 shows the schematic for this EVM. See Table 5 , the Bill of Materials, for specific values.
Figure 1. TPS40193EVM-001 Schematic
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4 General Configuration and Description
4.1 Adjusting Output Voltage (R7)
V = V
VOUT VREF ´R + R
R
8 7
7
(1)
4.2 Adjusting Short-Circuit Protection (R9)
General Configuration and Description
This section reviews the general configurations for using the TPS40193EVM-001.
The regulated output voltage can be adjusted within a limited range by changing the ground resistor in thefeedback resistor divider (R7). The output voltage is given by the formula shown in Equation 1 :
where:
•V
VREF
= 0.591V and•R
8
= 20k Ω
Table 2 contains common values for R7 to generate popular output voltages. The TPS40193EVM-001 isstable through these output voltages, but efficiency may suffer because the power stage is optimized for1.8V output.
Table 2. Adjusting V
OUT
with R7
V
OUT
R7 (k Ω)
3.3V 4.322.5V 6.192.25V 7.152.0V 8.251.8V 9.761.5V 13.01.2V 19.11.0V 28.70.9V 38.3
The values in Table 2 provide less than 1% nominal set-point error in the output voltage. If a tighternominal value is required, R5 can be used in parallel with R7 to obtain a wider range of resistor values,using commonly-available E96 resistors.
The TPS40193 uses a selectable current limit for short-circuit protection. The current limit is selected fromthree predefined levels by placing a resistor at R9. The TPS40193 compares the voltage drop across thehigh-side FET (VDD to SW) to an internal reference voltage selected during start-up. Table 3 shows thevoltage levels.
Table 3. Adjusting V
SCP
with R9
V
SCP
(min) R7 (k Ω)
88mV 3.9160mV Open228mV 12
The current before declaring short-circuit protection can be determined by dividing the V
SCP
by the R
DS(ON)of the high-side FET (Q2)
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4.3 Disable Jumper (JP1)
Placing the JP1 shunt in the Left Position
Dis En
JP 1
drives the Q1 FET to pull the TPS40193 EN pin low,
disabling the controller. Removing the JP1 shunt or installing it in the Right Position
Dis En
JP 1
shorts the Q1
4.4 Test Point Descriptions
4.4.1 Input Voltage Monitoring (TP1, TP2)
General Configuration and Description
The TPS40193EVM-001 provides a three-pin, 100mil (0.100in) header and shunt for testing theTPS40193 disable function.
gate to ground and enables the TPS40193EVM-001 output.
Table 4 describes the TPS40196EVM-001 test points and identifies the respective sections of this userguide that discuss each test point.
Table 4. Test Point Descriptions
Test Point Label Use/Function Section
TP1 V
IN+
Monitor input voltage to the module
Section 4.4.1TP2 V
IN–
Monitor input voltage to the moduleTP3 Power-Good Power-Good output voltageTP4 Ext Source External source for Power-Good circuit
Section 4.4.2Ground for external source forTP5 GND
Power-Good
Section 4.4.3 ,TP6 COMP Monitor COMP voltage
Section 4.4.5Ground for SW, LDRV and HDRVTP7 GND
measurementsTP8 HDRV Monitor high-side gate drive (Q2)
Section 4.4.4TP9 SW Monitor switch node waveformsTP10 LDRV Monitor low-side gate drive (Q3)TP11 GND Ground for Loop Monitoring ProbeLoop injection point and injectionTP12 CH1
monitoring point
Section 4.4.5Loop injection point and outputTP13 CH2
response monitoring pointTP14 GND Ground for Loop Monitoring ProbeTP15 V
OUT+
Monitor output voltage from the module
Section 4.4.6TP16 V
OUT–
Monitor output voltage from the moduleInjection point to test pre-bias loadTP17 Pre-Bias Section 4.4.7compliance
The TPS40193EVM-001 provides two test points for measuring the voltage applied to the module. Thesetest points allow the user to measure the actual module voltage without losses from input cables andconnector losses. All input voltage measurements should be made between TP1 and TP2. To use TP1and TP2, connect a voltmeter positive terminal to TP1 and negative terminal to TP2.
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4.4.2 Power-Good (TP3, TP4, TP5)
4.4.3 Compensation and Initialization (TP6)
4.4.4 Switching Waveforms (TP7, TP8, TP9, TP10)
4.4.5 Loop Analysis (TP11, TP12, TP13, TP14)
4.4.6 Output Voltage and Monitoring (TP15, TP16)
4.4.7 Pre-Bias Input (TP17)
General Configuration and Description
The TPS40193EVM-001 has three test points to allow the user to evaluate the TPS40193 Power-Goodfunction. TP4 provides access to the Power-Good output of the TPS40193. It has a 100k Ωpull-up resistorto the TPS40193 5V regulator, and can be used as a logic signal with no additional requirements. TP3provides a connection for an external power-good source for 3.3V logic. TP3 is connected to thepower-good circuit through a 10k Ωpull-up resistor. TP5 provides a local ground access to connect aremote disable circuit.
The TPS40193EVM-001 also provides a test point connection to the COMP pin of the TPS40193controller. This test point can be used to monitor the COMP voltage during the controller Power OnInitialization that sets the controller short-circuit protection (SCP) threshold. The test point can also beused to monitor the pulse-width modulator (PWM) comparator input voltage (COMP) during operation, orused to measure the Power Stage Gain by following the Loop Analysis directions but moving Channel Aprobe from TP12 to TP6.
The TPS40193EVM-001 has three test points and a local ground connection (TP7) to monitor the mainswitching waveforms. Connect an oscilloscope probe to TP8 to monitor the high-side gate drive applied tothe gate of Q2. Connect an oscilloscope probe to TP9 to monitor the switch node voltage. Thegate-to-source voltage (V
GS
) of the high-side FET can be determined by a math function TP8—TP9 if bothchannels use the same scale. Connect an oscilloscope probe to TP9 to monitor the low-side gate driveapplied to the gate of Q3. Because the source of Q3 is connected directly to ground, no math function isrequired to determine the gate-to-source voltage of the low-side FET.
The TPS40193EVM-001 contains a 49.9 Ωseries resistor (R14) in the feedback loop to allow for matchedimpedance signal injection into the feedback for loop response analysis. An isolation transformer shouldbe used to apply a small (30mV or less) signal across R14 through TP12 and TP13. By monitoring the acinjection level at TP13 and the returned ac level at TP14, the power-supply loop response can bedetermined. Moving Channel A from TP12 to TP6 (COMP) the control-to-output response of the powerstage (also referred to as the power stage transfer function) can be directly measured. See Section 3.9xxfor a detailed procedure to perform loop response measurements.
There are two test points on the TPS40193EVM-001 for measuring the voltage generated by the module.These test points allow the user to measure the actual module output voltage without losses from outputcables and connector losses. All output voltage measurements should be made between TP15 and TP16.To use TP1 and TP2, connect a voltmeter positive terminal to TP15 and negative terminal to TP16. Foroutput ripple measurements, TP15 and TP16 allow a user to limit the ground loop area by using the tipand barrel measurement technique shown in Figure 3xx. (All output ripple measurements should be madeusing this method of measurement.)
The TPS40193EVM-001 contains a pre-bias injection circuit with 100 Ωresistor and series diode to allowtesting and evaluation of the TPS40193 pre-bias support compatibility. Apply a voltage less than the targetoutput voltage to TP17. Monitoring the output voltage during start-up demonstrates the ability of theTPS40193 to power up without drawing current from a pre-biased output. D2 prevents the output voltagefrom back-driving the pre-bias source.
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5 Test Setup
5.1 Equipment
5.1.1 Voltage Source
5.1.2 Meters
5.1.3 Loads
5.1.4 Oscilloscope
5.1.5 Recommended Wire Gauge
5.1.6 Other
Test Setup
V
IN
:The input voltage source (V
IN
) should be a 0V–15V variable dc source capable of 5A
DC
. Connect V
INto J1 as shown in Figure 2 .
A1: 0A
DC
–5A
DC
, ammeter
V1: V
IN
, 0V–15V voltmeter
V2: V
OUT
0V–5V voltmeter
LOAD1: The output load (LOAD1) should be an electronic constant current mode load capable of0A
DC
–10A
DC
at 1.8V.
Oscilloscope: A digital or analog oscilloscope can be used to measure the ripple voltage on V
OUT
. Theoscilloscope should be set for 1M Ωimpedance, 20MHz bandwidth, ac coupling, 1 µs/division horizontalresolution, and 10mV/division vertical resolution for taking output ripple measurements. TP15 and TP16can be used to measure the output ripple voltage by placing the oscilloscope probe tip through TP15 andholding the ground barrel to TP16, as shown in Figure 3 . For a hands-free approach, the loop in TP16 canbe cut and opened to cradle the probe barrel. Using a leaded ground connection may induce additionalnoise because of the large ground loop area.
V
IN
to J1: The connection between the source voltage, V
IN
, and J1 of HPA238 can carry as much as5A
DC
. The minimum recommended wire size is AWG #16 with the total length of wire less than four feet(two feet input, two feet return max recommended).
J2 to LOAD1 (Power): The power connection between J2 of HPA238 and LOAD1 can carry as much as10A
DC
. The minimum recommended wire size is 2x AWG #16, with the total length of wire less than twofeet (one foot output, one foot return max recommended).
Fan: This evaluation module includes components that can become hot to the touch. Because this EVM isnot enclosed (to allow probing of circuit nodes), a small fan capable of 200lfm–400lfm is required toreduce component surface temperatures to prevent user injury.
CAUTION
The EVM should not be left unattended while powered.
WARNINGThe EVM should not be probed while the fan is not running.
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5.2 Equipment Setup
LOAD1
1.8V @
10A
-
+
FAN
TP17
TEXAS INSTRUMENTS
TPS40193EVM-001
12V to 1.8V @ 10A
HPA238
J2
V2
-
+
TP16
TP15
Pre-Bias
See Tip and Barrel
Measurement for
Vout ripple
+-
-
+
V1
+
-
A1
-
+
V
VIN
TP7 TP9 TP10 TP8
TP12 TP11 TP13 TP14
GND LDRVSW HDRV
CH1 GND CH2 GND
TP2
TP1
Oscilloscope
1MW, AC
20mV / div
20MHz
J1
Dis
TP6
COMP
TP5
TP4
TP3
External Source
GND
PGOOD
En
JP 1
TP16TP15
Probe Tip
Metal Ground Barrier
Tip and Barrel V
ripple measurement
OUT
Test Setup
Figure 2 through Figure 4 show the basic test setup recommended to evaluate the TPS40193EVM-001.Please note that although the return for J1 and J2 are the same, the connections should remain separate,as shown in Figure 2 .
Figure 2. TPS40193EVM-001 Recommended Test Setup
Figure 3. TPS40193EVM-001 Output Ripple Measurement—Tip and Barrel Using TP15 and TP16
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Network
Analyzer
Isolation
Transformer LOAD1
1.8V @
10A
-
+
FAN
TP17
TEXAS INSTRUMENTS
TPS40193EVM-001
12V to 1.8V @ 10A
HPA238
J2
V2
-
+
TP16
TP15
Pre-Bias
See Tip and Barrel
Measurement for
Vout ripple
+-
-
+
V1
+
-
A1
-
+
V
VIN
TP7 TP9 TP10 TP8
TP12 TP11 TP13 TP14
GND LDRVSW HDRV
CH1 GND CH2 GND
TP2
TP1
Oscilloscope
1MW, AC
20mV / div
20MHz
J1
Dis
TP6
COMP
TP5
TP4
TP3
External Source
GND
PGOOD
En
JP 1
5.3 Start-up/Shutdown Procedure
5.4 Output Ripple Voltage Measurement Procedure
Test Setup
Figure 4. TPS40193EVM-001 Control Loop Measurement Setup
Follow these steps to start up and shut down the TPS40193EVM-001.Step 1. Increase V
IN
from 0V to 12V
DC
.Step 2. Vary LOAD1 from 0A
DC
to 10A
DC
.Step 3. Vary V
IN
from 8.0V
DC
to 14V
DC
.Step 4. Decrease V
IN
to 0V
DC
.Step 5. Decrease LOAD1 to 0A.
Follow these steps to measure the output ripple voltage on the TPS40193EVM-001.Step 1. Increase V
IN
from 0V to 12V
DC
.Step 2. Adjust LOAD1 to desired load between 0A
DC
and 10A
DC
.Step 3. Adjust V
IN
to desired load between 8.0V
DC
and 14V
DC
.Step 4. Connect oscilloscope probe to TP15 and TP16 as shown in Figure 3 .Step 5. Measure output ripple.Step 6. Decrease V
IN
to 0V
DC
.Step 7. Decrease LOAD1 to 0A.
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5.5 Control Loop Gain and Phase Measurement Procedure
20 LOG´Channel B
Channel A
(2)
5.6 Equipment Shutdown
6 TPS40193EVM-001 Typical Performance Data and Characteristic Curves
6.1 Efficiency
100
90
80
70
60
50
40
30
20
10
0
h - Efficiency (%)
0 2 46 8 10 12
I Load Current (A)-
LOAD
8V
12V
14V
V
V =
V =
IN
IN
IN
=
V = 1.8V
I = 0A 10A
OUT
OUT -
TPS40193EVM-001 Typical Performance Data and Characteristic Curves
Follow these steps to measure the control loop gain and phase on the TPS40193EVM-001.Step 1. Connect 1kHz–1MHz isolation transformer to TP12 and TP13 as shown in Figure 4 .Step 2. Connect input signal amplitude measurement probe (Channel A) to TP12 as shown in Figure 4 .Step 3. Connect output signal amplitude measurement probe (Channel B) to TP13 as shown in Figure 4 .Step 4. Connect ground lead of Channel A and Channel B to TP11 and TP14, as shown in Figure 4 .Step 5. Inject 30mV (or less) signal across R14 through isolation transformer.Step 6. Sweep frequency from 1kHz to 1MHz, with 10Hz or lower post filter.Step 7. Control loop gain can be measured by Equation 2 :
Step 8. Control loop phase is measured by the phase difference between Channel A and Channel B.Step 9. Control to output response (power stage transfer function) can be measured by connectingChannel A probe to TP6 (COMP) and Channel B probe to TP13.Step 10. Output to control response (error amplifier transfer function) can be measured by connectingChannel B probe to TP6 (COMP) and Channel A probe to TP12Step 11. Disconnect isolation transformer from TP12 and TP13 before making other measurements(signal injection into feedback may interfere with accuracy of other measurements).
Follow these steps to power down the EVM.Step 1. Shut down oscilloscope.Step 2. Shut down V
IN
.Step 3. Shut down LOAD1.Step 4. Shut down fan.
Figure 5 through Figure 11 present typical performance curves for the TPS40193EVM-001. Since actualperformance data can be affected by measurement techniques and environmental variables, these curvesare presented for reference only and may differ from actual field measurements.
Figure 5. TPS40193EVM-001 Efficiency vs Load Current
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6.2 Line and Load Regulation
1.817
1.815
1.813
1.811
1.809
1.807
1.805
1.803
1.801
1.799
V Output Voltage (V)-
OUT
0 2 46 8 10
I Load Current (A)-
LOAD
8V
12V
14V
V
V =
V =
IN
IN
IN
=
V = 1.8V
I = 0A 10A
OUT
OUT -
6.3 Output Voltage Ripple
TPS40193EVM-001 Typical Performance Data and Characteristic Curves
Figure 6. TPS40193EVM-001 Output Voltage vs Load Current(±0.5% Window Shown)
Figure 7. TPS40193EVM-001 Output Voltage Ripple
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6.4 Switch Node
TPS40193EVM-001 Typical Performance Data and Characteristic Curves
Ch1: TP9 (SW); Ch2: TP8 (HDRV); Ch3: TP10 (LDRV).
Figure 8. TPS40193EVM-001 Switching Waveforms (V
IN
= 8V, I
OUT
= 10A)
Ch1: TP9 (SW); Ch2: TP8 (HDRV); Ch3: TP10 (LDRV).
Figure 9. TPS40193EVM-001 Switching Waveforms (V
IN
= 14V, I
OUT
= 10A)
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6.5 Control Loop Bode Plot
6.5.1 Low Line (V
IN
= 8V)
60
40
20
0
20
40
60
-
-
-
Gain (dB)
100 1k 10k 100k 1M
Frequency (Hz)
180
150
120
90
60
30
0
30
60
90
120
150
180
-
-
-
-
-
-
Phase ( )
°
Gain Phase
Margin
V = 8V
V = 1.8V
I = 10A
IN
OUT
OUT
Bandwidth: 46kHz
Phase Margin: 53°
6.5.2 High Line (V
IN
= 14V)
60
40
20
0
20
40
60
-
-
-
Gain (dB)
100 1k 10k 100k 1M
Frequency (Hz)
180
150
120
90
60
30
0
30
60
90
120
150
180
-
-
-
-
-
-
Phase ( )
°
Gain Phase
Margin
V = 14V
V = 1.8V
I = 10A
IN
OUT
OUT
Bandwidth: 68kHz
Phase Margin: 45°
7 EVM Assembly Drawings and Layout
EVM Assembly Drawings and Layout
Figure 10. TPS40193EVM-001 Gain and Phase vs Frequency
Figure 11. TPS40193EVM-001 Gain and Phase vs Frequency
Figure 12 through Figure 17 show the design of the TPS40193EVM-001 printed circuit board (PCB). TheEVM has been designed using a 4-layer, 2oz., copper-clad PCB (2.5in x 2.5in), with all components in a1.54in x 0.76in active area on the top side and all active traces to the top and bottom layers of the board.This configuration allows the user to easily view, probe and evaluate the TPS40193 control IC in apractical, double-sided application. Moving components to both sides of the PCB or using additionalinternal layers can offer additional size reduction for space-constrained systems.
Unless otherwise specified, these figures illustrate the view from the top side of the PCB.
Note: Board layouts are not to scale. These figures are intended to show how the board is laidout; they are not intended to be used for manufacturing TPS40193EVM-001 PCBs.
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TPS40193EVM-001
TEXAS
INSTRUMENTS
EVM Assembly Drawings and Layout
Figure 12. TPS40193EVM-001 Component Placement
Figure 13. TPS40193EVM-001 Silkscreen
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EVM Assembly Drawings and Layout
Figure 14. TPS40193EVM-001 Top Copper Layer
Figure 15. TPS40193EVM-001 Bottom Copper Layer
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EVM Assembly Drawings and Layout
Figure 16. TPS40193EVM-001 Internal Layer 1
Figure 17. TPS40193EVM-001 Internal Layer 2
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8 Bill of Materials
Bill of Materials
Table 5 lists the EVM components as configured according to the schematic (see Figure 1 ).
Table 5. Bill of MaterialsQty RefDes Value Description Size Part Number MFR
1 C1 47pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD
1 C11 1.0 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 STD STD
1 C12 0.1 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 STD STD
1 C2 1000pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD
1 C3 2200pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD
1 C4 1.0 µF Capacitor, Ceramic, 25V, X5R, 20% 0805 STD STD
1 C5 4.7 µF Capacitor, Ceramic, 10V, X5R, 20% 0805 STD STD
1 C6 220nF Capacitor, Ceramic, 10V, X5R, 20% 0603 Std Std
2 C7, C9 22 µF Capacitor, Ceramic, 25V, X5R, 20% 1210 C3225X7R1E1 TDK06M
2 C8, C10 100 µF Capacitor, Ceramic, 6.3V, X5R, 20% 1210 C3225X5R0J10 TDK7M
1 D2 BAT54HT1 Diode, Schottky, 200-mA, 30-V SOD323 BAT54HT1 On Semi
2 J1, J2 ED1609-ND Terminal Block, 2-pin, 15-A, 5.1mm 0.40in x 0.35in ED1609 OST
1 JP1 PTC36SAAN Header, 3-pin, 100mil spacing, (36-pin strip) 0.100in x 3in PTC36SAAN Sullins
1 L1 2 Inductor, SMT, xxA 0.512in x 0.571in PG0077.xxx Pulse
1 Q1 2N7002W Mosfet, N-Ch, VDS 60v, RDS 2 ohms, ID SOT-323 (SC-70) 2N7002W-7 Diodes Inc115 mA
1 Q2** IRF7828 XSTR, MOSFET, N-Chan, 30V, Rds(ON) SO8 IRF7828 IR9.5m Ω
1 Q3** IRF7832Z XSTR, MOSFET, N-Chan, 30V, Rds(ON) SO8 IRF7832Z IR4.8m Ω
2 R1, R2 51k Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R10 1.0k Resistor, Chip, 1/16W, 1% 0603 Std Std
2 R11, R13 0 Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R12 100k Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R14 49.9 Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R15 10k Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R16 100 Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R3 5.1k Resistor, Chip, 1/16W, 5% 0603 Std Std
1 R4 100k Resistor, Chip, 1/16W, 1% 0603 Std Std
0 R5 Open Resistor, Chip, 1/16W, 1% 0603 Std Std
1 R6 7.50k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 R7 9.76k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 R8 20k Resistor, Chip, 1/16W, 1% 0603 Std Std
1 R9 3.9k Resistor, Chip, 1/16W, 5% 0603 Std Std
4 TP1, TP4, 5010 Test Point, Red, Thru Hole 0.125in x 0.125in 5010 KeystoneTP15, TP17
6 TP2, TP5, 5011 Test Point, Black, Thru Hole 0.125in x 0.125in 5011 KeystoneTP7, TP11,
TP14, TP16
7 TP3, TP6, 5012 Test Point, White, Thru Hole 0.125in x 0.125in 5012 KeystoneTP8, TP9,TP10, TP12,TP13
1 U1 TPS40193DRC IC, Cost Optimized Mid Vin Freq. 300kHz DRC10 TPS40193DRC TexasSync. Buck controller Instruments
1 -— — PCB, 3 In x 3 In x 0.062 In — HPA238 Any
1 — — Shunt, 100-mil, Black 0.100 929950-00 3M
Using the TPS40193EVM-001 18 SLUU274 – May 2007Submit Documentation Feedback

EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling theproduct(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided arenot intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,including product safety and environmental measures typically found in end products that incorporate such semiconductorcomponents or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regardingelectromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet thetechnical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BYSELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDINGANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from allclaims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility totake any and all appropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHERFOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement ofpatents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling theproduct. This notice contains important safety information about temperatures and voltages. For additional information on TI’senvironmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, andcan radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of thisequipment in other environments may cause interference with radio communications, in which case the user at his own expensewill be required to take whatever measures may be required to correct this interference.EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 4.5V to 18V and the output voltage range of 0.6V to 5.0V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there arequestions concerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to theEVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the loadspecification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than +40 °C. The EVM is designed tooperate properly with certain components above +40 °C as long as the input and output ranges are maintained. These componentsinclude but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types ofdevices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes nearthese devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2007, Texas Instruments Incorporated

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TPS40193EVM-001