Texas Instruments DEM-DAI1802 User manual

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March 2002 DAV Digital Audio/Imaging Japan (DAL)
User’s Guide
SLEU017

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Copyright 2002, Texas Instruments Incorporated

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Copyright 2002, Texas Instruments Incorporated

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astheinputandoutput rangesare maintained.Thesecomponentsincludebut arenot limited
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When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
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Copyright 2002, Texas Instruments Incorporated

Related Documentation From Texas Instruments
v
Preface
Read This First
About This Manual
Thisuser’sguidedescribestheconstructionandcircuitryoftheDEM-DAI1802
demonstration board. It also contains instructions for connecting and setting
up the DEM-DAI1802 for operation.
How to Use This Manual
This document contains the following chapters:
Chapter 1 –Description
Chapter 2 –Schematics and Printed-Circuit Board
Related Documentation From Texas Instruments
PCM1802 Single-Ended Analog-Input 24-Bit, 96-kHz Stereo A/D Converter –
Literature No. SLES023
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
testedforcompliancewiththelimitsofcomputingdevicespursuanttosubpart
Jofpart15ofFCCrules,which aredesignedtoprovidereasonableprotection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.

vi

Contents
vii
Contents
1 Description 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 DEM-DAI1802 Basic Connection and Operation 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Configuration Controls 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Schematics and Printed-Circuit Board 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 DEM-DAI1802 Printed-Circuit Board 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 DEM-DAI1802 Schematics 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1–1 DEM-DAI1802 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Digital Signal I/F to PCM1802 (JP052) 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 DEM-DAI1802 Silkscreen 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 DEM-DAI1802 Top View 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 DEM-DAI1802 Bottom View 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 DEM-DAI1802 Analog Section Schematic Diagram 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 DEM-DAI1802 A/D Converter Section Schematic Diagram 2-6. . . . . . . . . . . . . . . . . . . . . . . . .
2–6 DEM-DAI1802 Regulator and Connector Schematic Diagram 2-6. . . . . . . . . . . . . . . . . . . . . . .
2–7 DEM-DAI1802 Digital Section (Digital Audio Interface) Schematic Diagram 2-7. . . . . . . . . . .

Contents
viii
Tables
1–1 Analog Input Selection (JP101/102)—CN101/102 for 2 V RMS,
CN103/104 for 1 V RMS 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 PCM1802: HPF Bypass Control (SW051) 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 PCM1802: Oversampling Control (SW051)—64 fSor 128 fS1-3. . . . . . . . . . . . . . . . . . . . . . . .
1–4 PCM1802: Master/Slave and Oversampling Rate Selection
(JP002/004/052 and SW002/051) 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 System-Clock Dividing Ratio for MCK: 128 fS-CS8404 (JP001) 1-3. . . . . . . . . . . . . . . . . . . . .
1–6 Bit-Clock Dividing Ratio (JP002) 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–7 LR-Clock Dividing Ratio (JP004) 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–8 Data Format Selection (JP003 and SW051) 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–9 System Clock Source Selection (JP005)—Internal Clock: X001/24.576 MHz,
External Clock Input: CN001 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–10 Manual Reset (SW003) 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–11 S/PDIF Transmitter Format: CS8404 Configuration (SW004) 1-5. . . . . . . . . . . . . . . . . . . . . . . .

1-1
Description
The DEM-DAI1802 is an evaluation board for the 96-kHz 24-bit PCM audio
A/Dconverter, PCM1802, with digitalaudiotransmitter,mode controls switch,
onboard oscillator, –6 dB amplifier, and LPF.
The DEM-DAI1802 operates from 5 V and ±15 V analog power supplies with
a 1-V RMS or 2-V RMS unbalanced analog signal input.
Topic Page
1.1 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 DEM-DAI1802 Basic Connection and Operation 1-2. . . . . . . . . . . . . . . . . .
Chapter 1

Block Diagram
1-2
1.1 Block Diagram
Figure 1–1.DEM-DAI1802 Block Diagram
Format Control
ADC
PCM1802
+5V–15V
SW051
OPT
COAX
JUMPER
+5 V
External–I/F
(CN002)
R–ch
L–ch
L/R–ch
FSYNC
BCLK
SCLK
DOUT
LRCK
24.576 MHz
DIT
CS8404
and
Logic
DAI
(BUS)
Select
and
Divider
3.3 V
REG.
+VDD
GND GND GND +15V
Sel.
For 2VRMS Input
–6 dB Amp.
and
2nd-Order LPF
OPA2134 R–ch
L–ch
1.2 DEM-DAI1802 Basic Connection and Operation
-Connect the 5.0-V and ±15-V power supplies to the VCC, AVCC, –AVCC,
andGNDonconnectorsCN051–CN055.The±15-Vsuppliesarerequired
only for 2-V RMS input.
-Connect the S/PDIF output to CN003 (COAX) or U001 (OPT).
-Ensure the presence of a system clock, supplied from the onboard
oscillator or external input clock connector (CN001) through
switch/jumper to PCM1802.
-Set the data format using SW001, JP003, and SW051.
-Select the master or slave mode using SW002, SW051, JP002, JP004,
and JP052.
1.2.1 Configuration Controls
Table 1–1.Analog Input Selection (JP101/102)—CN101/102 for 2 V RMS,
CN103/104 for 1 V RMS
Input Jumper-Pin Position
1-V RMS Direct-IN
2-V RMS –6dB/LPF
Table 1–2.PCM1802: HPF Bypass Control (SW051)
HPF Bypass BYPAS (SW051)
Enable H
Disable L

DEM-DAI1802 Basic Connection and Operation
1-3
Description
Table 1–3.PCM1802: Oversampling Control (SW051)—64 fSor 128 fS
Oversampling OSR (SW051)
×128 fSH
×64 fSL
Table 1–4.PCM1802: Master/Slave and Oversampling Rate Selection
(JP002/004/052 and SW002/051)
MODE1 MODE0 M/S select BCK sel LRCK sel FSYNC
MODE SYSCLK (SW051) (SW002) (JP002) (JP004) (JP052)
512 fSL H
Master mode 384 fSH L Master Remove
jum
p
er
p
in
Remove
jum
p
er
p
in
Remove
jum
p
er
p
ins
Master
mode
256 fSH H
Master
jumper-pin jumper-pin jumper-pins
Slave mode Auto-detect L L Slave
Select /2,
/4, or /8
(See
Table 1–6)
Select /128,
/256, or
/512 (See
Table 1–7)
Install
SLAVE
jumper-pin
Table 1–5.System-Clock Dividing Ratio for MCK: 128 fS-CS8404 (JP001)
Dividing Ratio Jumper-Pin
Position MCK Value (24.576 MHz oscillator: default)
1/1 /1 —
1/2 /2 12.288 MHz (128 fSfor fS= 96 kHz)
1/4 /4 6.144 MHz (128 fSfor fS= 48 kHz)
Table 1–6.Bit-Clock Dividing Ratio (JP002)
Dividing Ratio Jumper-Pin
Position BCK Value (24.576 MHz oscillator: default)
1/2 (Slave) /2 12.288 MHz (64 fSfor fS= 192 kHz)
1/4 (Slave) /4 6.144 MHz (64 fSfor fS= 96 kHz)
1/8 (Slave) /8 3.072 MHz (64 fSfor fS= 48 kHz)
–(Master) Remove —
Table 1–7.LR-Clock Dividing Ratio (JP004)
Dividing Ratio Jumper-Pin
Position MCK Value (24.576 MHz oscillator: default)
1/128 (Slave) /128 192 kHz
1/256 (Slave) /256 96 kHz
1/512 (Slave) /512 48 kHz
–(Master) Remove —

DEM-DAI1802 Basic Connection and Operation
1-4
Table 1–8.Data Format Selection (JP003 and SW051)
Data Format JP003 FMT1 FMT0
PCM, left justified, 24 bit L/J 24 L L
PCM, I2S, 24 bit I2S L H
Table 1–9.System Clock Source Selection (JP005)—Internal Clock: X001/24.576 MHz,
External Clock Input: CN001
Clock Source Jumper-Pin Position
Internal INT
External EXT
Table 1–10.Manual Reset (SW003)
Reset switch for CS8404
Figure 1–2.Digital Signal I/F to PCM1802 (JP052)
The digital signals generated by the internal
oscillator, divider, and PCM1802 are input to this
jumper. For each shorted pin the corresponding
digital signal is input to the PCM1802 and
CS8404.

DEM-DAI1802 Basic Connection and Operation
1-5
Description
Table 1–11.S/PDIF Transmitter Format: CS8404 Configuration (SW004)
Professional Mode Consumer Mode
Switch L=0,
H=1 Switch L=0, H=1
PRO 0 Professional mode PRO 1 Consumer mode
C9 C8,C9,C10,C11 –Channel mode (1 of 4) C15 Generation status
1 0000 –Not indicated (default: 2-ch) 1 0 –(see the S/PDIF standard)
0 0100 –Stereophonic 0 1 –(see the S/PDIF standard)
EM1,EM0 C2,C3,C4 –Emphasis (2 of 3) C8,C9 C8–C14 –Category code (2 of 7)
,
1 1 Not indicated (default: none)
,
1 1 0000 0000 –General
1 0 No emphasis 1 0 0100 0000 –PCM encoder/decoder
0 1 50/15Us 0 1 1000 0000 –CD
0 0 CCITT J.17 0 0 1100 0000 –DAT
C6,C7 C6,C7 –Sample frequency C3 C3,C4,C5 –Emphasis (1 of 3)
,
1 1 Not indicated (default: 48 kHz) 1 000 –None
1 0 48 kHz 0 100 –50/15Us
0 1 44.1 kHz C2 C2 –Copy/copyright
0 0 32 kHz 1 0 –Copy inhibited/copyright asserted
C1 C1 –Audio 0 1 –Copy permitted/copyright not asserted
1 0 –Normal audio FC1, C24,C25,C26,C27 –Sample frequency
0 1 –Nonaudio
,
FC0 1 1 44.1 kHz
TRNPT Transparent mode 1 0 48 kHz
0 0 –Normal operation 0 1 32 kHz
1 1 –Transparent mode 0 0 44.1 kHz, CD mode

1-6

2-1
Schematics and Printed-Circuit Board
Schematics and Printed-Circuit Board
This chapter presents the DEM-DAI1802 printed-circuit board and the DEM-
DAI1802 schematics.
Topic Page
2.1 DEM-DAI1802 Printed-Circuit Board 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 DEM-DAI1802 Schematics 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

DEM-DAI1802 Printed-Circuit Board
2-2
2.1 DEM-DAI1802 Printed-Circuit Board
Figure 2–1.DEM-DAI1802 Silkscreen

DEM-DAI1802 Printed-Circuit Board
2-3
Schematics and Printed-Circuit Board
Figure 2–2.DEM-DAI1802 Top VIew

DEM-DAI1802 Printed-Circuit Board
2-4
Figure 2–3.DEM-DAI1802 Bottom View

DEM-DAI1802 Schematics
2-5
Schematics and Printed-Circuit Board
2.2 DEM-DAI1802 Schematics
Figure 2–4.DEM-DAI1802 Analog Section Schematic Diagram
R108
4.7k
CN102
RCA pj
C110
10uF
/16V C112
10uF/16V
VINRU102
OPA2134PA
2/2
6
5
78
R110 4.7k
C108 100pF
JP102
FFC–4BMEP1
AVCC+
C114
10uF/16V
AVCC–
R104
3.3k
C104
1800pF
U102
OPA2134PA 1/2
2
3
1
R106 1.2k
C106 330pF
4
R102
2.4k
CN104
RCA pj
C102
10uF
/16V
R107
4.7k
CN101
RCA pj
C109
10uF
/16V C111
10uF/16V
VINLU101
OPA2134PA
2/2
6
5
78
R109 4.7k
C107 100pF
JP101
FFC–4BMEP1
AVCC+
C113
10uF/16V
AVCC–
R103
3.3k
C103
1800pF
U101
OPA2134PA 1/2
2
3
1
R105 1.2k
C105 330pF
4
R101
2.4k
CN103
RCA pj
C101
10uF
/16V

DEM-DAI1802 Schematics
2-6
Figure 2–5.DEM-DAI1802 A/D Converter Section Schematic Diagram
VDD
C066
0.1uF
U052 PCM1802
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11 C065
10uF/16V
VINL
VINR
VREF1
VREF2
VCC
AGND
PDWN
BYPAS
FSYNC
LRCK
MODE1
MODE0
FMT1
FMT0
TEST
SCKI
VDD
DGND
DOUT
BCK
VINR
VINL
VCC
SCLK
DATA
LRCK
FSYNC
JP052
FFC–12BMEP1
BCK
GND
M/S
1
2
3
4
5
6
SW051
DSS107
7
C061
10uF/16V
C062
0.1uF
C063
4.7uF/16V
C064
0.1uF
Figure 2–6.DEM-DAI1802 Regulator and Connector Schematic Diagram
VDD
C056
10uF
/16V
C054
100uF
/16V
C053
100uF
/16V
C051
0.1uF
C052
100uF
/16V
2
1
3
GND INOUT
C055
0.1uF
U051
REG1117–3.3
CN057
2
CN056 B2P–VH
1VCC
CN055
Banana
Jack
(Black)
CN053
Banana
Jack
(Blue)
CN054
Banana
Jack
(Red)
CN052
Banana
Jack
(Gray)
CN051
Banana
Jack
(Orange) AVCC+
AVCC–