Texas Instruments AM335 Series Product manual

AM335x ARM®Cortex™-A8 Microprocessors
(MPUs)
Technical Reference Manual
Literature Number: SPRUH73H
October 2011–Revised April 2013

Contents
Preface .................................................................................................................................... 149
1 Introduction .................................................................................................................... 150
1.1 AM335x Family ........................................................................................................... 150
1.1.1 Device Features ................................................................................................. 150
1.1.2 Device Identification ............................................................................................ 151
1.1.3 Feature Identification ........................................................................................... 151
1.2 Silicon Revision Functional Differences and Enhancements ....................................................... 153
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes ......................................................... 153
1.2.2 Changed BOOTP Identifier .................................................................................... 153
1.2.3 Changed Product String in USB Descriptor ................................................................. 153
1.2.4 Added DPLL Power Switch Control and Status Registers ................................................ 153
1.2.5 Added Control for CORE SRAM LDO Retention Mode .................................................... 153
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing ................................... 153
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn) .................................................... 153
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register ........................................ 154
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay ............................................ 154
1.2.10 Changed Default Value of RMII Clock Source ............................................................. 154
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot ........................ 154
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants ......................... 154
2 Memory Map ................................................................................................................... 155
2.1 ARM Cortex-A8 Memory Map .......................................................................................... 155
3 ARM MPU Subsystem ....................................................................................................... 164
3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 165
3.1.1 Features .......................................................................................................... 166
3.1.2 MPU Subsystem Integration ................................................................................... 166
3.1.3 MPU Subsystem Clock and Reset Distribution ............................................................. 167
3.1.4 ARM Subchip .................................................................................................... 170
3.1.5 Interrupt Controller .............................................................................................. 171
3.1.6 Power Management ............................................................................................ 171
3.1.7 ARM Programming Model ..................................................................................... 174
4 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) ............. 176
4.1 Introduction ............................................................................................................... 177
5 Graphics Accelerator (SGX) .............................................................................................. 178
5.1 Introduction ............................................................................................................... 179
5.1.1 POWERVR SGX Main Features .............................................................................. 179
5.1.2 SGX 3D Features ............................................................................................... 179
5.1.3 Universal Scalable Shader Engine (USSE) – Key Features .............................................. 180
5.1.4 Unsupported Features .......................................................................................... 181
5.2 Integration ................................................................................................................. 182
5.2.1 SGX530 Connectivity Attributes ............................................................................... 182
5.2.2 SGX530 Clock and Reset Management ..................................................................... 182
5.2.3 SGX530 Pin List ................................................................................................. 183
5.3 Functional Description ................................................................................................... 184
5.3.1 SGX Block Diagram ............................................................................................ 184
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5.3.2 SGX Elements Description .................................................................................... 184
6 Interrupts ........................................................................................................................ 186
6.1 Functional Description ................................................................................................... 187
6.1.1 Interrupt Processing ............................................................................................ 188
6.1.2 Register Protection ............................................................................................. 189
6.1.3 Module Power Saving .......................................................................................... 189
6.1.4 Error Handling ................................................................................................... 189
6.1.5 Interrupt Handling ............................................................................................... 189
6.2 Basic Programming Model .............................................................................................. 190
6.2.1 Initialization Sequence ......................................................................................... 190
6.2.2 INTC Processing Sequence ................................................................................... 190
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 194
6.2.4 Interrupt Preemption ............................................................................................ 198
6.2.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. 198
6.3 ARM Cortex-A8 Interrupts .............................................................................................. 199
6.4 PWM Events .............................................................................................................. 203
6.5 Interrupt Controller Registers ........................................................................................... 204
6.5.1 INTC Registers .................................................................................................. 204
7 Memory Subsystem ......................................................................................................... 250
7.1 GPMC ..................................................................................................................... 251
7.1.1 Introduction ...................................................................................................... 251
7.1.2 Integration ........................................................................................................ 254
7.1.3 Functional Description .......................................................................................... 256
7.1.4 Use Cases ....................................................................................................... 355
7.1.5 Registers ......................................................................................................... 366
7.2 OCMC-RAM .............................................................................................................. 398
7.2.1 Introduction ...................................................................................................... 398
7.2.2 Integration ........................................................................................................ 399
7.3 EMIF ....................................................................................................................... 400
7.3.1 Introduction ...................................................................................................... 400
7.3.2 Integration ........................................................................................................ 402
7.3.3 Functional Description .......................................................................................... 404
7.3.4 Use Cases ....................................................................................................... 422
7.3.5 EMIF4D Registers .............................................................................................. 422
7.3.6 DDR2/3/mDDR PHY Registers ............................................................................... 467
7.4 ELM ........................................................................................................................ 476
7.4.1 Introduction ...................................................................................................... 476
7.4.2 Integration ........................................................................................................ 477
7.4.3 Functional Description .......................................................................................... 478
7.4.4 Basic Programming Model ..................................................................................... 481
7.4.5 ELM Registers ................................................................................................... 487
8 Power, Reset, and Clock Management (PRCM) .................................................................... 499
8.1 Power, Reset, and Clock Management ............................................................................... 500
8.1.1 Introduction ...................................................................................................... 500
8.1.2 Device Power-Management Architecture Building Blocks ................................................. 500
8.1.3 Clock Management ............................................................................................. 500
8.1.4 Power Management ............................................................................................ 506
8.1.5 PRCM Module Overview ....................................................................................... 517
8.1.6 Clock Generation and Management .......................................................................... 519
8.1.7 Reset Management ............................................................................................. 535
8.1.8 Power-Up/Down Sequence .................................................................................... 544
8.1.9 IO State ........................................................................................................... 544
8.1.10 Voltage and Power Domains ................................................................................. 544
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8.1.11 Device Modules and Power Management Attributes List ................................................. 545
8.1.12 Clock Module Registers ....................................................................................... 548
8.1.13 Power Management Registers ............................................................................... 705
9 Control Module ................................................................................................................ 746
9.1 Introduction ............................................................................................................... 747
9.2 Functional Description ................................................................................................... 747
9.2.1 Control Module Initialization ................................................................................... 747
9.2.2 Pad Control Registers .......................................................................................... 747
9.2.3 EDMA Event Multiplexing ...................................................................................... 748
9.2.4 Device Control and Status ..................................................................................... 749
9.2.5 DDR PHY ........................................................................................................ 756
9.3 CONTROL_MODULE Registers ....................................................................................... 757
9.3.1 control_revision Register (offset = 0h) [reset = 0h] ......................................................... 762
9.3.2 control_hwinfo Register (offset = 4h) [reset = 0h] .......................................................... 763
9.3.3 control_sysconfig Register (offset = 10h) [reset = 0h] ..................................................... 764
9.3.4 control_status Register (offset = 40h) [reset = 0h] ......................................................... 765
9.3.5 control_emif_sdram_config Register (offset = 110h) [reset = 0h] ........................................ 766
9.3.6 core_sldo_ctrl Register (offset = 428h) [reset = 0h] ........................................................ 768
9.3.7 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h] ....................................................... 769
9.3.8 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h] ................................................... 770
9.3.9 bandgap_ctrl Register (offset = 448h) [reset = 0h] ......................................................... 771
9.3.10 bandgap_trim Register (offset = 44Ch) [reset = 0h] ....................................................... 772
9.3.11 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h] .................................................. 773
9.3.12 mosc_ctrl Register (offset = 468h) [reset = 0h] ............................................................ 774
9.3.13 deepsleep_ctrl Register (offset = 470h) [reset = 0h] ...................................................... 775
9.3.14 dpll_pwr_sw_status (offset = 50Ch) [reset = 0h] .......................................................... 776
9.3.15 device_id Register (offset = 600h) [reset = 0x] ............................................................ 777
9.3.16 dev_feature Register (offset = 604h) [reset = 0h] ......................................................... 778
9.3.17 init_priority_0 Register (offset = 608h) [reset = 0h] ........................................................ 779
9.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h] ....................................................... 780
9.3.19 mmu_cfg Register (offset = 610h) [reset = 0h] ............................................................. 781
9.3.20 tptc_cfg Register (offset = 614h) [reset = 0h] .............................................................. 782
9.3.21 usb_ctrl0 Register (offset = 620h) [reset = 0h] ............................................................. 783
9.3.22 usb_sts0 Register (offset = 624h) [reset = 0h] ............................................................. 785
9.3.23 usb_ctrl1 Register (offset = 628h) [reset = 0h] ............................................................. 786
9.3.24 usb_sts1 Register (offset = 62Ch) [reset = 0h] ............................................................ 788
9.3.25 mac_id0_lo Register (offset = 630h) [reset = 0h] .......................................................... 789
9.3.26 mac_id0_hi Register (offset = 634h) [reset = 0h] .......................................................... 790
9.3.27 mac_id1_lo Register (offset = 638h) [reset = 0h] .......................................................... 791
9.3.28 mac_id1_hi Register (offset = 63Ch) [reset = 0h] ......................................................... 792
9.3.29 dcan_raminit Register (offset = 644h) [reset = 0h] ........................................................ 793
9.3.30 usb_wkup_ctrl Register (offset = 648h) [reset = 0h] ...................................................... 794
9.3.31 gmii_sel Register (offset = 650h) [reset = 0h] .............................................................. 795
9.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h] .......................................................... 796
9.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h] .......................................................... 797
9.3.34 mreqprio_1 Register (offset = 674h) [reset = 0h] .......................................................... 798
9.3.35 hw_event_sel_grp1 Register (offset = 690h) [reset = 0h] ................................................ 799
9.3.36 hw_event_sel_grp2 Register (offset = 694h) [reset = 0h] ................................................ 800
9.3.37 hw_event_sel_grp3 Register (offset = 698h) [reset = 0h] ................................................ 801
9.3.38 hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h] ................................................ 802
9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h] ............................................................. 803
9.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h] ............................................ 804
9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h] ............................................... 805
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9.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h] ................................................. 806
9.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h] ................................................. 807
9.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h] ................................................. 808
9.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h] .............................................. 809
9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h] ................................................ 810
9.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h] ................................................ 811
9.3.48 bb_scale Register (offset = 7D0h) [reset = 0h] ............................................................ 812
9.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h] ................................................ 813
9.3.50 efuse_sma Register (offset = 7FCh) [reset = 0h] .......................................................... 814
9.3.51 conf_<module>_<pin> Register (offset = 800h–A34h) ................................................... 815
9.3.52 cqdetect_status Register (offset = E00h) [reset = 0h] .................................................... 816
9.3.53 ddr_io_ctrl Register (offset = E04h) [reset = 0h] ........................................................... 817
9.3.54 vtp_ctrl Register (offset = E0Ch) [reset = 0h] .............................................................. 818
9.3.55 vref_ctrl Register (offset = E14h) [reset = 0h] .............................................................. 819
9.3.56 tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h] ................................................. 820
9.3.57 tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h] ................................................. 821
9.3.58 tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h] ............................................... 822
9.3.59 tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] ............................................. 823
9.3.60 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h] .............................................. 824
9.3.61 tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h] .............................................. 825
9.3.62 tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h] .............................................. 826
9.3.63 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h] ............................................. 827
9.3.64 tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h] .............................................. 828
9.3.65 tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h] .............................................. 829
9.3.66 tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h] .............................................. 830
9.3.67 tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h] ............................................. 831
9.3.68 tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h] ............................................. 832
9.3.69 tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h] ............................................. 833
9.3.70 tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h] ............................................. 834
9.3.71 tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h] ............................................. 835
9.3.72 timer_evt_capt Register (offset = FD0h) [reset = 0h] ..................................................... 836
9.3.73 ecap_evt_capt Register (offset = FD4h) [reset = 0h] ..................................................... 837
9.3.74 adc_evt_capt Register (offset = FD8h) [reset = 0h] ....................................................... 838
9.3.75 reset_iso Register (offset = 1000h) [reset = 0h] ........................................................... 839
9.3.76 dpll_pwr_sw_ctrl Register (offset = 1318h) [reset = 0h] .................................................. 840
9.3.77 ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h] ....................................................... 842
9.3.78 sma2 Register (offset = 1320h) [reset = 0h] ................................................................ 843
9.3.79 m3_txev_eoi Register (offset = 1324h) [reset = 0h] ....................................................... 844
9.3.80 ipc_msg_reg0 Register (offset = 1328h) [reset = 0h] ..................................................... 845
9.3.81 ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h] ..................................................... 846
9.3.82 ipc_msg_reg2 Register (offset = 1330h) [reset = 0h] ..................................................... 847
9.3.83 ipc_msg_reg3 Register (offset = 1334h) [reset = 0h] ..................................................... 848
9.3.84 ipc_msg_reg4 Register (offset = 1338h) [reset = 0h] ..................................................... 849
9.3.85 ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h] ..................................................... 850
9.3.86 ipc_msg_reg6 Register (offset = 1340h) [reset = 0h] ..................................................... 851
9.3.87 ipc_msg_reg7 Register (offset = 1344h) [reset = 0h] ..................................................... 852
9.3.88 ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h] ................................................... 853
9.3.89 ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h] ................................................... 855
9.3.90 ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h] .................................................. 857
9.3.91 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ................................................... 859
9.3.92 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ................................................... 861
10 Interconnects .................................................................................................................. 863
10.1 Introduction ............................................................................................................... 864
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10.1.1 Terminology ..................................................................................................... 864
10.1.2 L3 Interconnect ................................................................................................. 864
10.1.3 L4 Interconnect ................................................................................................. 868
11 Enhanced Direct Memory Access (EDMA) ........................................................................... 869
11.1 Introduction ............................................................................................................... 870
11.1.1 EDMA3 Controller Block Diagram ........................................................................... 870
11.1.2 Third-Party Channel Controller (TPCC) Overview ......................................................... 870
11.1.3 Third-Party Transfer Controller (TPTC) Overview ......................................................... 871
11.2 Integration ................................................................................................................. 873
11.2.1 Third-Party Channel Controller (TPCC) Integration ....................................................... 873
11.2.2 Third-Party Transfer Controller (TPTC) Integration ....................................................... 874
11.3 Functional Description ................................................................................................... 876
11.3.1 Functional Overview ........................................................................................... 876
11.3.2 Types of EDMA3 Transfers ................................................................................... 879
11.3.3 Parameter RAM (PaRAM) .................................................................................... 881
11.3.4 Initiating a DMA Transfer ..................................................................................... 893
11.3.5 Completion of a DMA Transfer ............................................................................... 896
11.3.6 Event, Channel, and PaRAM Mapping ...................................................................... 897
11.3.7 EDMA3 Channel Controller Regions ........................................................................ 899
11.3.8 Chaining EDMA3 Channels .................................................................................. 901
11.3.9 EDMA3 Interrupts .............................................................................................. 902
11.3.10 Memory Protection ........................................................................................... 908
11.3.11 Event Queue(s) ............................................................................................... 912
11.3.12 EDMA3 Transfer Controller (EDMA3TC) .................................................................. 914
11.3.13 Event Dataflow ................................................................................................ 917
11.3.14 EDMA3 Prioritization ......................................................................................... 917
11.3.15 EDMA3 Operating Frequency (Clock Control) ............................................................ 918
11.3.16 Reset Considerations ........................................................................................ 918
11.3.17 Power Management .......................................................................................... 918
11.3.18 Emulation Considerations ................................................................................... 918
11.3.19 EDMA Transfer Examples ................................................................................... 920
11.3.20 EDMA Events ................................................................................................. 936
11.4 EDMA3 Registers ........................................................................................................ 939
11.4.1 EDMA3 Channel Controller Registers ....................................................................... 939
11.4.2 EDMA3 Transfer Controller Registers ....................................................................... 993
11.5 Appendix A .............................................................................................................. 1018
11.5.1 Debug Checklist .............................................................................................. 1018
11.5.2 Miscellaneous Programming/Debug Tips ................................................................. 1019
11.5.3 Setting Up a Transfer ........................................................................................ 1020
12 Touchscreen Controller .................................................................................................. 1022
12.1 Introduction .............................................................................................................. 1023
12.1.1 TSC_ADC Features .......................................................................................... 1023
12.1.2 Unsupported TSC_ADC_SS Features .................................................................... 1023
12.2 Integration ............................................................................................................... 1024
12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 1024
12.2.2 TSC_ADC Clock and Reset Management ................................................................ 1025
12.2.3 TSC_ADC Pin List ............................................................................................ 1025
12.3 Functional Description ................................................................................................. 1026
12.3.1 HW Synchronized or SW Channels ........................................................................ 1026
12.3.2 Open Delay and Sample Delay ............................................................................. 1026
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................ 1026
12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 1026
12.3.5 Interrupts ...................................................................................................... 1026
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12.3.6 DMA Requests ................................................................................................ 1027
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1027
12.4 Operational Modes ..................................................................................................... 1029
12.4.1 PenCtrl and PenIRQ ......................................................................................... 1030
12.5 Touchscreen Controller Registers .................................................................................... 1033
12.5.1 TSC_ADC_SS Registers .................................................................................... 1033
13 LCD Controller ............................................................................................................... 1097
13.1 Introduction .............................................................................................................. 1098
13.1.1 Purpose of the Peripheral ................................................................................... 1098
13.1.2 Features ....................................................................................................... 1099
13.2 Integration ............................................................................................................... 1100
13.2.1 LCD Controller Connectivity Attributes .................................................................... 1100
13.2.2 LCD Controller Clock and Reset Management ........................................................... 1101
13.2.3 LCD Controller Pin List ...................................................................................... 1101
13.3 Functional Description ................................................................................................. 1102
13.3.1 Clocking ........................................................................................................ 1102
13.3.2 LCD External I/O Signals .................................................................................... 1104
13.3.3 DMA Engine ................................................................................................... 1105
13.3.4 LIDD Controller ............................................................................................... 1106
13.3.5 Raster Controller ............................................................................................. 1108
13.3.6 Interrupt Conditions .......................................................................................... 1119
13.3.7 DMA ............................................................................................................ 1121
13.3.8 Power Management .......................................................................................... 1121
13.4 Programming Model .................................................................................................... 1122
13.4.1 LCD Character Displays ..................................................................................... 1122
13.4.2 Active Matrix Displays ....................................................................................... 1125
13.4.3 System Interaction ........................................................................................... 1125
13.4.4 Palette Lookup ................................................................................................ 1125
13.4.5 Test Logic ..................................................................................................... 1127
13.4.6 Disable and Software Reset Sequence ................................................................... 1127
13.4.7 Precedence Order for Determining Frame Buffer Type ................................................. 1128
13.5 LCD Registers .......................................................................................................... 1128
13.5.1 PID Register (offset = 0h) [reset = 0h] ..................................................................... 1130
13.5.2 CTRL Register (offset = 4h) [reset = 0h] .................................................................. 1131
13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h] .......................................................... 1132
13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h] .................................................. 1133
13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h] .................................................. 1134
13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h] .................................................. 1135
13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h] ................................................. 1136
13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h] .................................................. 1137
13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h] .................................................. 1138
13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h] ................................................... 1139
13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h] ............................................. 1141
13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h] ............................................. 1142
13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h] ............................................. 1143
13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h] ........................................... 1145
13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h] ......................................... 1146
13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h] .................................................. 1147
13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h] ............................................ 1148
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h] ........................................ 1149
13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h] ........................................... 1150
13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] ........................................ 1151
13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] ...................................................... 1152
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13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h] ............................................... 1153
13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h] ...................................................... 1155
13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h] ................................................ 1157
13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h] ............................................ 1159
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h] .................................................. 1161
13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h] .................................................... 1162
14 Ethernet Subsystem ....................................................................................................... 1163
14.1 Introduction .............................................................................................................. 1164
14.1.1 Features ....................................................................................................... 1164
14.1.2 Unsupported Features ....................................................................................... 1165
14.2 Integration ............................................................................................................... 1166
14.2.1 Ethernet Switch Connectivity Attributes ................................................................... 1167
14.2.2 Ethernet Switch Clock and Reset Management .......................................................... 1168
14.2.3 Ethernet Switch Pin List ..................................................................................... 1169
14.2.4 Ethernet Switch RMII Clocking Details .................................................................... 1169
14.2.5 GMII Interface Signal Connections and Descriptions .................................................... 1170
14.2.6 RMII Signal Connections and Descriptions ............................................................... 1173
14.2.7 RGMII Signal Connections and Descriptions ............................................................. 1174
14.3 Functional Description ................................................................................................. 1176
14.3.1 CPSW_3G Subsystem ....................................................................................... 1176
14.3.2 CPSW_3G ..................................................................................................... 1181
14.3.3 Ethernet Mac Sliver (CPGMAC_SL) ....................................................................... 1223
14.3.4 Command IDLE ............................................................................................... 1225
14.3.5 RMII Interface ................................................................................................. 1225
14.3.6 RGMII Interface ............................................................................................... 1226
14.3.7 Common Platform Time Sync (CPTS) ..................................................................... 1228
14.3.8 MDIO ........................................................................................................... 1233
14.4 Software Operation ..................................................................................................... 1235
14.4.1 Transmit Operation ........................................................................................... 1235
14.4.2 Receive Operation ........................................................................................... 1237
14.4.3 Initializing the MDIO Module ................................................................................ 1238
14.4.4 Writing Data to a PHY Register ............................................................................ 1238
14.4.5 Reading Data from a PHY Register ........................................................................ 1239
14.4.6 Initialization and Configuration of CPSW .................................................................. 1239
14.5 Ethernet Subsystem Registers ....................................................................................... 1240
14.5.1 CPSW_ALE Registers ....................................................................................... 1240
14.5.2 CPSW_CPDMA Registers .................................................................................. 1255
14.5.3 CPSW_CPTS Registers ..................................................................................... 1308
14.5.4 CPSW_STATS Registers ................................................................................... 1321
14.5.5 CPDMA_STATERAM Registers ............................................................................ 1321
14.5.6 CPSW_PORT Registers ..................................................................................... 1355
14.5.7 CPSW_SL Registers ......................................................................................... 1410
14.5.8 CPSW_SS Registers ........................................................................................ 1424
14.5.9 CPSW_WR Registers ........................................................................................ 1437
14.5.10 Management Data Input/Output (MDIO) Registers ..................................................... 1473
15 Pulse-Width Modulation Subsystem (PWMSS) ................................................................... 1485
15.1 Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 1486
15.1.1 Introduction .................................................................................................... 1486
15.1.2 Integration ..................................................................................................... 1488
15.1.3 PWMSS Registers ........................................................................................... 1489
15.2 Enhanced PWM (ePWM) Module .................................................................................... 1494
15.2.1 Introduction .................................................................................................... 1494
15.2.2 Functional Description ....................................................................................... 1498
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15.2.3 Use Cases ..................................................................................................... 1557
15.2.4 Registers ...................................................................................................... 1581
15.3 Enhanced Capture (eCAP) Module .................................................................................. 1607
15.3.1 Introduction .................................................................................................... 1607
15.3.2 Functional Description ....................................................................................... 1608
15.3.3 Use Cases ..................................................................................................... 1618
15.3.4 Registers ...................................................................................................... 1634
15.4 Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 1650
15.4.1 Introduction .................................................................................................... 1650
15.4.2 Functional Description ....................................................................................... 1653
15.4.3 eQEP Registers .............................................................................................. 1672
16 Universal Serial Bus (USB) .............................................................................................. 1690
16.1 Introduction .............................................................................................................. 1691
16.1.1 Acronyms, Abbreviations, and Definitions ................................................................. 1691
16.1.2 USB Features ................................................................................................. 1692
16.1.3 Unsupported USB OTG and PHY Features .............................................................. 1693
16.2 Integration ............................................................................................................... 1694
16.2.1 USB Connectivity Attributes ................................................................................. 1694
16.2.2 USB Clock and Reset Management ....................................................................... 1695
16.2.3 USB Pin List ................................................................................................... 1695
16.2.4 USB GPIO Details ............................................................................................ 1695
16.2.5 USB Unbonded PHY Pads .................................................................................. 1696
16.3 Functional Description ................................................................................................. 1697
16.3.1 VBUS Voltage Sourcing Control ............................................................................ 1697
16.3.2 Pullup/PullDown Resistors .................................................................................. 1697
16.3.3 Role Assuming Method ...................................................................................... 1698
16.3.4 Clock, PLL, and PHY Initialization ......................................................................... 1698
16.3.5 Indexed and Non-Indexed Register Spaces .............................................................. 1698
16.3.6 Dynamic FIFO Sizing ........................................................................................ 1698
16.3.7 USB Controller Host and Peripheral Modes Operation .................................................. 1699
16.3.8 Protocol Description(s) ....................................................................................... 1701
16.3.9 Communications Port Programming Interface (CPPI) 4.1 DMA ....................................... 1734
16.3.10 USB 2.0 Test Modes ....................................................................................... 1758
16.4 Supported Use Cases ................................................................................................. 1759
16.5 USB Registers .......................................................................................................... 1760
16.5.1 USBSS Registers ............................................................................................. 1760
16.5.2 USB0_CTRL Registers ...................................................................................... 1803
16.5.3 USB1_CTRL Registers ...................................................................................... 1853
16.5.4 USB2PHY Registers ......................................................................................... 1901
16.5.5 CPPI_DMA Registers ........................................................................................ 1925
16.5.6 CPPI_DMA_SCHEDULER Registers ...................................................................... 2081
16.5.7 QUEUE_MGR Registers .................................................................................... 2084
17 Interprocessor Communication ........................................................................................ 3235
17.1 Mailbox ................................................................................................................... 3236
17.1.1 Introduction .................................................................................................... 3236
17.1.2 Integration ..................................................................................................... 3237
17.1.3 Functional Description ....................................................................................... 3238
17.1.4 Programming Guide .......................................................................................... 3242
17.1.5 MAILBOX Registers .......................................................................................... 3245
17.2 Spinlock .................................................................................................................. 3306
17.2.1 SPINLOCK Registers ........................................................................................ 3306
18 Multimedia Card (MMC) ................................................................................................... 3344
18.1 Introduction .............................................................................................................. 3345
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18.1.1 MMCHS Features ............................................................................................ 3345
18.1.2 Unsupported MMCHS Features ............................................................................ 3345
18.2 Integration ............................................................................................................... 3346
18.2.1 MMCHS Connectivity Attributes ............................................................................ 3347
18.2.2 MMCHS Clock and Reset Management .................................................................. 3348
18.2.3 MMCHS Pin List .............................................................................................. 3348
18.3 Functional Description ................................................................................................. 3350
18.3.1 MMC/SD/SDIO Functional Modes ......................................................................... 3350
18.3.2 Resets ......................................................................................................... 3357
18.3.3 Power Management .......................................................................................... 3358
18.3.4 Interrupt Requests ............................................................................................ 3361
18.3.5 DMA Modes ................................................................................................... 3363
18.3.6 Mode Selection ............................................................................................... 3366
18.3.7 Buffer Management .......................................................................................... 3366
18.3.8 Transfer Process ............................................................................................. 3369
18.3.9 Transfer or Command Status and Error Reporting ...................................................... 3370
18.3.10 Auto Command 12 Timings ................................................................................ 3375
18.3.11 Transfer Stop ................................................................................................ 3377
18.3.12 Output Signals Generation ................................................................................ 3378
18.3.13 Card Boot Mode Management ............................................................................ 3380
18.3.14 CE-ATA Command Completion Disable Management ................................................ 3382
18.3.15 Test Registers ............................................................................................... 3382
18.3.16 MMC/SD/SDIO Hardware Status Features .............................................................. 3383
18.4 Low-Level Programming Models ..................................................................................... 3384
18.4.1 Surrounding Modules Global Initialization ................................................................. 3384
18.4.2 MMC/SD/SDIO Controller Initialization Flow .............................................................. 3384
18.4.3 Operational Modes Configuration .......................................................................... 3387
18.5 Multimedia Card Registers ............................................................................................ 3389
18.5.1 MULTIMEDIA_CARD Registers ............................................................................ 3389
19 Universal Asynchronous Receiver/Transmitter (UART) ....................................................... 3446
19.1 Introduction .............................................................................................................. 3447
19.1.1 UART Mode Features ........................................................................................ 3447
19.1.2 IrDA Mode Features ......................................................................................... 3447
19.1.3 CIR Mode Features .......................................................................................... 3447
19.1.4 Unsupported UART Features ............................................................................... 3447
19.2 Integration ............................................................................................................... 3449
19.2.1 UART Connectivity Attributes ............................................................................... 3449
19.2.2 UART Clock and Reset Management ..................................................................... 3450
19.2.3 UART Pin List ................................................................................................. 3452
19.3 Functional Description ................................................................................................. 3453
19.3.1 Block Diagram ................................................................................................ 3453
19.3.2 Clock Configuration .......................................................................................... 3454
19.3.3 Software Reset ............................................................................................... 3454
19.3.4 Power Management .......................................................................................... 3454
19.3.5 Interrupt Requests ............................................................................................ 3456
19.3.6 FIFO Management ........................................................................................... 3459
19.3.7 Mode Selection ............................................................................................... 3467
19.3.8 Protocol Formatting .......................................................................................... 3473
19.4 UART/IrDA/CIR Basic Programming Model ......................................................................... 3496
19.4.1 UART Programming Model ................................................................................. 3496
19.4.2 IrDA Programming Model ................................................................................... 3502
19.5 UART Registers ........................................................................................................ 3505
19.5.1 UART Registers .............................................................................................. 3505
10 Contents SPRUH73H–October 2011–Revised April 2013
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