Texas Instruments bq77915EVM-014 User manual

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bq77915 3-5S Low Power Protector Evaluation Module
User's Guide
SLUUBU2B–March 2018–Revised August 2018
bq77915 3-5S Low Power Protector Evaluation Module
This evaluation module (EVM) is a complete evaluation system for the bq77915 3-5S low power protector
for lithium-ion cells. The EVM includes one bq77915 and FETs to control current in a configuration typical
for switching current in a lithium-ion battery pack. The circuit module includes one bq77915 integrated
circuit (IC), sense resistors, thermistor, two CSD18534Q5A FETs, and all other onboard components
necessary to switch charge and discharge current. The circuit module connects between a battery source
and a pack load. In addition to the current and voltage applied to the module, the user can remove
onboard jumpers to simulate overtemperature or undertemperature conditions to observe FET control
under different charge and discharge conditions. Balancing of unmatched cells can also be performed on
the module.
Contents
1 Features....................................................................................................................... 3
1.1 Kit Contents.......................................................................................................... 3
1.2 Ordering Information ............................................................................................... 3
1.3 Documentation ...................................................................................................... 3
1.4 bq77915 Circuit Module Performance Specification Summary............................................... 3
2 bq77915EVM Quick-Start Guide........................................................................................... 3
2.1 Before You Begin................................................................................................... 3
2.2 Items Needed for EVM Quick Start Evaluation ................................................................. 4
2.3 EVM Connections................................................................................................... 4
2.4 Quick-Start Sequence.............................................................................................. 5
3 Additional Evaluation Setups............................................................................................... 6
3.1 Operation With Charge and Discharge Currents ............................................................... 6
3.2 Reducing the Cell Count........................................................................................... 6
3.3 Connecting to Cells................................................................................................. 7
3.4 Stacking Modules................................................................................................... 8
3.5 Troubleshooting ................................................................................................... 10
3.6 Changing Configuration or Conditions.......................................................................... 10
4 bq77915EVM Optional Circuit Features................................................................................. 10
4.1 Alternate FETs..................................................................................................... 10
4.2 Single-Ended Filter Capacitors.................................................................................. 10
4.3 Other Uninstalled Components.................................................................................. 10
4.4 Cell Balance Indicators........................................................................................... 10
4.5 OCD Timing........................................................................................................ 10
5 Circuit Module Physical Layouts ......................................................................................... 11
5.1 Board Layout....................................................................................................... 11
5.2 Schematic .......................................................................................................... 15
6 Bill of Materials ............................................................................................................. 17
7 Related Documentation from Texas Instruments ...................................................................... 19
List of Figures
1 bq77915 Circuit Module Connection for Simple Demonstration....................................................... 4
2 Bipolar Operation ............................................................................................................ 6
3 Operation With Reduced Cell Count...................................................................................... 7
4 Connecting to Cells.......................................................................................................... 7
5 Stacking Circuit Modules ................................................................................................... 9

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6 Top Silk Screen............................................................................................................. 11
7 Top Assembly............................................................................................................... 12
8 Top Layer ................................................................................................................... 12
9 Internal Layer 1............................................................................................................. 13
10 Internal Layer 2............................................................................................................. 13
11 Bottom Layer................................................................................................................ 14
12 bq77915EVM Schematic.................................................................................................. 15
13 bq77915EVM Cell Balance Indicator Schematic....................................................................... 16
List of Tables
1 Performance Specification Summary ..................................................................................... 3
2 Module Modifications for Stacking......................................................................................... 8
3 bq77915EVM Bill of Materials ........................................................................................... 17

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(1) All trademarks are the property of their respective owners.
(1)
1 Features
The bq77915EVM has the following features:
• Complete evaluation system for the bq77915 3-5S low power protector IC
• Populated circuit module for quick setup
1.1 Kit Contents
The bq77915EVM contains the following:
• bq77915 circuit module
1.2 Ordering Information
The EVM orderable part number is bq77915EVM-014. For complete ordering information, see the product
page at www.ti.com.
1.3 Documentation
For more information on device hardware, refer to bq77915 3-5S Low Power Protector with Cell Balancing
and Hibernate Mode.
1.4 bq77915 Circuit Module Performance Specification Summary
This section summarizes the performance specifications of the bq77915EVM.
Table 1. Performance Specification Summary
Specification Minimum Typical Maximum Unit
Input voltage BATT+ to BATT– 3 18 22 V
Output voltage PACK+ to PACK- 0 18 22 V
Charge and discharge current 0 2.5 4 A
Cell Balancing Current 50 mA
Operating temperature 20 25 30 oC
2 bq77915EVM Quick-Start Guide
This section provides the step-by-step procedures required to use a new EVM and configure it for
operation in a laboratory environment.
2.1 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
bq77915 EVM. Observe all safety precautions.
CAUTION
The circuit module has signal traces and component leads on the bottom of the
board. This may result in exposed voltages, hot surfaces, or sharp edges. Do
not reach under the board during operation. Do not operate the EVM on a
conductive surface.

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CAUTION
The circuit module may be damaged by overtemperature. To avoid damage,
monitor the temperature during evaluation and provide cooling, as needed, for
your system environment.
CAUTION
Some power supplies can be damaged by application of external voltages. If
using more than one power supply, check your equipment requirements and
use blocking diodes or other isolation techniques, as needed, to prevent
damage to your equipment.
CAUTION
The circuit module is not a finished product or electrical appliance. It must be
used by qualified personnel with additional equipment for evaluation only. Do
not leave EVM powered when unattended.
2.2 Items Needed for EVM Quick Start Evaluation
• A bq77915 circuit module
• An adjustable DC power supply that can provide 10 V to 22 V and 1 A minimum (a voltage range,
bipolar operation, and constant current – constant voltage capability is desirable)
• Five resistors for cell voltage simulation such as 200 Ω, 1% 1/4-W or other suitable value
• A load such as a 5-kΩ, 1/4-W or other suitable resistor
• A DC meter or measurement instrument
• Some suitable cables for connection
2.3 EVM Connections
This section covers the hardware connections for the EVM (see Figure 1).
Figure 1. bq77915 Circuit Module Connection for Simple Demonstration

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• Supply terminal block (J2)
These are the supply terminals for the board. BATT+ or CELL5 is the positive terminal of the power
supply and BATT– is the negative terminal of the power supply. The inputs CELL1 through CELL4 are
divided between the BATT+ and BATT– voltages. When using a power supply for evaluation, be sure
the power supply can accept or is protected from any reverse current such as with a blocking diode if
another supply is used in the system.
• Pack terminals (J9)
PACK+ and PACK– terminals are for attachment for the load or charger. If using a power supply to
simulate a charger, be sure it can accept or is protected from any reverse current.
• Shunts on J3
Shunts should be placed shorting J3 pins 1 to 2 and pins 3 to 4. The shunt on pins 1 and 2 connects
the IC VTB pin to the temperature measurement path. A hot temperature is simulated when the shunt
on pins 1 to 2 is removed. The shunt on pins 3 and 4 connects the IC TS pin to the thermistor. A cold
temperature is simulated when the shunt is removed.
• Shunt on J4
A shunt should be placed shorting J4 pins 2 to 3. The shunt pulls up the IC PRES pin to wake the IC.
Remove the shunt to allow the part to hibernate.
• Shunt on J5
A shunt should be placed shorting J5 pins 1 to 2. The shunt pulls down the IC CBI pin to enable cell
balancing. Remove the shunt to disable cell balancing.
• Shunt on J6
A shunt should be placed shorting J6 pins 13 to 14. The 100-kΩOCDP resistor connected by the
shunt selects the EEPROM defined OCD delays. See bq77915 3-5S Low Power Protector with Cell
Balancing and Hibernate Mode for a description of OCDP options.
2.4 Quick-Start Sequence
These steps describe a simple demonstration or check of the operation of the bq77915EVM in a 5S
configuration with a typical 18-V stack voltage.
1. Connect five 200-Ωresistors between the cell terminals of J3.
2. Confirm that shunts are in place on J3 shorting pins 1 to 2 and 3 to 4.
3. Confirm a shunt is in place on the J4 pins 2 to 3 to enable the IC.
4. Confirm a shunt is in place on the J5 pins 1 to 2 to enable balancing.
5. Confirm a shunt is in place on the J6 pins 13 to 14 to select the EEPROM-defined OCD delays.
6. Connect an 18-V adjustable DC power supply across the BATT+ and BATT– terminals of J3.
7. Enable the supply.
8. Measure the voltage on the pack terminals. Observe that this is the same voltage as the supply
because both charge and discharge FETs are on, approximately 18 V.
9. Connect a load such as a 5-kΩresistor across the PACK terminals
10. Adjust the supply voltage to 22 V to simulate an overvoltage condition. Observe that the voltage on
the PACK terminals is approximately 600 mV below the supply voltage because the charge FET is off.
11. Adjust the supply voltage to 18 V to cause recovery from the overvoltage condition. Observe that the
voltage on the PACK terminals is the supply voltage.
12. Remove the shunt on pins 1-2 of J4 to simulate a hot condition. Observe that the pack voltage drops
to approximately 0 V, and returns to normal when the shunt is re-installed.
13. Remove the shunt on pins 3-4 of J4 to simulate a cold condition. Observe that the pack voltage drops
to approximately 0 V and returns to normal when the shunt is re-installed.
14. Adjust the supply voltage to 12 V to simulate an undervoltage condition. Observe that the pack
voltage drops to approximately 0 V.
15. Adjust the supply voltage to 18 V to allow recovery from the undervoltage condition. Observe that the
pack voltage remains at approximately 0 V with the load resistor in place.

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(2 quadrant)
+ -
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supply
(2 quadrant)
+ -
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16. Remove the load resistor on the PACK terminals. Observe that the pack voltage returns to the supply
voltage because undervoltage recovers on the installed part configuration with both voltage and load
removal.
17. Disable the power supply and disconnect, if complete.
3 Additional Evaluation Setups
CAUTION
The bq77915 EVM does not contain capacitors on the input or output current
paths to dampen transients. Be sure to use appropriate transient suppression
to avoid damage to the board from cable or equipment transient responses
during evaluation.
3.1 Operation With Charge and Discharge Currents
If bipolar power supplies are available, current control can be demonstrated through the board in both
directions, see Figure 2. A battery voltage in range must be applied to the BATT side of the EVM for
operation. The instrument on the PACK side can be used as a load if it is set to a lower voltage than the
battery side or as a charger if set to a higher voltage. Additional equipment can be used to adjust the
voltage across the individual input resistors to simulate different cell voltages.
Figure 2. Bipolar Operation
Operation can also be demonstrated with conventional supplies and loads. Connect and operate the
equipment within its performance limits.
3.2 Reducing the Cell Count
The bq77915 EVM may be modified to provide monitoring of three or four cells. Figure 3 shows a concept
of simple three-cell evaluation. Cells are connected from the bottom up with unused top-cell inputs
connected to the top cell at J2. While this is not the direct IC pin connection shown in the data sheet, it will
work for general evaluation. The CCFG pin must also be connected to AVDD or GND to select monitoring
of three or four cells. This can be done by adding a jumper at the J8 pattern between pins 1 and 2 or 2
and 3 as desired. If the board will be used for further evaluation, be sure to remove the jumper at J8 after
the reduced cell test.

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Add shunt
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CAUTION
With a jumper installed at the J8 pattern, the bq77915 will not evaluate the top
one or two cells depending on the jumper installation. Remove any jumper to
monitor all cell inputs.
Figure 3. Operation With Reduced Cell Count
3.3 Connecting to Cells
TI recommends operating the bq77915 EVM with power supplies to become familiar with the operation
and features of the module and bq77915 before connecting cells. The bq77915 EVM may be connected to
cells so that the cells can provide the power for the bq77915, a concept is shown in Figure 4. The cells
should be connected together before connecting to the board. The BATT- connection should be made
first, then other cell connections can be made in any sequence.
Figure 4. Connecting to Cells

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3.4 Stacking Modules
While the bq77915 EVM modules do not stack as delivered, they can be modified for a basic
demonstration of stacking by adding additional components. The resulting circuit is not ideal because the
ESD capacitors will remain across each module rather than across the pack terminals. The charge and
discharge FETs installed are 60-V rated and will normally accommodate connection of two EVMs.
Connection of more than two EVMs is not supported by the patterns on the board and is not
recommended. Before connecting the modules, the bottom and top modules must have component
additions and changes shown in Table 2 to enable the stacking inputs and support the UV load removal
recovery detection for the upper device. Next, connect the upper board J7 to the lower board J1. Also
connect the upper board J5 pins 1 and 3 to the lower board J4 pins 1 and 3, respectively. The top board
must also have a wire connecting the BATT- pin on J2 to the PACK- pin on J9. A connection example of
the two modules is shown in Figure 5.
Table 2. Module Modifications for Stacking
Module Reference Designator Action Function
Bottom
R2 Install 10-MΩresistor
Stacking interface
R3 Install 10-MΩresistor
R7 Remove
R8 Remove
R12 Install 10-kΩresistor
J4 Remove shunt
R32 Install 470-kΩresistor UV load detect recovery
D3 Install BAS16J switching diode
Top R18 Install 10-kΩresistor Stacking interfaceJ5 Remove shunt
J6 Move shunt to pins 15 and 16

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supply
RLOAD
+ -
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200
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Modify
components
Move shunt
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Figure 5. Stacking Circuit Modules
CAUTION
The bottom bq77915 module will not receive fault conditions from the top
module unless properly modified and connected. Confirm operation of your
modified evaluation setup.
Once modified, the bottom module will not enable FETs when disconnected from the top module.
The stacked modules hibernate when the shunt is removed from the top module J4. Installing the shunt on
the top module J4 pins 2 to 3 exits hibernate mode. Cell balancing for the stacked modules is enabled by
installing a shunt on the bottom module J5 pins 1 to 2, removing the shunt disables cell balancing. The
shunt on the top module J6 should be moved to pins 15 and 16 to select the 10-MΩOCDP resistance,
see the data sheet.

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3.5 Troubleshooting
If the bq77915 does not appear to be operating, check the VDD voltage at TP1 as this should be the
same as the BATT+ voltage. Check that the shunt is installed at J4 pins 2 to 3 to exit hibernate mode.
Check the AVDD voltage at J8 pin 3, this should be approximately 2.5 V. Check that the shunts are
installed on J3 shorting pins 1 to 2 and pins 3 to 4. Check that the cell input voltages are within the
operating range of the part. If a fault has been induced, check that the recovery condition has been met.
The configuration of the supplied IC requires load removal for recovery from undervoltage; therefore,
remove any load from the PACK terminals or supply a charge voltage to recover from UV after the cell
voltages have returned to normal. The Section 2.4 section is a good procedure to check the basic
operation of the board. If the board has been used for stacking evaluation be sure the R7 and R8 resistors
have been replaced.
3.6 Changing Configuration or Conditions
If the board is modified to change the IC or other components or is operated at an expanded temperature
range, be sure to check component temperatures and other operating characteristics to be sure the board
does not provide a hazard in evaluation. A sample IC device may allow more current flow with higher
surface temperatures. Alternate FETs may require a change to the gate resistor to provide an appropriate
switching time.
4 bq77915EVM Optional Circuit Features
This section contains information on other EVM features.
4.1 Alternate FETs
The EVM has TO-220 footprints for use as test points or power FETs as options for evaluation.
4.2 Single-Ended Filter Capacitors
C2, C4, C5, and C7 are patterns for single-ended filters on the battery input terminals, if desired. With the
internal cell balancing, differential capacitors may be preferred, they distribute voltages during cell
connection and avoid conduction of the internal balance FET body diodes. VC1 should use a single-ended
capacitor to avoid pushing VC0 below VSS during load transients.
4.3 Other Uninstalled Components
The bq77915 EVM contains patterns for the stacking interface. Refer to Section 5.2 and Section 3 for
additional information.
4.4 Cell Balance Indicators
The bq77915 EVM contains LED indicators with current-limit resistors in parallel with the input filter
resistors. These indicators are not typically part of a battery circuit but are provided for evaluation. The
indicators will glow dimly when balancing with a low-impedance source. When operated with a resistor cell
simulator, the indicators will not typically illuminate since the resistor voltage will drop when balancing
turns on. To see the indicator, enable balancing with the J5 shunt, apply a supply voltage across the cell
and raise its voltage above the other cells and the balancing or OV threshold. Do not increase the cell
voltage significantly beyond OV to make the indicator brighter since higher balancing current into the
bq77915 may exceed the absolute maximum rating.
4.5 OCD Timing
The EVM supports changing the overcurrent protection delay by moving the jumper on J6 to select
different resistor values for the OCDP pin. See bq77915 3-5S Low Power Protector with Cell Balancing
and Hibernate Mode for details and the EVM schematic (Figure 12) for supported resistors.

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5 Circuit Module Physical Layouts
This section contains the printed-circuit board (PCB) layout, assembly drawings, and schematic for the
bq77915 circuit module.
5.1 Board Layout
This section shows the PCB layers and assembly drawing for the bq77915 module (see Figure 6 through
Figure 11). The board is a single-sided assembly, no components are located on the bottom.
Figure 6. Top Silk Screen

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Figure 7. Top Assembly
Figure 8. Top Layer

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Figure 9. Internal Layer 1
Figure 10. Internal Layer 2

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Figure 11. Bottom Layer

GNDGND
VC1
VC2
VC3
VC4
VC5
1
2
3
4
5
6
J2
C5
C4
C3
C2
C1
3 - 22 V
4 A
Input
1.0k
R4
GND
1uF
C1
TP1
VC0
GND
C0
TP5
GND
TP6
GND
BATT-
0.015
R33
26V
D1
GND
NT1
C5
TP3
TP2
100
R26
100
R27
0.1uF
C14
0.1uF
C15
0.1uF
C13
GND GND
GND
1
2
3
J8
GND
GND
1
2
J9
60V
4
7,8
1,2,3
5,6,
Q1 60V
4
7,8 1,2,3
5,6,
Q2
60V
1
3 2
Q3
DNP
60V
1
32
Q4
DNP
PACK-
0.1uF
C18
0.1uF
C19
5.1k
R23
10M
R29
3.0M
R30
470k
R31
0.1uF
C17
0.1uF
C16
C5
12
E1
0 - 22 V
4 A
Output
TP7
TP4
PACK+
CD
470k
R32
DNP
16V
D4
100V
D3
DNP
10M
R3
DNP
10M
R2
DNP
0
R8
0
R7
GND GND
4
1
2
3
J1
DNP
GND
4
1
2
3
J7
DNP
LD
CHG
DSG
GND
10.0k
R6
GND
4
1
2
3
J3
10k
t°
RT1
CCFG
AVDD
LDU
PRES
CBO
LPWR
CBI
5.1k
R24
1.0M
R28
100V
D2
1uF
C3
1uF
C6
1uF
C8
1uF
C9
1uF
C10
1uF
C11
1uF
C12
10.0k
R1
10.0k
R18
DNP
10.0k
R12
DNP
1uF
C7
DNP
GND
1uF
C5
DNP
GND
1uF
C4
DNP
GND
1uF
C2
DNP
GND
43
R5
43
R9
43
R10
43
R11
43
R14
43
R16
BQ7791500PWR
DSG 12
CCFG 20
CHG 13
LD 14
TS 18
VTB 19
CTRC 23
AVDD
2
VDD
1
VC5
3
VC4
4
VC3
5
VC2
6
VC1
7
VSS 9
SRP
10
SRN
11 OCDP 17
LPWR
15
VC0
8
PRES 22
CBI 16
CBO 21
CTRD 24
U1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J6
OCDP
750k
R13
604k
R15
487k
R17
383k
R19
294k
R20
196k
R21
100k
R22
10.0M
R25
VDD
1
2
3
J5
1
2
3
J4
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5.2 Schematic
Figure 12 and Figure 13 show the bq77915EVM schematic.
Figure 12. bq77915EVM Schematic

Red
D5
1.00k
R34
Red
D6
1.00k
R35
Red
D7
1.00k
R36
Red
D8
1.00k
R37
Red
D9
1.00k
R38
C1
C2
C3
C4
C5
VC1
VC2
VC3
VC4
VC5
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Figure 13. bq77915EVM Cell Balance Indicator Schematic

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6 Bill of Materials
Table 3 lists the bq77915EVM bill of materials (BOM).
(1) Unless otherwise noted in the Alternate Part Number or Alternate Manufacturer columns, all parts may be substituted with equivalents.
Table 3. bq77915EVM Bill of Materials(1)
Designator QTY Value Description Package Reference Part Number Manufacturer Alternate Part
Number Alternate Manufacturer
!PCB1 1 Printed Circuit Board BMS014 Any
C1 1 1µF CAP, CERM, 1µF, 50 V, ±10%, X7R, 0805 0805 GRM21BR71H105KA12L Murata
C3, C6, C8, C9,
C10, C11, C12 7 1µF CAP, CERM, 1µF, 10V, ±10%, X7R, 0805 0805 GRM21BR71A105KA01L Murata
C13, C14, C15,
C16, C17, C18,
C19
7 0.1µF CAP, CERM, 0.1µF, 50V, ±10%, X7R, 0603 0603 06035C104KAT2A AVX
D1 1 26V Diode, TVS, 26V, 42.1 Vc, SMB SMB SMBJ26A-13-F Diodes Inc.
D2 1 100V Diode, Switching, 100V, 0.25A, SOD-323F SOD-323F BAS16J,135 Nexperia USA
Inc.
D4 1 16V Diode, Zener, 16V, 200mW, SOD-323 SOD-323 MMXZ5246B-TP Micro
Commercial Co.
D5, D6, D7, D8,
D9 5 Red LED, Red, SMD 3x1.5mm BR1101W-TR Stanley electric Co.
H9, H10, H11,
H12 4 Bumpon, Hemisphere, 0.44 X 0.20, Clear Transparent Bumpon SJ-5303 (CLEAR) 3M
J2 1 Terminal Block, 3.5mm Pitch, 6x1, TH 20.5x8.2x6.5mm ED555/6DS On-Shore
Technology
J3 1 Header, 100mil, 4x1, Tin, TH Header, 4x1, 100mil, TH PEC04SAAN Sullins Connector
Solutions
J4, J5, J8 3 Header, 100mil, 3x1, Tin, TH Header, 3 PIN, 100mil,
Tin PEC03SAAN Sullins Connector Solutions
J6 1 Header, 2.54 mm, 8x2, Tin, Vertical, TH Header, 2.54 mm, 8x2,
TH PEC08DAAN Sullins Connector Solutions
J9 1 Terminal Block, 3.5mm Pitch, 2x1, TH 7.0x8.2x6.5mm ED555/2DS On-Shore
Technology
Q1, Q2 2 60V MOSFET, N-CH, 60V, 50A, DQJ0008A (VSONP-8) DQJ0008A CSD18534Q5A Texas
Instruments
R1, R6 2 10.0k RES, 10.0k, 1%, 0.1W, 0603 0603 CRCW060310K0FKEA Vishay-Dale
R4 1 1.0k RES, 1.0k, 5%, 0.125W, 0805 0805 CRCW08051K00JNEA Vishay-Dale
R5, R9, R10,
R11, R14, R16 6 43 RES, 43, 5%, 0.25W, 1206 1206 CRCW120643R0JNEA Vishay-Dale
R8, R9 2 0 RES, 0, 5%, 0.1W, 0603 0603 CRCW06030000Z0EA Vishay-Dale
R13 1 750k RES, 750k, 1%, 0.1W, 0603 0603 CRCW0603750KFKEA Vishay-Dale
R15 1 604k RES, 604k, 1%, 0.1W, 0603 0603 CRCW0603604KFKEA Vishay-Dale
R17 1 487k RES, 487k, 1%, 0.1W, 0603 0603 CRCW0603487KFKEA Vishay-Dale
R19 1 383k RES, 383k, 1%, 0.1W, 0603 0603 CRCW0603383KFKEA Vishay-Dale

Bill of Materials www.ti.com
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bq77915 3-5S Low Power Protector Evaluation Module
Table 3. bq77915EVM Bill of Materials(1) (continued)
Designator QTY Value Description Package Reference Part Number Manufacturer Alternate Part
Number Alternate Manufacturer
R20 1 294k RES, 294k, 1%, 0.1W, 0603 0603 CRCW0603294KFKEA Vishay-Dale
R21 1 196k RES, 196k, 1%, 0.1W, 0603 0603 CRCW0603196KFKEA Vishay-Dale
R22 1 100k RES, 100k, 1%, 0.1W, 0603 0603 CRCW0603100KFKEA Vishay-Dale
R23, R24 2 5.1k RES, 5.1k, 5%, 0.1W, 0603 0603 CRCW06035K10JNEA Vishay-Dale
R25 1 10.0Meg RES, 10.0M, 1%, 0.1W, 0603 0603 CRCW060310M0FKEA Vishay-Dale
R26, R27 2 100 RES, 100, 5%, 0.1W, 0603 0603 CRCW0603100RJNEA Vishay-Dale
R28 1 1.0Meg RES, 1.0M, 5%, 0.1W, 0603 0603 CRCW06031M00JNEA Vishay-Dale
R29 1 10Meg RES, 10M, 5%, 0.1W, 0603 0603 CRCW060310M0JNEA Vishay-Dale
R30 1 3.0Meg RES, 3.0M, 5%, 0.1W, 0603 0603 CRCW06033M00JNEA Vishay-Dale
R31 1 470k RES, 470k, 5%, 0.1W, 0603 0603 CRCW0603470KJNEA Vishay-Dale
R33 1 0.015 RES, 0.015, 1%, 1W, 2010 2010 CSRN2010FK15L0 Stackpole
Electronics Inc
R34, R35, R36,
R37, R38 5 1.00k RES, 1.00k, 1%, 0.1W, 0603 0603 CRCW06031K00FKEA
RT1 1 10.0kΩThermistor NTC, 10.0kΩ, 1%, Disc, 5 × 8.4 mm Disc, 5 × 8.4 mm 103AT-2 SEMITEC
Corporation
TP1 1 Test Point, Miniature, White, TH White Miniature Testpoint 5002 Keystone
TP2, TP3, TP4,
TP7 4 Test Point, Multipurpose, White, TH White Multipurpose Testpoint 5012 Keystone
TP5, TP6 2 Test Point, Multipurpose, Black, TH Black Multipurpose
Testpoint 5011 Keystone
U1 1 3-5S Ultra Low-Power Battery Protector with Smart
Cell Balancing, PW0024A PW0020A bq7791500PWR Texas Instruments bq7791500PW Texas Instruments
SH-J3-1, SH-J3-
3, SH-J4-2, SH-
J5-1, SH-J6-13
5 1x2 Shunt, 100mil, Gold plated, Black Shunt SNT-100-BK-G Samtec 969102-0000-DA 3M
C2, C4, C5, C7 0 1µF CAP, CERM, 1µF, 50V, ±10%, X7R, 0805 0805 GRM21BR71H105KA12L Murata
D3 0 100V Diode, Switching, 100V, 0.25A, SOD-323F SOD-323F BAS16J,135 Nexperia
FID1, FID2, FID3 0 Fiducial mark. There is nothing to buy or mount. N/A N/A N/A
J1, J7 0 Header, 100mil, 4x1, Tin, TH Header, 4x1, 100mil, TH PEC04SAAN Sullins Connector
Solutions
Q3, Q4 0 60V MOSFET, N-CH, 60V, 100A, KCS0003B (TO-220-3) KCS0003B CSD18534KCS Texas
Instruments
R2, R3 0 10Meg RES, 10M, 5%, 0.1W, 0603 0603 CRCW060310M0JNEA Vishay-Dale
R12, R18 0 10.0k RES, 10.0k, 1%, 0.1W, 0603 0603 CRCW060310K0FKEA Vishay-Dale
R32 0 470k RES, 470k, 5%, 0.1W, 0603 0603 CRCW0603470KJNEA Vishay-Dale

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SLUUBU2B–March 2018–Revised August 2018
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bq77915 3-5S Low Power Protector Evaluation Module
7 Related Documentation from Texas Instruments
• Texas Instruments, bq77915 3-5S Low Power Protector with Cell Balancing and Hibernate Mode Data
Sheet

Revision History www.ti.com
20 SLUUBU2B–March 2018–Revised August 2018
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Revision History
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (August 2018) to B Revision ................................................................................................ Page
• Added sentence to first paragraph in Section 3.4..................................................................................... 8
• Changed J2 to J4 in Table 2............................................................................................................. 8
• Changed J2 to J4 in last paragraph in Section 3.4 ................................................................................... 9
Changes from Original (March 2018) to A Revision ....................................................................................................... Page
• Updated Cell Balance Indicators section ............................................................................................ 10
• Updated Top Silkscreen image ........................................................................................................ 11