Texas Instruments TAS2559 User manual

1
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TAS2559 Evaluation Module
User's Guide
SLOU462A–November 2016–Revised March 2017
TAS2559 Evaluation Module
This user’s guide describes the characteristics, operation, and use of the TAS2559 Evaluation Module
(EVM). A complete schematic diagram, printed-circuit board layouts, and bill of materials are included in
this document.
NOTE: Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or
technical data (as defined by the U.S., EU, and other Export Administration Regulations)
including software, or any controlled product restricted by other applicable national
regulations, received from Disclosing party under this Agreement, or any direct product of
such technology, to any destination to which such export or re-export is restricted or
prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent
required by those laws. This provision shall survive termination or expiration of this
Agreement. According to our best knowledge of the state and end-use of this product or
technology, and in compliance with the export control regulations of dual-use goods in force
in the origin and exporting countries, this technology is classified as follows:
• US ECCN: 3E991
• EU ECCN: EAR99
This technology may require export or re-export license for shipping it in compliance with the
applicable regulations of certain countries.

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TAS2559 Evaluation Module
Contents
1 Description.................................................................................................................... 3
2 Specifications................................................................................................................. 3
3 Software....................................................................................................................... 3
4 Mono Setup................................................................................................................... 4
5 Stereo Setup ................................................................................................................. 7
6 Digital Audio Interfaces ..................................................................................................... 8
7 Hardware Documentation ................................................................................................. 11
List of Figures
1 TAS2559 EVM Mono Setup................................................................................................ 4
2 Setting Default Playback Device........................................................................................... 5
3 3-Pin Jumper................................................................................................................. 6
4 TAS2559EVM Stereo Setup ............................................................................................... 7
5 USB Audio Selection........................................................................................................ 9
6 Direct (AP/PSIA) Audio Selection........................................................................................ 10
7 TAS2559EVM USB Block................................................................................................. 11
8 TAS2559EVM Input Muxes and Translators ........................................................................... 12
9 TAS2559EVM Output Muxes and Translators ......................................................................... 13
10 TAS2559EVM Channel 1 Schematic.................................................................................... 14
11 TAS2559EVM Channel 2 (TAS2560) Schematic ...................................................................... 15
12 TAS2559EVM Power Supply............................................................................................. 16
13 Top Overlay................................................................................................................. 17
14 Top Solder Mask ........................................................................................................... 17
15 Top Layer ................................................................................................................... 18
16 Copper Layer 2............................................................................................................. 18
17 Copper Layer 3............................................................................................................. 19
18 Copper Layer 4............................................................................................................. 19
19 Copper Layer 5............................................................................................................. 20
20 Bottom Layer................................................................................................................ 20
21 Bottom Solder Mask ....................................................................................................... 21
22 Drill Drawing ................................................................................................................ 21
23 Board Dimensions.......................................................................................................... 22
List of Tables
1 EVM Specifications.......................................................................................................... 3
2 Default Jumper Settings .................................................................................................... 5
3 TAS2559EVM Bill of Materials ........................................................................................... 23
Trademarks
PurePath is a trademark of Texas Instruments.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.

www.ti.com Description
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TAS2559 Evaluation Module
1 Description
The TAS2559 device is an amplifier with integrated boost converter and programmable digital signal
processor. The output amplifier is a Class-D device that can be driven to higher output levels with the on-
chip Class-H boost. The on-chip voltage and current sense, together with TI’s Smart Amp algorithm,
protect the speaker against overheating and excessive excursion.
The TAS2559 EVM supports evaluation and development with the TAS2559 device through the following
interfaces:
• USB interface
– TAS2559 control through PurePath™ Console 3 (PPC3) GUI, USB-HID
– USB-class audio device, compatible with Microsoft®Windows®7+
• Digital audio AP and PSIA interface through 100-mil headers
• TI Learning Board 2 for speaker characterization
• SPI interface for TAS2559 control
• I2C interface for TAS2559 control
2 Specifications
Table 1. EVM Specifications
SOURCE REQUIREMENT
Amplifier Power Supply (VBAT) 2.9 to 5.5 V
Analog Supply (AVDD) 1.65 to 1.95 V
Digital Supply (DVDD) 1.65 to 1.95 V
EVM Power Supply 5.0 V
IO Power Supply (IOVDD) 1.62 to 3.6 V
Output Power 5.7 W
USB, USB Class-Audio Micro-USB B
3 Software
The TAS2559 EVM requires PurePath Console 3 with the TAS2559 plug-in.
NOTE: The TAS2559 device needs to be configured using this software. It will not function without
this configuration.
Please refer to the Smart Amp Tuning Guide which can be found in the project folder at
MySecureSoftware for detailed information about this software and how to configure the TAS2559 device
for Smart Amp Speaker Protection.

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4 Mono Setup
1. Install PurePath Console 3 with the TAS2559EVM plug-in.
2. Connect a speaker to J8 on the EVM.
3. Attach a 5.0 V/ 2.5 A power supply to connector J29 (inner = 5V, outer = GND).
4. Remove Jumpers J38, J47, J51, and J40.
5. Connect the EVM to a Windows 7+ PC with a micro-USB cable (J23). It will enumerate as a USB-
AudioEVM device (sound card).
Figure 1. TAS2559 EVM Mono Setup

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6. Verify that the EVM is the default playback device by opening the sound dialog from the Windows
Control Panel as shown in Figure 2.
Figure 2. Setting Default Playback Device
7. Check if the sampling rate matches the Windows setting by opening the advanced tab in the properties
menu. The EVM firmware enumerates as a USB-AudioEVM that supports 48 kHz sampling rate by
default. This setting must match the EVM at 2-channel, 16-bit, 48000 Hz (CD Quality).
Table 2. Default Jumper Settings
JUMPER SETTING DESCRIPTION CHANNEL
J2 Insert VBAT 5V
J3 Remove DOUT 1
J4 Insert DVDD 1.8V 1
J6 Insert AVDD 1.8V 1
J7 Insert IOVDD Setting from J30 1
J9 Remove SCL / SS 1
J10 Remove SDA / MOSI 1
J11 Insert Address Select1 1
J12 Insert Address Select0 1
J13 Insert SPI Select 1
J14 Remove IRQ 1
J15 Pin 1-2 SDIN = on-board 1
J16 Pin 1-2 WCLK = on-board 1
J17 Pin 1-2 BCLK = on-board 1
J18 Pin 1-2 MCLK = on-board 1
J19 Pin 1-2 SCL = on-board 1
J20 Pin 1-2 SDA = on-board 1
J22 Remove Reset 1

1 2 3
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Table 2. Default Jumper Settings (continued)
JUMPER SETTING DESCRIPTION CHANNEL
J24 Insert WP = 1, write protect EEPROM
J25 Remove DOUT 2
J26 Insert P1 = 0, select USB for on-board digital
audio
J27 Insert P0 = 0, select USB for on-board digital
audio
J30 Pin 1-2 IOVDD Select = 3.3 V 2
J32 Pin 1-2 SDIN = on-board 2
J33 Pin 1-2 WCLK = on-board 2
J34 Pin 1-2 BCLK = on-board 2
J35 Pin 1-2 MCLK = on-board 2
J36 Pin 1-2 SCL = on-board 2
J37 Pin 1-2 SDA = on-board 2
J38 Pin 2-3 ICC =1, inter-chip communication 2
J39 Insert AVDD 1.8V 2
J40 Pin 2-3 ICC =1, inter-chip communication 2
J41 Insert IOVDD 2
J42 Remove Reset 2
J43 Remove SCL = on-board
J45 Remove SDA = on-board
J46 Remove Address Select0 2
J47 Pin 2-3 ICC =1, inter-chip communication 2
J48 Remove PDM CLK 2
J49 Remove IRQ 2
J51 Pin 2-3 ICC =1, inter-chip communication 2
J52 Pin 1-2 Address Select1 2
Figure 3. 3-Pin Jumper
Please refer to Figure 5 for default jumper settings.

www.ti.com Stereo Setup
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5 Stereo Setup
1. Install PurePath Console 3 with the TAS2559EVM plug-in.
2. Connect speakers to both J44 and J8 on the EVM.
3. Attach a 5.0 V/ 5.0 A power supply to connector J29 (inner = 5V, outer = GND).
4. Connect the EVM to a Windows 7+ PC with a micro-USB cable (J23). It will enumerate as a USB-
AudioEVM device (sound card).
Figure 4. TAS2559EVM Stereo Setup
5. Proceed with characterization per the PPC3 User’s guide.
6. Change to channel B in the device control pane and set to Right Channel.
7. Play the test tone as shown in Figure 2.

Digital Audio Interfaces www.ti.com
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6 Digital Audio Interfaces
The various digital audio interfaces on the TAS2559EVM can be selected through hardware settings and
software settings. Several headers close to the TAS2559 device allow access to the following digital audio
signals:
• J3: Data Out (DOUT) from the TAS2559 (For example, current and voltage sense data.)
• J25: Data out (DOUT2) from the TAS2560
• J15: Data In (DIN) to the TAS2559
• J16: Word Clock or Frame Sync (WCLK)
• J17: Bit Clock (BCLK)
• J18: Master Clock (MCLK) (This is optional if TAS2559 PLL is not used.)
• J48: PDM Clock (PDMCLK) – optional input source for TAS2560
• J32: Data in (DIN2) to the TAS2650 – can be used for PDM input if desired
J3 has two pins:
• Digital data (for example, I and V sense data) from the TAS2559 device
• Ground
J15, J16, J17, and J18 have three pins:
• Digital audio signals from the EVM
• Digital audio signals to the TAS2559
• Ground
A jumper inserted in position 1-2 connects the TAS2559 to the digital audio signals from the board (for
example, USB or Learning Board 2). Replacing the jumper with a connector from an external source
connects the TAS2559 to the external source (for example, AP or PSIA).
The selection between the two on-board digital audio sources (USB or Learning Board 2) is controlled by:
(a) Hardware: J26,J27
• J26 = inserted, J27 = inserted; Selects USB
• J26 = inserted, J27 = removed; Selects Learning Board 2
(b) Software: The PPC3 GUI controls the digital audio routing during speaker characterization. This has
priority over the hardware settings from point a.
The secondary digital audio interface from the TAS2559 device is directly available through J5.

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6.1 Digital Audio Interface Selection
6.1.1 USB
The TAS2559EVM contains a microcontroller (TAS1020B) that acts as a USB HID and USB-class audio
interface. To select USB, insert both J26 and J27 and insert J15, J16, J17, and J18 in the 1-2 position.
This is shown in Figure 5.
Figure 5. USB Audio Selection

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6.1.2 Direct (AP/PSIA)
Remove the jumpers from J15, J16, J17 and J18 for Channel 1 (or J32, J33, J34, and J35 for Channel 2)
and connect the external digital audio source (for example AP or PSIA) to pin 2 of each head. Pin 3
provides a convenient ground connection. This is shown in Figure 6.
Figure 6. Direct (AP/PSIA) Audio Selection

+3.3V
10.0k
R17
10.0k
R18
27.4
R27
27.4
R26
1.50k
R25
47pF
C46
47pF
C45
Q1
15.0k
R20
BlueD1
USB LOCK 360
R28
3.09k R23
100pF
C47
1000pF C48
GND GND GND
GND
+3.3V
GND
GND
+3.3V
+3.3V
+3.3V
+3.3V +3.3V
100k
R29
GND
S1
+3.3V
USB RESET
MRESET
+3.3V
+5V-USB
PUR
DP
DM
0.1µF
16V
C35
0.1µF
16V
C36
0.1µF
16V
C37
0.1µF
16V
C38
0.1µF
16V
C39
0.1µF
16V
C49
0.1µF
16V
C43
MRESET
FB1
FB2
GND
GND
4.99k
R16
GND
+3.3V
TP12
SCL
TP13
SDA
SCL
SDA
I2C
2.00k
R9
DNP
DNP 2.00k
R10
DNP
DNP
SCL-USB
SDA-USB
0.1µF
16V
C33
0.1µF
16V
C34
0.1µF
16V
C40
0.1µF
16V
C41
0.1µF
16V
C42
IOVDD
0.1µF
16V
C44
GND
IOVDD
MCLK-USB
I2S-USB
49.9R19
49.9
R21
49.9
R22
49.9
R24
SDIN-USB
10.0k
R15
J24
WP
NC
1
NC
2
A2
3
VSS
4SDA 5
SCL 6
WP 7
VCC 8
U2
24LC256-I/MS
VBUS 1
D- 2
D+ 3
ID 4
GND 5
6
7
8
9
J23
USB-IN
6MHz
VCC 4 E/D
1
GND
2OUT 3
Y1
SDA_B
1
GND
2VCCA 3
SDA_A 4
SCL_A 5
OE 6
VCCB 7
SCL_B
8
U3
TCA9406DCUR
GND
USB_I2CEN
FROM LB2 CONN
+3.3V
USB_I2CEN IOVDD
IOVDD IOVDD
SCL-USB
SDA-USB
I2C-USB
0
R41
MCLK-USB
1A
1
GND
2
2A
32Y 4
VCC 5
1Y 6
U15
SN74LVC2G34DRLR
GND
+3.3V
1A
1
GND
2
2A
32Y 4
VCC 5
1Y 6
U16
SN74LVC2G34DRLR
1A
1
GND
2
2A
32Y 4
VCC 5
1Y 6
U17
SN74LVC2G34DRLR
1A
1
GND
2
2A
32Y 4
VCC 5
1Y 6
U18
SN74LVC2G34DRLR
MCLKIN-LB2
BCLKIN-LB2
LRCLKIN-LB2
SDIN0-LB2
I2S
LEARNING BOARD2
LRCLK-USB
BCLK-USB
SDOUT-USB
SDOUT-USB
BCLK-USB
LRCLK-USB
0.1µF
16V
C59
0.1µF
16V
C56
0.1µF
16V
C57
0.1µF
16V
C58
MCLKIN-LB2
SDIN0-LB2
BCLKIN-LB2
LRCLKIN-LB2
0.1µF
16V
C60
DECOUPLING
SCL-USB
SDA-USB
SDIN-USB
CSYNC
CSCLK
CDATO
MCLK01
PLLFILO
1
AVDD
2
MCLKI
3
DVSS 4
PUR
5
DP
6DM
7
DVDD
8
MRESET
9
TEST
10
EXTEN
11
RSTO
12
P3-0 13
P3-1 14
P3-2/XINT 15
DVSS 16
P3-3 17
P3-4 18
P3-5 19
NC
20
DVDD
21
NC
22
P1-0 23
P1-1 24
P1-2 25
P1-3 26
P1-4 27
DVSS 28
P1-5 29
P1-6 30
P1-7 31
CSCHNE 32
DVDD
33
CSYNC 35
CDATI 36
CSCLK 37
CDATO 38
MCLKO1 39
MCLKO2 40
RESET
41 VREN
42
SDA 43
SCL 44
AVSS 45
XTALO
46
XTALI
47
PLLFILI
48
CRESET 34
U4
TAS1020BPFBR
GND
GND
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TAS2559 Evaluation Module
7 Hardware Documentation
7.1 TAS2559EVM Schematics
Figure 7 through Figure 12 show the schematics for the TAS2559 EVM.
Figure 7. TAS2559EVM USB Block

GND
+5.0V
SCL-USB
SDA-USB
GND
GND
GND
IOVDD
10.0k
R38
0R33
0
R32
0R31
0
R30
MCLK
SCLK
LRCLK
SDIN
GND
MCLK
SDIN
SCLK
LRCLK
MCLK-USB
I2S-USB
SDOUT-USB
BCLK-USB
LRCLK-USB
MCLK-USB
SDOUT-USB
BCLK-USB
LRCLK-USB
WCLK-from-LB2
SDOUT3-from-LB2
BCLK-from-LB2
SDIN-USB
SDIN-USB
47k
R36
2.2k
R35
GND
47k
R34
2.2k
R37
GNDGND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
33 34
J28
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
GND
+3.3V
GND
1A 1
GND 2
2A 3 2Y
4
VCC
5
1Y
6
U10
SN74LVC2G34DRLR
GND
+3.3V
A1
B2
Y
3
GND 4
Y
5
A/B 6
G
7
VCC
8
U9
SN74LVC2G157DCTR
RESET
1
P0 2
P1 3
P2 4
P3 5
GND 6
P4 7
P5 8
P6 9
P7 10 INT
11
SCL
12
SDA
13
VCCP
14
VCCI
15
ADDR
16
U8
TCA6408ARSVR
GNDGND I2C
EXPANDER
DECOUPLING
0.1µF
C50
+3.3V
GND
0.1µF
C53
+3.3V
GND
0.1µF
C54
GND
0.1µF
C51
+3.3V
GND
0.1µF
C52
GND
IOVDD
DIR1
15
DIR2
16
A1
1
A2
2
A3
3
A4
4
DIR3
5
DIR4
6
OE
7GND 8
B4 9
B3 10
B2 11
B1 12
VCCB 13 VCCA
14
U6
SN74AVC4T774RSVR
10.0k
R39
I2S/MIX-MUX
WCLK-DUT
BCLK-DUT
MCLK-DUT
DOUT-MIXMUX
DIN-DUT
I2C-USB
USB_I2CEN
USB_I2CEN
DIR1
15
DIR2
16
A1
1
A2
2
A3
3
A4
4
DIR3
5
DIR4
6
OE
7GND 8
B4 9
B3 10
B2 11
B1 12
VCCB 13 VCCA
14
U11
SN74AVC4T774RSVR
GND GND
DIN1
BCLK1
WCLK1
IOVDD+3.3V
LRCLK-to-LB2
BCLK-to-LB2
LRCLK-to-LB2
BCLK-to-LB2
WCLK-from-LB2
BCLK-from-LB2
MCLK-from-LB2
SDOUT3-from-LB2
IOVDD
J26
P1
J27
P0
S1 2
1B1
6
1B2
51A 7
2B4
13 2B3
12
1B4
31B3
4
2B1
10
2B2
11 2A 9
GND
8
VCC 16
1OE 1
2OE 15
S0 14
EP
17
U5
SN74CB3Q3253RGYR
S1 2
1B1
6
1B2
51A 7
2B4
13 2B3
12
1B4
31B3
4
2B1
10
2B2
11 2A 9
GND
8
VCC 16
1OE 1
2OE 15
S0 14
EP
17
U7
SN74CB3Q3253RGYR
10.0k
R43
GND
0.1µF
C55
GND
IOVDD
1
2
3
4
5
U14 SN74LVC1G125DCKR
+3.3V
GND
49.9R45SDOUT3-from-LB2
10.0k
R44
+3.3V
MCLKIN-LB2
SDIN0-LB2
BCLKIN-LB2
LRCLKIN-LB2
LRCLK-to-LB2
BCLK-to-LB2
+3.3V
SCL-USB
SDA-USB
I2S
LEARNING
BOARD 2
MCLKIN-LB2
SDIN0-LB2
BCLKIN-LB2
LRCLKIN-LB2
MCLK-from-LB2
SDOUT1-from-LB2
SDIN2-to-LB2
SDOUT1-from-LB2
SDIN2-to-LB2
SDOUT1-from-LB2
49.9
R1 LRCLK-MM
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Figure 8. TAS2559EVM Input Muxes and Translators

GND
GND
GND
10k
R50
10k
R51
0.1µF
C61
0.1µF
C62
0.1µF
C63
0.1µF
C64
GND
0.1µF
C65
GND
GND
A
1
B
2
Y3
GND
4
Y5
A/B
6
G7
VCC 8
U19
SN74LVC2G157DCTR
A
1
B
2
Y3
GND
4
Y5
A/B
6
G7
VCC 8
U21
SN74LVC2G157DCTR
S1 2
1B1
6
1B2
51A 7
2B4
13 2B3
12
1B4
31B3
4
2B1
10
2B2
11 2A 9
GND
8
VCC 16
1OE 1
2OE 15
S0 14
EP
17
U20
SN74CB3Q3253RGYR
GND GND
GND
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
SDATA-MM1
SDATA-MM2
SCL-USB
SDA-USB
LRCLK-MM
SCL-USB
SDA-USB
I2C-USB
DOUT-MIXMUX
RESET
3
P0 4
P1 5
P2 6
P3 7
GND 8
P4 9
P5 10
P6 11
P7 12
IRQ
13
SCL
14
SDA
15
VCCP
16
VCC
1
A0
2
U22
XRA1206IG16-F
10k
R52
+3.3V
TO
SCL-USB
GND
SDATA-MM1
SDATA-MM2
DOUT-MIXMUX
DIR1 15
DIR2 16
A1 1
A2 2
A3 3
A4 4
DIR3 5
DIR4 6
OE 7 GND
8
B4
9B3
10 B2
11 B1
12
VCCB
13 VCCA 14
U24
SN74AVC4T774RSVR
GNDGND
IOVDD +3.3V
From LB2 LRCLK-MM
DOUT-DUT2
DOUT-DUT1
From DUTS LB2/USB
0.1µF
C88
GND
IOVDD
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TAS2559 Evaluation Module
Figure 9. TAS2559EVM Output Muxes and Translators

INM1
GND
BCLK2-1
WCLK2-1
DIN2-1
RESET1
10.0k
R6
IOVDD
GND
ADR1-1_MISO
ADR0-1_SCLK
SPI_SELECT1
IRQ_GPIO4-1
RESET1
SPI-SEL
ADR
IRQ
IOVDD
ADR1-1_MISO
ADR0-1_SCLK
SPI_SELECT1
IRQ_GPIO4-1
GND
MOSI
SS SCL1_SS
SDA1_MOSI
ASI2
ASI1
10.0k
R2
IOVDD
10.0k
R3
IOVDD
10.0k
R4
IOVDD
10.0k
R5
IOVDD
GND
DOUT2-1
1 2
3 4
5 6
7 8
J5
PSIA
1 2 3
J15
1 2 3
J16
1 2 3
J17
1 2 3
J18
1 2 3
J19
1 2 3
J20
ICC-GPI3
ICC-GPIO10
ICC-GPIO9
BCLK2-1
WCLK2-1
DIN2-1
DOUT2-1
GND
MCLK1
BCLK1
WCLK1
DIN1
DOUT-DUT1
SCL
SDA
I2C
I2S
TP6
GND
GND
TP7
GND
GND
LB2
CONN DIN1
BCLK1
WCLK1
J9
J10
J11
J12
J13
J14
SCL1_SS
SDA1_MOSI
J3
10.0k
R11
10.0k
R12
10.0k
R13
10.0k
R14
WCLK-DUT
BCLK-DUT
MCLK-DUT
DIN-DUT
J22
RESET1
0.1µF
C20
GND
DOUT-DUT1
MIX
MUX
VBAT1
0.1µF
C11
1µF
C12
10µF
C13
GND GND GND
+1.8V
J4
DVDD1
0.1µF
C16
1µF
C17
10µF
C15
DNP
DNP
GND GND GND
+1.8V
J6
AVDD1
DVDD1
AVDD1
1µF
C19
0.1µF
C18
GND GND
IOVDD
J7
IOVDD1
IOVDD1
DIN1
BCLK1
DOUT-DUT1
MCLK1
WCLK1
TP1
MCLK1
TP2
BCLK1
TP3
WCLK1
TP4
DIN1
TP5
DOUT1
TP10
NC1
TP11
NC2
0.1µFC1
0.1µFC2
INP1
TO
DUT2
DIN-DUT2
BCLK-DUT2
WCLK-DUT2
MCLK1
1 2 3
J51
WCLK2
1 2 3
J47
DOUT2
1 2 3
J40
BCLK2
1 2 3
J38
DIN2
DOUT-DUT2
PGND_B A1
PGND_B A2
VBAT
A3
ICC_GPIO9
A4
WCLK1_GPIO2 A5
DOUT1_GPIO3 A6
SW B1
SW B2
ICC_GPIO10
B3
ICC_GPI3
B4
DIN1_GPI1 B5
BCLK1_GPIO1 B6
VBOOST C1
VBOOST C2
INP
C3
DGND C4
DIN2_GPIO8
C5
DVDD
C6
SPK_M D1
VREG D2
INM
D3
IOGND D4
IRQ_GPIO4
D5
MCLK_GPI2 D6
PGND E1
VSENSE_P E2
AGND E3
SDA_MOSI
E4
WCLK2_GPIO6
E5
DOUT2_GPIO7
E6
SPK_P F1
VSENSE_M F2
SCL_SSZ
F3
AVDD
F4
ADR0_SCLK
F5
BCLK2_GPIO5
F6
NC2
G1 NC1
G2
ADR1_MISO
G3
SPI_SELECT
G4
RESET
G5
IOVDD
G6
U1
TAS2559YZR
OUT1+
OUT1-
ASI1
MCLK1
BCLK1
WCLK1
DIN1
DOUT-DUT1
GND GND
GND GND
GND
+5.0V
SPEAKER
OUT
GND
VBAT1
GND
DNP
VBOOST1
SPK1+
SPK1-
SW1
SW1
DIN1
BCLK1
DOUT-DUT1
MCLK1
WCLK1
1000pF
C21
DNP
DNP
GND
1.00k
R7
DNP
DNP
4700pF
C23
DNP
DNP
GND
TP8
OUT1- DNP
DNP GND
1000pF
C22
DNP
DNP
1.00k
R8
DNP
DNP
4700pF
C24
DNP
DNP
GND
TP9 OUT1+
DNP
DNP
1
2
J8
OUT1
0
R42
0
R46
0.01µF
C14
0.1µF
16V
C3
TP14 VBST1
22µF
16V
C4
2.2uH
L1
0.1µF
C9
1µF
C10
J2
VBAT1
22µF
16V
C5
22µF
16V
C8
ICC-GPI3
ICC-GPIO9
ICC-GPIO10
DIN2-1
TO
DUT2
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TAS2559 Evaluation Module
Figure 10. TAS2559EVM Channel 1 Schematic

0.1µF
C69
1µF
C70
2.2uH
L2
0.01µF
C76
1000pF
C82
DNP
DNP
GND
GND GND
GND GND
GND
0.1µF
C78
1µF
C79 10µF
C77
DNP
DNP
GNDGNDGND
GND
IOVDD
ADDR
IRQ
GND
0.1µF
16V
C71
1000pF
C83
DNP
DNP
SCL2
SDA2
+1.8V
TP15 VBST2
SPEAKER
OUT
22µF
16V
C72
1.00k
R53
DNP
DNP
4700pF
C85
DNP
DNP
GND
1.00k
R57
DNP
DNP
4700pF
C86
DNP
DNP
GND
TP25
OUT2+ DNP TP26 OUT2-
DNP
MCLK1-2
BCLK1-2
WCLK1-2
DIN1-2
DOUT-DUT2
GND
22µF
C68
1 2 3
J32
DIN2
1 2 3
J33
WCLK2
1 2 3
J34
BCLK2
1 2 3
J35
MCLK2
1 2 3
J36
SCL2
1 2 3
J37
SDA2
TP16
MCLK2
TP17
BCLK2
TP18
WCLK2
TP19
DIN2
TP20
DOUT2
GND
MCLK1-2
BCLK1-2
WCLK1-2
DIN1-2
DOUT-DUT2
SCL
SDA
I2C
TP21
GND
GND
TP22
GND
GND
J39
AVDD2
J43
SCL2
J45
SDA2
J46
ADDR
J49
IRQ
J25
DOUT2
1
2
J44
OUT2
0
R54
0
R55
DNP DNP
22.1kR56
10.0k
R48
ADDR
IRQ
SCL2
SDA2
GND
RESET2
10.0k
R49
IOVDD
RESET2
J42
RESET2
0.1µF
C84
GND
DOUT-DUT2
MIX
MUX
SW2
VBAT2
TP27
VBAT2
MCLK
B1
BCLK
D2
WCLK
C1
DIN
D1
DOUT
E2
SCL
E3
SDA
F2
ADDR
A1
IRQ
A3
RESETZ
F1
NC2 B2
NC1 C2
SW E4
SW E5
VBOOST D4
VBOOST D5
VBAT
F3
AVDD
B3
IOVDD
A2
VREG C4
SPK_P C5
SPK_N A5
VSENSE_P A4
VSENSE_N B4
GND D3
GND C3
PGND_B F5
PGND_B F4
PGND B5
PDMCLK
E1
U23
TAS2560YFFR
VBOOST2
SPK2+
SPK2-
1µF
C81
0.1µF
C80
GND GND
IOVDD
J41
IOVDD2
IOVDD2
AVDD2
10.0k
R47
GND
TP23
PDMCLK
GND
J48
PDMCLK
10µF
C73
GND
OUT2+
OUT2-
FROM
TAS2559
DIN-DUT2
BCLK-DUT2
WCLK-DUT2
MCLK1
1
2
3
J52
ADDR SEL
GND
IOVDD
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TAS2559 Evaluation Module
Figure 11. TAS2559EVM Channel 2 (TAS2560) Schematic

C25
IN
1
2
EN
3NR 4
OUT 5
GND
U13
TPS73618DBVR
1µF
C7
0.1µF
C27
10µF
C6
1µF
C28
0.1µF
C30
0.01µF
C29
+3.3V
+1.8V
360
R40
GND
Green
D2
3.3V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+1.8V
+3.3V
IOVDD
1
3
2
J29
+5V
+5.0V
IN
1OUT 2
3
NR 4 EN
5
6
GND
U12
TPS73733DCQ
1µF
C26
GND
+5V
1 2 3
J30
IOVDD SEL
+3.3V
VBAT
VBAT1
0.1µF
10V
C32
GND
22µF
16V
C31
GND
GND
J31
VBAT1
VBAT2
0.1µF
10V
C67
GND
22µF
16V
C66
GND
GND
J21
VBAT2
VBAT1 VBAT2
Hi Current Shunt
J1
J50
+5V
GND
100µF
C74
GND
100µF
C87
GND
0.1µF
C89
GND
0.1µF
C75
GND
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TAS2559 Evaluation Module
Figure 12. TAS2559EVM Power Supply

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TAS2559 Evaluation Module
7.2 TAS2559 EVM Printed Circuit Board Layout
Figure 13. Top Overlay
Figure 14. Top Solder Mask

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TAS2559 Evaluation Module
Figure 15. Top Layer
Figure 16. Copper Layer 2

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TAS2559 Evaluation Module
Figure 17. Copper Layer 3
Figure 18. Copper Layer 4

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TAS2559 Evaluation Module
Figure 19. Copper Layer 5
Figure 20. Bottom Layer