Texas Instruments ADC12DJ3200CVAL User manual

User’s Guide
ADC12DJ3200EVMCVAL With Alpha Data Xilinx®
Kintex Ultrascale Space Development Kit
Jim Seton
ABSTRACT
This user's guide describes the functionality, hardware, operation, and software instructions to interface the
Texas Instruments ADC12DJ3200EVMCVAL with the Alpha Data ADA-SDEV-Kit1&2 development boards, which
contain a XQRKU060, a space grade Xilinx® Kintex® UltraScale™ field-programmable gate array (FPGA).
Table of Contents
1 Trademarks..............................................................................................................................................................................2
2 Introduction.............................................................................................................................................................................3
3 Functionality............................................................................................................................................................................3
4 Required Hardware.................................................................................................................................................................4
4.1 AlphaData ADA-SDEV-KIT1&2® ....................................................................................................................................... 4
4.2 TI ADC12DJ3200CVAL Evaluation Module....................................................................................................................... 4
4.3 Test Equipment.................................................................................................................................................................. 4
5 Required Software.................................................................................................................................................................. 5
5.1 HSDC Pro GUI................................................................................................................................................................... 5
5.2 ADC12DJ3200EVM-CVAL GUI..........................................................................................................................................6
6 Hardware Setup.......................................................................................................................................................................7
7 Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions.............................................................................................. 11
7.1 Configure the ADC EVM...................................................................................................................................................11
7.2 Manual SYNC Operation of the ADC12DJ3200EVM.......................................................................................................14
7.3 Viewing the Captured Data With High-Speed Data Converter Pro GUI...........................................................................22
8 Revision History................................................................................................................................................................... 25
List of Figures
Figure 5-1. Required File Structure............................................................................................................................................. 6
Figure 6-1. ADC12DJ3200EVM Board........................................................................................................................................ 7
Figure 6-2. Output Power Cable Connection...............................................................................................................................8
Figure 6-3. JTAG and USB Cable Connections...........................................................................................................................9
Figure 6-4. Alpha Data Board Power Switch............................................................................................................................... 9
Figure 6-5. Alpha Data Board With ADC12DJ3200 CVAL EVM Setup......................................................................................10
Figure 7-1. ADC12DJ3200EVM-CVAL GUI............................................................................................................................... 11
Figure 7-2. Low Level View Tab.................................................................................................................................................13
Figure 7-3. JESD204B Tab........................................................................................................................................................ 14
Figure 7-4. Setting ADC to use Software SYNC........................................................................................................................15
Figure 7-5. SYNC is now set low Inside the ADC......................................................................................................................16
Figure 7-6. Vivado Main Menu...................................................................................................................................................17
Figure 7-7. Open Target.............................................................................................................................................................18
Figure 7-8. Auto Connect...........................................................................................................................................................18
Figure 7-9. Select Device.......................................................................................................................................................... 19
Figure 7-10. Navigate to bit File Location.................................................................................................................................. 19
Figure 7-11. Program Device With the bit File........................................................................................................................... 20
Figure 7-12. Send SYNC High to ADC...................................................................................................................................... 21
Figure 7-13. HSDC PRO GUI.................................................................................................................................................... 22
Figure 7-14. Enter ADC Sampling Rate.....................................................................................................................................23
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Figure 7-15. ILA Analyser.......................................................................................................................................................... 24
Figure 7-16. HSDC Pro Captured Data..................................................................................................................................... 25
1 Trademarks
UltraScale™ is a trademark of Xilinx Incorporated.
Xilinx®, AlphaData ADA-SDEV-KIT1&2®, Vivado®, space grade Xilinx®, Kintex®, are registered trademarks of
Xilinx Incorporated.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
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2 Introduction
This design is developed for the Alpha Data System Development Kit (SDEV) to interface with the
ADC12DJ3200EVMCVAL using JMODE0. This design uses custom TI JESD204B IP, which implements both
JESD204B Base IP and JESD204B PHY IP to get JESD204B data from the ADC12DJ3200QML-SP device at
6.2 GSPS in single-device mode with 12.4 Gbps data lane rate. The reference design implements a transport
layer that collects 40 samples from the 8 lanes (as depicted in the JMODE0 table of the data sheet). The
samples are captured using the Xilinx Internal Logic Analyzer (ILA) tool and offloaded to a PC were the results
can be displayed using the TI High-Speed Data Converter Pro GUI.
3 Functionality
The AlphaData SDEV has a standard FMC+ connector that provides an interface between this board and the TI
JESD204B ADC12DJ3200CEVMCVAL. For communicating, the AlphaData SDEV uses JTAG to acquire and
receive data using a host PC. The industry-standard JTAG connector is used for configuring the FPGA using the
Vivado® Design Suite, a design tool by Xilinx. The firmware designed for this integration only supports JMODE0
at 6.2 GSPS single ADC. Future firmware will support all modes of this ADC.
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4 Required Hardware
4.1 AlphaData ADA-SDEV-KIT1&2®
The ADA-SDEV-KIT1&2 includes the ADM-SDEV-BASE/XCKU060-AD01360 Evaluation board which contains a
Xilinx XQRKU060-CNA1509 FPGA and the ADM-SDEV-CFG1-AD01361 USB interface board. For more
information regarding these boards, see the AlphaData website.
4.2 TI ADC12DJ3200CVAL Evaluation Module
The ADC12DJ3200EVMCVAL contains a space grade ADC12DJ3200QML-SP which can operate as either a 6.4
GSPS single 12-bit ADC or 3.2 GSPS dual 12-bit ADC. For more information regarding this board and ADC, see
the ADC12DJ3200EVMCVAL and ADC12DJ3200QML-SP product pages.
4.3 Test Equipment
• Low-noise RF signal generator. Recommendations:
– HP 8644B, Rohde & Schwarz SMA100A, or equivalent
• Bandpass filters for desired analog input. Recommendations:
– Trilithic 5VH-series Tunable BPF, K&L BT-series Tunable BPF, TTE KC6 or KC7-series Fixed BPF
• Signal path cables, SMA or BNC with BNC-SMA adapters
• 5 VDC 3-A power supply
• Corsair CX 650 power supply or equivalent
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5 Required Software
5.1 HSDC Pro GUI
Download the latest version of the HSDC Pro GUI (slwc107x.zip) to a local directory on a host PC. This is found
on the TI website by entering “HIGH SPEED DATA CONVERTER PRO GUI INSTALLER” in the search
parameter window at www.ti.com.
Unzipping the software package generates a folder called High Speed Data Converter Pro - Installer vx.xx.exe,
where x.xx is the version number. Run this program to start the installation.
Follow the on-screen instructions during installation.
Note
If an older version of the GUI has already been installed, make sure to uninstall it before loading a
newer version.
Click on the Install button. A new window opens. Click the Next button.
Accept the License Agreement. Click on Next to start the installation. After the installer has finished, click on the
Next button one last time.
The installation is now complete. The GUI executable and associated files will reside in the following directory.
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro
When new TI high-speed data converter EVMs or JESD204B interface modes become available that are not
currently supported by the latest release of HSDC Pro GUI, the HSDCProv_xpxx_Patch_setup executable,
available on the TI website under the High-Speed Data Converter Pro (HSDCP) Software product folder (http://
www.ti.com/tool/dataconverterpro-sw), will allow the user to add these to the GUI device list. After the patch has
been downloaded, follow the on-screen instructions to run the patch. The software displays the files that will be
added. After running the patch, open HSDC Pro and the new parts and modes will appear in the ADC and DAC
device drop-down selection box. The patch is always specific to a core GUI version and will not work for a GUI
version for which the patch was not explicitly created.
5.1.1 Xilinx® Vivado® Design Suite
The Vivado Design Suite by Xilinx, is required to load firmware to the FPGA and extract captured data from the
FPGA. See the Vivado Design Suite on Xilinx.com: https://www.xilinx.com/products/design-tools/vivado for more
details. The latest build that supports this integration is Vivado 2019.1.
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5.2 ADC12DJ3200EVM-CVAL GUI
This section provides the steps to download and begin using the ADC12DJ3200EVM-CVAL GUI.
1. Download the configuration GUI software from the EVM tool folder at ADC12DJ3200EVMCVAL.
2. Extract files from the .zip file
3. Run the executable file (setup.exe), and follow the instructions
4. Download the zipped file called “Alpha_Data_ADC12DJ3200_Demo” from this same location. This file
contains the required FPGA bit file and ADC GUI configuration files
5. Copy the files to the following new directory: "C:\ AlphaData_ADC12DJ3200_Demo". The directory structure
is critical and should look as illustrated in Figure 5-1.
Figure 5-1. Required File Structure
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6 Hardware Setup
This section provides directions and illustrations for setting up the hardware.
Figure 6-1. ADC12DJ3200EVM Board
By default, the FMC+ interface EEPROM on the ADC12DJ3200EVM is installed. Without this part, the
FMC3_VADJ voltage for the FPGA bank that drives the JESD204B SYNC will be set to 0 V, thus preventing the
SYNC signal from working. Using the ADC manual SYNC is a work around for this. U5 (24C65T-I/SM from
Microchip) is programmed with the provided .bin file called "FMC-ADC12DJ3200-CVAL.bin". This .bin file uses
address 0x53 which is required for the FMC+ slot on the Alpha Data board and will set the FMC3_VADJ to 1.8 V
after power up. With the EEPROM installed and programmed properly, after power up, test point TP3 on the
Alpha Data board should be at 1.8 V.
1. Connect the Alpha Data board with ADC12DJ3200 CVAL EVM. Use the FMC+ connector (J3) to connect the
ADC EVM.
2. Connect the output power cable from the CX 650 power supply to the Alpha Data board as Figure 6-2 shows:
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Figure 6-2. Output Power Cable Connection
3. Connect the JTAG cable between the PC and the JTAG port on the USB daughter board.
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4. Connect a USB cable between USB daughter board and the PC, see Figure 6-3.
USB Cable
JTAG Cable
Figure 6-3. JTAG and USB Cable Connections
5. Connect a USB cable between the ADC12DJ3200EVM (J31) and the PC. Connect the 5-V power supply that
can source a minimum of 3 A to J37 on the ADC12DJ3200EVM. TP12 (+5 V) and TP13 (GND) provide
another option for connecting to 5 V.
6. Connect a RF analog input source to J2 (VINA) of the ADC12DJ3200EVM. This guide uses a 70-MHz source
at 0 dBm from a TI TSW2700EVM.
7. Turn on the Alpha Data board. The power switch is near the power input cable.
Power Switch
Figure 6-4. Alpha Data Board Power Switch
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8. Figure 6-5 illustrates the setup.
Figure 6-5. Alpha Data Board With ADC12DJ3200 CVAL EVM Setup
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7 Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions
This chapter provides descriptions to program the ADC12DJ3200EVM, program the FPGA, setup the
ADC12DJ3200EVM for manual SYNC operation, capture the data with the FPGA, then view the captured data
with the HSDC Pro GUI.
7.1 Configure the ADC EVM
Use the following steps to configure the ADC EVM.
1. Open ADC12DJ3200EVM-CVAL GUI, choose Fclk = 3100MHz and select JMODE0 (equivalent to 6.2 GSPS
ADC sample rate and 12.4Gbps lane rate) in the EVM tab.
2. Click “Program Clocks and ADC”. On the ADC EVM, verify PLL1 LCKD LED turns on. This will indicate the
LMK04828 PLL1 is locked to the onboard 100-MHz VCXO.
3. Figure 7-1 illustrates the GUI.
Figure 7-1. ADC12DJ3200EVM-CVAL GUI
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4. By default, the FMC+ interface EEPROM on the ADC12DJ3200EVM is installed and programmed. Please go
to section 7.2.1. If using a board without this EEPROM, do the folowing steps:
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5. Go to the Low Level View tab.
6. In the Block box near the bottom of the page, click the drop-down arrow and select "ADC12DJxx00".
7. In the Address box enter "213”, in the Write Data box write “00”, then click the Write Register button.
8. Click the Read Register button to verify address 0x213 is now set to 0x00, as Figure 7-2 shows.
Figure 7-2. Low Level View Tab
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7.2 Manual SYNC Operation of the ADC12DJ3200EVM
This section provides details on the manual SYNC operation of the ADC12DJ3200EVM.
1. In the ADC12DJ3200EVM-CVAL GUI, click on the JESD204B tab as Figure 7-3 shows.
Figure 7-3. JESD204B Tab
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2. Implement the following steps (in order):
• Click on the "JESD Block Enable" to disable it (the green arrow should not be lit).
• Click on the SFORMAT button (to enable it). The FPGA firmware is using unsigned data and a K value of
4.
• Click the JSYNC_N Sync _Request button (it should be enabled or ‘lit’).
• Select “No SYNC Input Signal” from the SYNC Input Selection drop-down menu.
Figure 7-4. Setting ADC to use Software SYNC
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3. Click on the “JESD Block Enable" (to enable it). The GUI should look now as shown in Figure 7-5.
Figure 7-5. SYNC is now set low Inside the ADC
7.2.1 Programming the FPGA
This section provides instructions for programming the FPGA.
Launch Vivado 2019.1 and open the Hardware Manager.
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Figure 7-6. Vivado® Main Menu
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Select “Open Target”.
Figure 7-7. Open Target
Select “Auto Connect”
Figure 7-8. Auto Connect
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Right click on the xcku060… device and select “Program”.
Figure 7-9. Select Device
Navigate to C:\AlphaData_ADC12DJ3200_Demo and select the file “alpha-data-samples.bit”.
Figure 7-10. Navigate to bit File Location
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Click the Program button to complete the FPGA configuration with the bitfile.
Figure 7-11. Program Device With the bit File
In the Vivado TCL console, execute the following:
• cd c:/AlphaData_ADC12DJ3200_Demo
• source setup_new.txt
Switch back to the ADC12DJ3200EVM-CVAL GUI.
Navigate to the JESD204B tab and click on the JSYNC_N Sync Request button (it should now be off, as Figure
7-12 shows).
Switch back to the Vivado setup.
In the Vivado TCL console, execute the following:
cd c:/AlphaData_ADC12DJ3200_Demo
source capture_new.txt
The FPGA will now be doing continuous captures of the ADC data.
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