Texas Instruments MSP430G2533 User manual

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G –APRIL 2011–REVISED APRIL 2016
MSP430G2x33, MSP430G2x03 Mixed-Signal Microcontrollers
1 Device Overview
1
1.1 Features
1
• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode: 230 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
• Five Power-Saving Modes
• Ultra-Fast Wake up From Standby Mode in Less
Than 1 µs
• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle
Time
• Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With Four
Calibrated Frequencies
– Internal Very-Low-Power Low-Frequency (LF)
Oscillator
– 32-kHz Crystal
– External Digital Clock Source
• Two 16-Bit Timer_A With Three Capture/Compare
Registers
• Up to 24 Capacitive-Touch Enabled I/O Pins
• Universal Serial Communication Interface (USCI)
– Enhanced UART Supports Automatic Baud-
Rate Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
• 10-Bit 200-ksps Analog-to-Digital Converter (ADC)
With Internal Reference, Sample-and-Hold, and
Autoscan (See Table 3-1)
• Brownout Detector
• Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security Fuse
• On-Chip Emulation Logic With Spy-Bi-Wire
Interface
•Section 3 Summarizes Available Family Members
• Package Options
– TSSOP: 20 Pin, 28 Pin
– PDIP: 20 Pin
– QFN: 32 Pin
• For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
1.2 Applications
• Power Management
• Sensor Interface • Capacitive Touch
1.3 Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices that feature different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-
power modes to active mode in less than 1 µs.
The MSP430G2x03 and MSP430G2x33 devices are ultra-low-power mixed-signal microcontrollers with
built-in 16-bit timers, up to 24 I/O capacitive-touch enabled pins, and built-in communication capability
using the USCI. In addition, the MSP430G2x33 family members have a 10-bit ADC. See Section 3 for
configuration details.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital
values, and then process the data for display or for transmission to a host system.

Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
registers
16-MHz
CPU
including
16 registers
Emulation
2BP
JTAG
interface
SMCLK
ACLK
Port P1
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
P1.x
8
P2.x
Port P2
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
Spy-Bi-
Wire
Timer1_A3
3 CC
registers
XIN XOUT
Port P3
8 I/Os,
pullup or
pulldown
resistors
P3.x
8 8
RAM
512B
256B
Flash
16KB
8KB
4KB
2KB
USCI A0
UART,
LIN, IrDA,
SPI
USCI B0
SPI, I C
2
ADC
10 bit,
8 channel,
autoscan,
1-channel
DMA
MDB
MAB
Copyright © 2016, Texas Instruments Incorporated
2
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G –APRIL 2011–REVISED APRIL 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Device Overview Copyright © 2011–2016, Texas Instruments Incorporated
(1) For the most current part, package, and ordering information, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE(2)
MSP430G2533IRHB VQFN (32) 5 mm × 5 mm
MSP430G2533IPW TSSOP (28) 9.7 mm × 4.4 mm
TSSOP (20) 6.5 mm × 4.4 mm
MSP430G2533IN PDIP (20) 24.33 mm × 6.35 mm
1.4 Functional Block Diagrams
Figure 1-1 shows the functional block diagram of the MSP430G2x33 MCUs.
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Figure 1-1. Functional Block Diagram, MSP430G2x33

Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
registers
16-MHz
CPU
including
16 registers
Emulation
2BP
JTAG
interface
SMCLK
ACLK
Port P1
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
P1.x
8
P2.x
Port P2
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
Spy-Bi-
Wire
Timer1_A3
3 CC
registers
XIN XOUT
Port P3
8 I/Os,
pullup or
pulldown
resistors
P3.x
8 8
RAM
256B
Flash
8KB
4KB
2KB
USCI A0
UART,
LIN, IrDA,
SPI
USCI B0
SPI, I C
2
MDB
MAB
Copyright © 2016, Texas Instruments Incorporated
3
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com SLAS734G –APRIL 2011–REVISED APRIL 2016
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Device OverviewCopyright © 2011–2016, Texas Instruments Incorporated
Figure 1-2 shows the functional block diagram of the MSP430G2x03 MCUs.
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Figure 1-2. Functional Block Diagram, MSP430G2x03

4
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G –APRIL 2011–REVISED APRIL 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Table of Contents Copyright © 2011–2016, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagrams........................... 2
2 Revision History ......................................... 5
3 Device Comparison ..................................... 6
3.1 Related Products ..................................... 7
4 Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Signal Descriptions.................................. 10
5 Specifications........................................... 13
5.1 Absolute Maximum Ratings ........................ 13
5.2 ESD Ratings ........................................ 13
5.3 Recommended Operating Conditions............... 13
5.4 Active Mode Supply Current Into VCC Excluding
External Current..................................... 14
5.5 Typical Characteristics, Active Mode Supply Current
(Into VCC)............................................ 15
5.6 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 16
5.7 Typical Characteristics, Low-Power Mode Supply
Currents ............................................. 17
5.8 Thermal Resistance Characteristics ................ 18
5.9 Schmitt-Trigger Inputs, Ports Px .................... 19
5.10 Leakage Current, Ports Px.......................... 19
5.11 Outputs, Ports Px ................................... 19
5.12 Output Frequency, Ports Px ........................ 19
5.13 Typical Characteristics – Outputs................... 20
5.14 Pin-Oscillator Frequency – Ports Px................ 21
5.15 Typical Characteristics – Pin-Oscillator Frequency.21
5.16 POR, BOR .......................................... 22
5.17 Main DCO Characteristics .......................... 24
5.18 DCO Frequency..................................... 24
5.19 Calibrated DCO Frequencies, Tolerance ........... 25
5.20 Wake-up Times From Lower-Power Modes (LPM3,
LPM4) .............................................. 26
5.21 Typical Characteristics, DCO Clock Wake-up Time
From LPM3 or LPM4................................ 26
5.22 Crystal Oscillator, XT1, Low-Frequency Mode ..... 27
5.23 Internal Very-Low-Power Low-Frequency Oscillator
(VLO)................................................ 27
5.24 Timer_A ............................................. 27
5.25 USCI (UART Mode)................................. 28
5.26 USCI (SPI Master Mode)............................ 28
5.27 USCI (SPI Slave Mode)............................. 29
5.28 USCI (I2C Mode) .................................... 30
5.29 10-Bit ADC, Power Supply and Input Range
Conditions (MSP430G2x33 Only)................... 31
5.30 10-Bit ADC, Built-In Voltage Reference
(MSP430G2x33 Only)............................... 32
5.31 10-Bit ADC, External Reference (MSP430G2x33
Only)................................................. 33
5.32 10-Bit ADC, Timing Parameters (MSP430G2x33
Only)................................................. 33
5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33
Only)................................................. 33
5.34 10-Bit ADC, Temperature Sensor and Built-In VMID
(MSP430G2x33 Only)............................... 34
5.35 Flash Memory....................................... 34
5.36 RAM ................................................. 35
5.37 JTAG and Spy-Bi-Wire Interface.................... 35
5.38 JTAG Fuse.......................................... 35
6 Detailed Description ................................... 36
6.1 CPU ................................................. 36
6.2 Instruction Set....................................... 37
6.3 Operating Modes.................................... 38
6.4 Interrupt Vector Addresses.......................... 39
6.5 Special Function Registers (SFRs) ................. 40
6.6 Memory Organization ............................... 41
6.7 Bootloader (BSL).................................... 41
6.8 Flash Memory....................................... 42
6.9 Peripherals .......................................... 42
6.10 I/O Port Diagrams ................................... 48
7 Device and Documentation Support ............... 64
7.1 Getting Started and Next Steps..................... 64
7.2 Device Nomenclature ............................... 64
7.3 Tools and Software ................................. 66
7.4 Documentation Support............................. 68
7.5 Related Links........................................ 70
7.6 Community Resources.............................. 71
7.7 Trademarks.......................................... 71
7.8 Electrostatic Discharge Caution..................... 71
7.9 Glossary............................................. 71
8 Mechanical, Packaging, and Orderable
Information .............................................. 72

5
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com SLAS734G –APRIL 2011–REVISED APRIL 2016
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Revision HistoryCopyright © 2011–2016, Texas Instruments Incorporated
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from May 2, 2013 to April 27, 2016 Page
• Document format and organization changes throughout, including addition of section numbering........................ 1
• Added Device Information table .................................................................................................... 2
• Added Section 3.1,Related Products ............................................................................................. 7
• Moved Section 5,Specifications .................................................................................................. 13
• Added Section 5.2,ESD Ratings.................................................................................................. 13
• Added Section 5.8,Thermal Resistance Characteristics ...................................................................... 18
• Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 39
• Changed all instances of "INCHx = 0x1010" to "INCHx = 1010b" in Table 6-11,Labels Used by the ADC
Calibration Tags..................................................................................................................... 43
• Moved and renamed Section 6.10,I/O Port Diagrams......................................................................... 48
• Added notes to UCB0STE and UCA0CLK in Table 6-18...................................................................... 53
• Added notes to UCB0CLK and UCA0STE in Table 6-19...................................................................... 55
• Added "and PW28" to title of Section 6.10.8 .................................................................................... 62
• Added "and PW28" to title of Table 6-23......................................................................................... 63
• Added Section 7,Device and Documentation Support......................................................................... 64
• Added Section 8,Mechanical, Packaging, and Orderable Information ...................................................... 72

6
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G –APRIL 2011–REVISED APRIL 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Device Comparison Copyright © 2011–2016, Texas Instruments Incorporated
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website
at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
3 Device Comparison
Table 3-1 compares the available family members.
Table 3-1. Device Comparison(1)(2)
DEVICE BSL EEM FLASH
(KB) RAM (B) Timer_A ADC10 CHANNELS USCI_A0, USCI_B0 CLOCK I/O PACKAGE
MSP430G2533 1 1 16 512 2x TA3 8 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP
MSP430G2433 1 1 8 512 2x TA3 8 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP
MSP430G2333 1 1 4 256 2x TA3 8 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP
MSP430G2233 1 1 2 256 2x TA3 8 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP
MSP430G2403 1 1 8 512 2x TA3 – 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP
MSP430G2303 1 1 4 256 2x TA3 – 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP
MSP430G2203 1 1 2 256 2x TA3 – 1 LF, DCO,
VLO
24 32-QFN
24 28-TSSOP
16 20-TSSOP
16 20-PDIP

7
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com SLAS734G –APRIL 2011–REVISED APRIL 2016
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Device ComparisonCopyright © 2011–2016, Texas Instruments Incorporated
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for MSP 16-Bit and 32-Bit MCUs Low-power mixed-signal processors with smart analog and
digital peripherals for a wide range of industrial and consumer applications.
Products for Ultra-low Power MCUs MSP Ultra-Low-Power microcontrollers (MCUs) from Texas
Instruments (TI) offer the lowest power consumption and the perfect mix of integrated
peripherals for a wide range of low-power and portable applications.
Products for MSP430G2x/i2x Low-Cost Industrial MCUs MSP430G2x microcontrollers (MCUs) from
the MSP ultra-low-power MCU series, offers the low power and performance of 16-bit MSP
microcontrollers with a feature set targeted at cost sensitive applications.
Companion Products for MSP430G2533 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for MSP430G2533 TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.

PW28
(TOP VIEW)
1
DVCC
2
P1.0/TA0CLK/ACLK/A0
3
4
5
P1.3/ADC10CLK/VREF-/VEREF-/A3
6
7
8
P3.0/TA0.2 9
P3.1/TA1.0
10
P2.0/TA1.0 19 P3.5/TA0.1
20 P3.6/TA0.2
21 P3.7/TA1CLK
22
23
24 RST/NMI/SBWTDIO
25 TEST/SBWTCK
26 XOUT/P2.7
27 XIN/P2.6/TA0.1
28 DVSS
P1.6/TA0.1/ TDI/TCLKUCB0SOMI/UCB0SCL/A6/
P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA
P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI
P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO
P1.4/SMCLK/ TCK/VREF+/VEREF+/A4/UCB0STE/UCA0CLK
P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE
11
12
P2.2/TA1.1
13
P3.2/TA1.1
14
P3.3/TA1.2 15 P3.4/TA0.0
16 P2.3/TA1.0
17 P2.4/TA1.2
18 P2.5/TA1.2
P2.1/TA1.1
1
DVCC
2
P1.0/TA0CLK/ACLK/A0
3
4
5
P1.3/ADC10CLK/VREF-/VEREF-/A3
6
7
8
P2.0/TA1.0
9
P2.1/TA1.1
10
P2.2/TA1.1 11 P2.3/TA1.0
12 P2.4/TA1.2
13 P2.5/TA1.2
14
15
16 RST/NMI/SBWTDIO
17 TEST/SBWTCK
18 XOUT/P2.7
19 XIN/P2.6/TA0.1
20 DVSS
P1.6/TA0.1/ /TDI/TCLKUCB0SOMI/UCB0SCL/A6
P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA
P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI
P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO
P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK
P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE
N20
PW20
(TOP VIEW)
8
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G –APRIL 2011–REVISED APRIL 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 20-pin N or PW
package.
NOTE: ADC10 is available on MSP430G2x33 devices only.
NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
Figure 4-1. 20-Pin N or PW Package (Top View), MSP430G2x03 and MSP430G2x33
Figure 4-2 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 28-pin PW
package.
NOTE: ADC10 is available on MSP430G2x33 devices only.
Figure 4-2. 28-Pin PW Package (Top View), MSP430G2x03 and MSP430G2x33

RHB32
(TOP VIEW)
1
2
3
4
5
6
P2.0/TA1.0
7
P2.1/TA1.1
8NC
9
P2.2/TA1.1
10
P3.0/TA0.2
11
P3.1/TA1.0
12
P3.2/TA1.1
13
P3.3/TA1.2
14
P3.4/TA0.0
15
P3.5/TA0.1
16
P2.3/TA1.0
17
P2.4/TA1.2
18
P2.5/TA1.2
19
20
P3.6/TA0.2
21
P3.7/TA1CLK
22
23 RST/NMI/SBWTDIO
24 TEST/SBWTCK
25
XOUT/P2.7
26
XIN/P2.6/TA0.1
27
AVSS
28
DVSS
29
AVCC
30
DVCC
31
P1.0/TA0CLK/ACLK/A0/CA0
32
NC
P1.3/ADC10CLK/VREF-/VEREF-/A3
P1.1/TA0.0/ A1/
UCA0RXD/UCA0SOMI
P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO
P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK
P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE
P1.6/TA0.1/ /TDI/TCLKUCB0SOMI/UCB0SCL/A6
P1.7 /TDO/TDI/UCB0SIMO/UCB0SDA/A7
9
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com SLAS734G –APRIL 2011–REVISED APRIL 2016
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Terminal Configuration and FunctionsCopyright © 2011–2016, Texas Instruments Incorporated
Figure 4-3 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 32-pin RHB
package.
NOTE: ADC10 is available on MSP430G2x33 devices only.
Figure 4-3. 32-Pin RHB Package (Top View), MSP430G2x03 and MSP430G2x33

10
MSP430G2533 , MSP430G2433 , MSP430G2333 , MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G –APRIL 2011–REVISED APRIL 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated
(1) MSP430G2x33 devices only
4.2 Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
PW20,
N20 PW28 RHB32
P1.0/
2 2 31 I/O
General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
ACLK/ ACLK signal output
A0 ADC10 analog input A0(1)
P1.1/
3 3 1 I/O
General-purpose digital I/O pin
TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit
UCA0RXD/ USCI_A0 receive data input in UART mode
UCA0SOMI/ USCI_A0 slave data out/master in SPI mode
A1 ADC10 analog input A1(1)
P1.2/
4 4 2 I/O
General-purpose digital I/O pin
TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output
UCA0TXD/ USCI_A0 transmit data output in UART mode
UCA0SIMO/ USCI_A0 slave data in/master out in SPI mode
A2 ADC10 analog input A2(1)
P1.3/
5 5 3 I/O
General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output(1)
A3/ ADC10 analog input A3(1)
VREF-/VEREF- ADC10 negative reference voltage (1)
P1.4/
6 6 4 I/O
General-purpose digital I/O pin
SMCLK/ SMCLK signal output
UCB0STE/ USCI_B0 slave transmit enable
UCA0CLK/ USCI_A0 clock input/output
A4/ ADC10 analog input A4(1)
VREF+/VEREF+ ADC10 positive reference voltage(1)
TCK JTAG test clock, input terminal for device programming and test
P1.5/
7 7 5 I/O
General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output / BSL receive
UCB0CLK/ USCI_B0 clock input/output
UCA0STE/ USCI_A0 slave transmit enable
A5/ ADC10 analog input A5(1)
TMS JTAG test mode select, input terminal for device programming and test
P1.6/
14 22 21 I/O
General-purpose digital I/O pin
TA0.1/ Timer0_A, compare: Out1 output
A6/ ADC10 analog input A6(1)
UCB0SOMI/ USCI_B0 slave out/master in SPI mode,
UCB0SCL/ USCI_B0 SCL I2C clock in I2C mode
TDI/TCLK JTAG test data input or test clock input during programming and test

11
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Terminal Configuration and FunctionsCopyright © 2011–2016, Texas Instruments Incorporated
Table 4-1. Terminal Functions (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
PW20,
N20 PW28 RHB32
(2) TDO or TDI is selected by JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
P1.7/
15 23 22 I/O
General-purpose digital I/O pin
A7/ ADC10 analog input A7(1)
UCB0SIMO/ USCI_B0 slave in/master out in SPI mode
UCB0SDA/ USCI_B0 SDA I2C data in I2C mode
TDO/TDI JTAG test data output terminal or test data input during programming and
test(2)
P2.0/ 8 10 9 I/O General-purpose digital I/O pin
TA1.0 Timer1_A, capture: CCI0A input, compare: Out0 output
P2.1/ 9 11 10 I/O General-purpose digital I/O pin
TA1.1 Timer1_A, capture: CCI1A input, compare: Out1 output
P2.2/ 10 12 11 I/O General-purpose digital I/O pin
TA1.1 Timer1_A, capture: CCI1B input, compare: Out1 output
P2.3/ 11 16 15 I/O General-purpose digital I/O pin
TA1.0 Timer1_A, capture: CCI0B input, compare: Out0 output
P2.4/ 12 17 16 I/O General-purpose digital I/O pin
TA1.2 Timer1_A, capture: CCI2A input, compare: Out2 output
P2.5/ 13 18 17 I/O General-purpose digital I/O pin
TA1.2 Timer1_A, capture: CCI2B input, compare: Out2 output
XIN/ 19 27 26 I/O Input terminal of crystal oscillator
P2.6/ General-purpose digital I/O pin
TA0.1 Timer0_A, compare: Out1 output
XOUT/ 18 26 25 I/O Output terminal of crystal oscillator(3)
P2.7 General-purpose digital I/O pin
P3.0/ - 9 7 I/O General-purpose digital I/O pin
TA0.2 Timer0_A, capture: CCI2A input, compare: Out2 output
P3.1/ - 8 6 I/O General-purpose digital I/O pin
TA1.0 Timer1_A, compare: Out0 output
P3.2/ - 13 12 I/O General-purpose digital I/O pin
TA1.1 Timer1_A, compare: Out1 output
P3.3/ - 14 13 I/O General-purpose digital I/O
TA1.2 Timer1_A, compare: Out2 output
P3.4/ - 15 14 I/O General-purpose digital I/O
TA0.0 Timer0_A, compare: Out0 output
P3.5/ - 19 18 I/O General-purpose digital I/O
TA0.1 Timer0_A, compare: Out1 output
P3.6/ - 20 19 I/O General-purpose digital I/O
TA0.2 Timer0_A, compare: Out2 output
P3.7/ - 21 20 I/O General-purpose digital I/O
TA1CLK Timer1_A, clock signal TACLK input
RST/ 16 24 23 I Reset
NMI/ Nonmaskable interrupt input
SBWTDIO Spy-Bi-Wire test data input/output during programming and test

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Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated
Table 4-1. Terminal Functions (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
PW20,
N20 PW28 RHB32
TEST/ 17 25 24 I Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
SBWTCK Spy-Bi-Wire test clock input during programming and test
AVCC NA NA 29 NA Analog supply voltage
DVCC 1 1 30 NA Digital supply voltage
DVSS 20 28 27, 28 NA Ground reference
NC NA NA 8, 32 NA Not connected
QFN Pad NA NA Pad NA QFN package pad connection to VSS recommended.

13
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SpecificationsCopyright © 2011–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin(2) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Storage temperature, Tstg(3) Unprogrammed device –55 150 °C
Programmed device –55 150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
5.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA= 25°C (unless otherwise noted) MIN NOM MAX UNIT
VCC Supply voltage During program execution 1.8 3.6 V
During flash programming or erase 2.2 3.6
VSS Supply voltage 0 V
TAOperating free-air temperature –40 85 °C
fSYSTEM Processor frequency (maximum MCLK frequency
using the USART module)(1)(2)
VCC = 1.8 V,
Duty cycle = 50% ±10% DC 6
MHz
VCC = 2.7 V,
Duty cycle = 50% ±10% DC 12
VCC = 3.3 V,
Duty cycle = 50% ±10% DC 16

Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
16 MHz
System Frequency - MHz
12 MHz
6 MHz
1.8 V
Supply Voltage - V
3.3 V
2.7 V
2.2 V 3.6 V
14
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Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 5-1. Safe Operating Area
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IAM,1MHz Active mode (AM)
current at 1 MHz
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
2.2 V 230
µA
3 V 330 420

0.0
1.0
2.0
3.0
4.0
5.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC − Supply Voltage − V
Active Mode Current − mA
fDCO = 1 MHz
fDCO = 8 MHz
fDCO = 12 MHz
fDCO = 16 MHz
0.0
1.0
2.0
3.0
4.0
0.0 4.0 8.0 12.0 16.0
fDCO − DCO Frequency − MHz
Active Mode Current − mA
TA= 25 °C
TA= 85 °C
VCC = 2.2 V
VCC = 3 V
TA= 25 °C
TA= 85 °C
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5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)
Figure 5-2. Active Mode Current vs VCC, TA= 25°C Figure 5-3. Active Mode Current vs DCO Frequency

16
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Specifications Copyright © 2011–2016, Texas Instruments Incorporated
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
ILPM0,1MHz Low-power mode 0
(LPM0) current(3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C 2.2 V 56 µA
ILPM2 Low-power mode 2
(LPM2) current(4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C 2.2 V 22 µA
ILPM3,LFXT1 Low-power mode 3
(LPM3) current(4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0 25°C 2.2 V 0.7 1.5 µA
ILPM3,VLO Low-power mode 3
current, (LPM3)(4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0 25°C 2.2 V 0.5 0.7 µA
ILPM4 Low-power mode 4
(LPM4) current(5)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C 2.2 V 0.1 0.5 µA
85°C 0.8 1.7

0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
-40
I – Low-Power Mode Current – µA
LPM3
V = 3.6 V
CC
T – Temperature – °C
A
VCC = 1.8 V
VCC = 3 V
VCC = 2.2 V
-20 020 40 60 80
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
-40
I – Low-Power Mode Current – µA
LPM4
V = 3.6 V
CC
T – Temperature – °C
A
VCC = 1.8 V
VCC = 3 V
VCC = 2.2 V
-20 020 40 60 80
17
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5.7 Typical Characteristics, Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 5-4. LPM3 Current vs Temperature Figure 5-5. LPM4 Current vs Temperature

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(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
5.8 Thermal Resistance Characteristics
PARAMETER VALUE (1) UNIT
RθJA Junction-to-ambient thermal resistance, still air (2)
VQFN (RHB-32) 32.1
°C/W
TSSOP (PW-28) 72.2
TSSOP (PW-20) 86.5
PDIP (N-20) 49.3
RθJC(TOP) Junction-to-case (top) thermal resistance (3)
VQFN (RHB-32) 22.3
°C/W
TSSOP (PW-28) 18.3
TSSOP (PW-20) 20.8
PDIP (N-20) 41
RθJC(BOTTOM) Junction-to-case (bottom) thermal resistance
VQFN (RHB-32) 1.4
°C/W
TSSOP (PW-28) N/A
TSSOP (PW-20) N/A
PDIP (N-20) N/A
θJB Junction-to-board thermal resistance (4)
VQFN (RHB-32) 6.1
°C/W
TSSOP (PW-28) 30.4
TSSOP (PW-20) 39
PDIP (N-20) 30.2
ΨJT Junction-to-package-top characterization parameter
VQFN (RHB-32) 0.3
°C/W
TSSOP (PW-28) 0.7
TSSOP (PW-20) 0.8
PDIP (N-20) 18.1
ΨJB Junction-to-board characterization parameter
VQFN (RHB-32) 6.1
°C/W
TSSOP (PW-28) 29.9
TSSOP (PW-20) 38.1
PDIP (N-20) 30.1

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5.9 Schmitt-Trigger Inputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage 0.45 VCC 0.75 VCC V
3 V 1.35 2.25
VIT– Negative-going input threshold voltage 0.25 VCC 0.55 VCC V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT–) 3 V 0.3 1 V
RPull Pullup or pulldown resistor For pullup: VIN = VSS
For pulldown: VIN = VCC 3 V 20 35 50 kΩ
CIInput capacitance VIN = VSS or VCC 5 pF
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
5.10 Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.y) High-impedance leakage current See (1) (2) 3 V ±50 nA
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
5.11 Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH High-level output voltage I(OHmax) = –6 mA(1) 3 V VCC – 0.3 V
VOL Low-level output voltage I(OLmax) = 6 mA(1) 3 V VSS + 0.3 V
(1) A resistive divider with two 50-kΩresistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
5.12 Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fPx.y Port output frequency (with load) Px.y, CL= 20 pF, RL= 1 kΩ(1) (2) 3 V 12 MHz
fPort_CLK Clock output frequency Px.y, CL= 20 pF(2) 3 V 16 MHz

VOH − High-Level Output Voltage − V
−25
−20
−15
−10
−5
0
0 0.5 1 1.5 2 2.5
VCC = 2.2 V
P1.7
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOH − High-Level Output Voltage − V
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5
VCC = 3 V
P1.7
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5
VCC = 2.2 V
P1.7 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
VOL − Low-Level Output Voltage − V
0
10
20
30
40
50
0 0.5 1 1.5 2 2.5 3 3.5
VCC = 3 V
P1.7 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
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5.13 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage Figure 5-7. Typical Low-Level Output Current vs Low-Level Output Voltage
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage