Texas Instruments TMS570LS User manual

Application Report
Lit. Number –Month Year
1
Getting Started With TMS570LS Microcontrollers
Sunil Oak AEC-Automotive Microcontrollers
ABSTRACT
This application report provides a brief overview of the TMS570LS series of microcontrollers. It
describes the initialization procedure for the TMS570LS series of microcontrollers. The
document also shows code fragments from source files that are generated using the HALCoGen
tool. All code constructs used in this document are also defined in header files also generated by
the same utility.
Contents
1Block Diagram.................................................................................................................................3
2Overview of Features......................................................................................................................4
3Standard Initialization Sequence for TMS570LS Microcontrollers.............................................7
3.1 Enabling Floating Point Coprocessor (FPU) .............................................................................8
3.2 Initialization of Cortex-R4F Registers........................................................................................9
3.3 Initialize stack pointers for all CPU operating modes..............................................................11
3.4 Enable the Cortex-R4F CPU‟s Vectored Interrupt Controller (VIC) Port .................................12
3.5 Configure Flash Access ..........................................................................................................13
3.6 Configure flash bank and pump power modes........................................................................14
3.7 Configure PLLs........................................................................................................................17
3.7.1 FMzPLL.......................................................................................................................17
3.7.2 FPLL............................................................................................................................20
3.8 Enable Clock Sources.............................................................................................................22
3.8.1 Available Clock Sources on TMS570LS Microcontrollers ...........................................22
3.8.2 Control Registers for Enabling and Disabling Clock Sources......................................23
3.8.3 Example Clock Source Configuration..........................................................................24
3.9 Clock Domains........................................................................................................................25
3.9.1 Mapping Clock Domains to Clock Sources .................................................................26
3.9.2 Example Clock Domain Mapping ................................................................................27
3.9.3 Configuring VCLK and VCLK2 Frequencies................................................................27
3.10 Run CPU Self-Test..................................................................................................................29
3.11 Release Reset and Clocks to Peripherals...............................................................................30
3.12 Memories‟ Self-Test ................................................................................................................31
3.13 Memories‟ Auto-Initialization ...................................................................................................32
3.14 Vectored Interrupt Manager Configuration..............................................................................34
3.14.1 Example VIM RAM Configuration................................................................................34
3.14.2 Configure Interrupts to be Fast Interrupts or Normal Interrupts...................................36
3.14.3 Enabling Interrupts ......................................................................................................36
3.15 Additional Initializations Required by Compiler .......................................................................39
3.16 Call the Main Application.........................................................................................................39

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2Getting Started With TMS570LS Microcontrollers
Figures
Figure 1. Device Block Diagram........................................................................................................3
Figure 2. Flash Read Control Register: FRDCNTL, Address = 0xFFF87000...............................13
Figure 3. Flash Bank Fall-Back Control Register: FBFALLBACK, Address = 0xFFF87040 ......14
Figure 4. Flash Bank Access Control Register: FBAC, Address = 0xFFF8703C........................15
Figure 5. Flash Pump Access Control Register 1: FPAC1, Address = 0xFFF87048 ..................16
Figure 6. Flash Pump Access Control Register 2: FPAC2, Address = 0xFFF8704C..................16
Figure 7. FMzPLL Block Diagram ...................................................................................................17
Figure 8. PLL Control Register 1: PLLCTL1, Address = 0xFFFFFF70.........................................18
Figure 9. PLL Control Register 2: PLLCTL2, Address = 0xFFFFFF74.........................................19
Figure 10. FPLL Block Diagram ........................................................................................................20
Figure 11. PLL Control Register 3: PLLCTL3, Address = 0xFFFFE100.........................................21
Figure 12. Clock Source Disable Register: CSDIS, Address = 0xFFFFFF30 ................................23
Figure 13. Clock Source Disable Set Register: CSDISSET, Address = 0xFFFFFF34...................23
Figure 14. Clock Source Disable Clear Register: CSDISCLR, Address = 0xFFFFFF38...............24
Figure 15. GCLK, HCLK , VCLKx Source Register: GHVSRC, Address = 0xFFFFFF48...............26
Figure 16. Asynchronous Clock Source Register: VCLKASRC, Address = 0xFFFFFF4C ..........26
Figure 17. RTI Clock Source Register: RCLKSRC, Address = 0xFFFFFF50.................................27
Figure 18. Peripheral Clock Control Register: CLKCNTL, Address = 0xFFFFFFD0 ....................28
Figure 19. Memory Hardware Initialization Global Control Register: MINITGCR, Address =
0xFFFFFF5C......................................................................................................................32
Figure 20. Memory Self-Test / Initialization Control Register: MSIENA, Address = 0xFFFFFF6032
Figure 21. Memory Self-Test / Initialization Status Register: MSTCGSTAT, Address =
0xFFFFFF68......................................................................................................................33
Figure 22. VIM Interrupt Address Memory Map...............................................................................34
Figure 23. FIQ/IRQ Control Register 0: FIRQPR0, Address = 0xFFFFFE10 ..................................36
Figure 24. FIQ/IRQ Control Register 1: FIRQPR1, Address = 0xFFFFFE14 ..................................36
Figure 25. Interrupt Enable Set Register 0: REQENASET0, Address = 0xFFFFFE30 ..................37
Figure 26. Interrupt Enable Set Register 1: REQENASET1, Address = 0xFFFFFE34 ..................37
Figure 27. Interrupt Enable Clear Register 0: REQENACLR0, Address = 0xFFFFFE40...............37
Figure 28. Interrupt Enable Clear Register 1: REQENACLR1, Address = 0xFFFFFE44...............38
Tables
Table 1. Clock Sources on TMS570LS Microcontrollers.............................................................22
Table 2. Clock Domains on TMS570LS Microcontrollers............................................................25

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Getting Started With TMS570LS Microcontrollers 3
1Block Diagram
Figure 1 shows a high-level block diagram of the TMS570LS series microcontroller.
Figure 1. Device Block Diagram
Flash
2.0MB
with ECC
CRC
OSC
NHET
SYS
LIN2
MiBSPI1
DCAN1
OSCIN
OSCOUT
TRST
TMS
TCK
TDI
TDO
RST
PORRST
TEST
NHET[31:0]
LIN2RX
LIN2TX
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1CLK
MIBSPI1SCS[3:0]
CAN1RX
CAN1TX
FLTP1
ECLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI3CLK
DCAN2 CAN2RX
CAN2TX
128 Words
128 Buffers
MIBSPI3SCS[3:0]
VIM
HET TU
8DCP
64 Messages
64 Messages
DMA
16 Channels
Primary SCR
ETM
ETMTRACECTL
ETMTRACECLKOUT CCM-R4
RTP
DMM
RTCK
RTPDATA[15:0]
RTPSYNC
RTPCLK
1Port
MIBSPI1ENA
with Parity
with Parity
with Parity
with Parity
VCCP1
withParity
withMPU
ETMDATA[31:0]
MIBSPI3ENA
FLTP2
with MPU
RTPENA
8 Transfer
Groups
64 Channel
withParity
2Channel
Clock
Monitor
MiBSPI3
128 Buffers
with Parity
8 Transfer
Groups
Flexray
8k Byte
with Parity
FRAYRX1
FRAYTX1
FRAYTXEN1
FRAYRX2
FRAYTX2
FRAYTXEN2
DCAN3 CAN3RX
CAN3TX32 Messages
with Parity
RAM
160kB
with ECC
FMzPLL
Kelvin_GND
DAP
DMMENA
DMMSYNC
DMMCLK
DMMDATA[1:0] withParity
Periph Bridge
Cortex-R4F
Msg RAM
Flexray
with MPU
withParity
RTI
SCR
2
TU
SCR
1
Note:
Priorities
SCR2 : round robin
SCR : round robin
SCR1 : 1=DMA, 2=DMM, 3=DAP
DMMDATA[15:2]*
MiBADC2
64 Words
with Parity
AD2IN[7:0]
AD2EVT
MiBSPIP5 MIBSPI5SIMO[3:0]*
MIBSPI5SOMI[3:0]*
MIBSPI5CLK*
MIBSPI5SCS[3:0]*
MIBSPI5ENA*
128 Buffers
with Parity
8 Transfer
Groups
32 Regions
with DMMDATA[15:2] pins
64 Words
with
ICEPick
2RAMblocks
ESM
ERROR
MiBADC1
64 Words
withParity
AD1IN[7:0]
VSSAD
ADREFHI
ADREFLO
AD1EVT
12Bit 12Bit
with MPU
Cortex-R4F
with MPU
GIO GIOA[7:0] /INT[7:0]
GIOB[7:0]
LIN1 LIN1RX
LIN1TX
STC
LBIST
EMIFADD[21:0]
EMIFDATA[15:0]
EMIFCS[3:0]
EMIFWE
EMIFOE
EMIF
EMIFBADD[1:0]
VCCAD
ADSIN[15:8]
P
O
M
*MIBSPIP5 pins are multiplexed
ETMTRACECLKIN
EMIFDQM[1:0]
SCR
PCR
FPLL
for Flexray
VMON
VccIO
Vcc

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4Getting Started With TMS570LS Microcontrollers
2Overview of Features
The TMS570LS series is a high-performance microcontroller family which has been certified for
use in IEC 61508 SIL3 safety systems.
The microcontrollers included in the TMS570LS Series are:
–TMS570LS20216
–TMS570LS20206
–TMS570LS10216
–TMS570LS10206
–TMS570LS10116
–TMS570LS10106
TMS570LS Series microcontrollers contain the following:
Dual ARM Cortex™-R4F processors operating in lock-step
–1.6 DMIPS/MHz
–CPU clock speeds up to 160MHz, providing up to 250 DMIPS
–Big-Endian
–Core-Compare Module (CCM-R4) to monitor lock-step operation
–Supports Built-In Self-Test (BIST)
Integrated Memory
–Up to 2MB Flash Memory
Non-volatile, electrically-erasable and programmable with 64-bit data bus interface
Single 3.3V supply needed for all read, program and erase operations
Connected to Tightly-Coupled Memory interface (TCM A) of the Cortex™-R4F CPU
Protects accesses with ECC (Single Error Correction Double Error Detection) logic
Supports accesses up to 160MHz in pipelined mode
–Up to 160KB SRAM
Supports single-cycle accesses at the maximum specified clock speed
Allows read/write accesses in byte, half-word (16 bits), and word (32 bits) sizes
Protects accesses with ECC (Single Error Correction Double Error Detection) logic
External Memory Interface (EMIF)
–Provides 8- or 16-bit interface to external asynchronous memories, 22 address lines
–Supports up to 4 chip selects
–Each chip select can address up to 32MB in 16-bit mode or 16MB in 8-bit mode

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Getting Started With TMS570LS Microcontrollers 5
TMS570 High-Performance Architecture for Safety-Critical Applications
–Consistent memory map across entire microcontroller family
–Real-Time Interrupt (RTI) for use as OS timer
Up to 6 configurable periodic interrupts
–Vectored Interrupt Manager (VIM)
Supports vectored interrupt controller (NVIC) port on the Cortex™-R4F CPU
Reduces interrupt latency even if NVIC port is not used
–2-Channel Cyclic Redundancy Checker (CRC)
Allows integrity checks for memories
Direct Memory Access (DMA) controller
–16 channels
–32 hardware requests configured by control packets
–Control packet information protected by parity error detection
–Built-in Memory Protection Unit (MPU) dedicated to prevent erroneous DMA transfers
Enhanced High-End Timer (NHET)
–Programmable timer coprocessor with its own assembly microcode
–128-word instruction memory with parity protection
–32 programmable channels for output compare or input capture functions
–Unused channels can be used as general-purpose I/O signals
–Dedicated transfer unit (HTU) with 8 programmable transfer configurations
–Control packet information protected by parity error detection
–Built-in Memory Protection Unit (MPU) dedicated to prevent erroneous HTU transfers
Analog-to-Digital Converters (ADC)
–Two 12-bit-resolution Successive Approximation Resistor A2D converters
–Dedicated memory to store up to 64 conversion results, with parity protection
–24 total input channels, 8 shared channels
Communication Modules
–Dual-channel FlexRay™ Controller
8 KB message RAM with parity protection
Dedicated transfer unit (FTU)
Parity protection for transfer unit configuration memory
Dedicated MPU to protect against erroneous transfers by FTU
–Three Multi-Buffered Serial Peripheral Interface (MibSPI) Controllers

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6Getting Started With TMS570LS Microcontrollers
4 chip selects and 1 enable for each MibSPI
128 transmit and receive buffers with parity protection for each MibSPI
One MibSPI supports unique parallel interface mode with up to 4-bit data
–Two Local Interconnect Network (LIN) Interface Controllers
Compliant to LIN specification version 2.0
Support the standard Serial Communication Interface (SCI) mode
–Three Controller Area Network (CAN) Controllers
Two controllers with 64 mailboxes, one controller with 32 mailboxes
Parity protection for mailbox memory
Trace and Calibration Interfaces
–Embedded Trace Macrocell (ETM-R4) for Cortex™-R4F
Provides trace for instruction and data accesses by the Cortex™-R4F CPU
–Parameter Overlay Module (POM)
Re-routes flash accesses to external memory via the EMIF
Allows application to update parameters without re-programming the flash
–Data Modification Module (DMM)
Provides ability to modify data anywhere within the 4GB addressable space
–RAM Trace Port (RTP)
Provides a high-speed trace of RAM accesses

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Getting Started With TMS570LS Microcontrollers 7
3Standard Initialization Sequence for TMS570LS Microcontrollers
A typical basic sequence to be followed for initialization and configuration of key features on the
TMS570LS Series microcontrollers is summarized below and detailed in the following sections.
This is not a mandatory sequence. Applications that are non-safety-critical can choose to not
use the ECC feature for flash and RAM accesses, for example.
Enable the Floating Point Unit (FPU) inside the Cortex-R4F CPU
Initialize the CPU registers and FPU registers
Initialize stack pointers for all operating modes
Enable CPU‟s dedicated vectored interrupt controller (VIC) port
Set up flash wrapper for required wait states and pipelined mode
Set up flash bank and pump power modes
Configure PLL control registers
Enable desired clock sources
Map device clock domains to desired clock sources
Run the Built-In Self-Test for the CPU
Release peripherals from reset and enable clocks to all peripherals
Run self-tests on all device memories using Programmable Built-In Self-test (PBIST)
Perform auto-initialization for all on-chip SRAMs
Program Vectored Interrupt Manager memory to map all interrupt service routine addresses
Configure IRQ / FIQ interrupt priorities for all interrupt channels
Enable the desired interrupts
Initialize copy table, global variables, and constructors
Call the main application
The following sections describe each of the above steps in more detail. Code examples are also
provided.

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8Getting Started With TMS570LS Microcontrollers
3.1 Enabling Floating Point Coprocessor (FPU)
The floating point coprocessor is disabled upon a CPU reset and must be enabled.
First access to the FPU must be enabled.
MRC p15, #0x0, r0, c1, c0, #2
MOV r3, #0xf00000
ORR r0, r0, r3
MCR p15, #0x0, r0, c1, c0, #2
MRC p15, #0x0, r0, c0, c0
Enable the FPU
MOV r0, #0x40000000
FMXR FPEXC, r0

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Getting Started With TMS570LS Microcontrollers 9
3.2 Initialization of Cortex-R4F Registers
The TMS570LS series of microcontrollers include dual Cortex-R4F CPUs running in a lock-step
operation mode. A Core Compare Module (CCM-R4) compares the output signals from each
R4F CPU. Any difference in the two CPUs‟ outputs is flagged as a fault of a high severity level.
The CPU internal core registers need to be initialized to a predefined state in order to prevent an
error from being flagged during system initialization.
Initialize CPU registers R0 through R12
mov r0, lr
mov r1, #0x03D0
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
Initialize CPU banked registers
orr r13, r1, #0x0001
msr cpsr_cxsf, r13
msr spsr_cxsf, r13
mov lr, r0
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
orr r13, r1, #0x0002
msr cpsr_c, r13
msr spsr_cxsf, r13
mov lr, r0
orr r13, r1, #0x0007
msr cpsr_c, r13
msr spsr_cxsf, r13
mov lr, r0
orr r13, r1, #0x000B
msr cpsr_c, r13
msr spsr_cxsf, r13
mov lr, r0
orr r13, r1, #0x0003
msr cpsr_c, r13
msr spsr_cxsf, r13

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10 Getting Started With TMS570LS Microcontrollers
Initialize the FPU registers
fmdrr d0, r1, r1
fmdrr d1, r1, r1
fmdrr d2, r1, r1
fmdrr d3, r1, r1
fmdrr d4, r1, r1
fmdrr d5, r1, r1
fmdrr d6, r1, r1
fmdrr d7, r1, r1
fmdrr d8, r1, r1
fmdrr d9, r1, r1
fmdrr d10, r1, r1
fmdrr d11, r1, r1
fmdrr d12, r1, r1
fmdrr d13, r1, r1
fmdrr d14, r1, r1
fmdrr d15, r1, r1
Initialize CPU return stack
bl $+4
bl $+4
bl $+4
bl $+4
bx r0

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Getting Started With TMS570LS Microcontrollers 11
3.3 Initialize stack pointers for all CPU operating modes
Define the base addresses for the stacks used for the different operating modes. The addresses
listed below are only examples and can be defined by the application as required.
user: .word 0x08000000+0x00001000
svc: .word 0x08000000+0x00001000+0x00000100
fiq: .word 0x08000000+0x00001000+0x00000100+0x00000100
irq: .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
abort: .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
undef: .word
0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
The Cortex-R4F CPU can operate in one of several modes:
User mode (USR) is the usual mode for the execution of ARM or Thumb programs. It is
used for executing most application programs. Many control registers on the TMS570LS
microcontroller are not writable in user mode.
msr cpsr_c, #0xDF
ldr sp, user
Fast interrupt mode (FIQ) is entered upon taking a fast interrupt.
msr cpsr_c, #0xD1
ldr sp, fiq
Interrupt mode (IRQ) is entered on taking a normal interrupt.
msr cpsr_c, #0xD2
ldr sp, irq
Abort mode (ABT) is entered after a data or instruction abort.
Undefined mode (UND) is entered when an undefined instruction exception occurs.
msr cpsr_c, #0xDB
ldr sp, undef
System mode (SYS) is a privileged mode for the operating system. This is also the default
mode of the CPU after a CPU reset.
Supervisor mode (SVC) is a protected mode for the operating system and is entered upon
taking a Supervisor Call (SVC).
msr cpsr_c, #0xD3
ldr sp, svc
The application can initialize the stack pointers in the above sequence. This will leave the CPU
in the Supervisor (SVC) mode once the stack pointers are initialized.

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12 Getting Started With TMS570LS Microcontrollers
3.4 Enable the Cortex-R4F CPU’s Vectored Interrupt Controller (VIC) Port
The CPU has a dedicated port that enables the Vectored Interrupt Manager (VIM) module to
supply the address of an interrupt service routine along with the interrupt (IRQ) signal. This
provides faster entry into the interrupt service routine versus the CPU having to decode the
pending interrupts and identify the highest priority interrupt to be serviced first.
The VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC
is enabled by setting the VE bit in the CPU‟s System Control Register, as shown below.
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x01000000
mcr p15, #0, r0, c1, c0, #0

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Getting Started With TMS570LS Microcontrollers 13
3.5 Configure Flash Access
The flash memory on the TMS570LS series microcontrollers is a non-volatile electrically
erasable and programmable memory.
The TMS570LS microcontrollers contain a digital wrapper module that manages all accesses to
the flash memory. A flash access can be completed without any wait states required for bus
master clock speeds up to 36MHz. If the bus clock is faster than 36MHz, then any flash access
requires the appropriate number of wait states depending on the bus clock speed. The
TMS570Ls series microcontrollers support clock speeds up to 160MHz. Please refer to the
device datasheet for the actual maximum allowed speed as it varies per the package type.
Suppose that the application requires the microcontroller to run at the maximum supported
speed of 160MHz. This requires 1 address wait state and 3 data wait states for any access to
the flash memory. These wait states need to be configured in the flash wrapper registers.
The flash wrapper also features a special pipeline mode. When this mode is enabled, the
wrapper reads 128 bits from the flash memory and holds them in buffers that the CPU can read
from without any wait state. The CPU can read 32 or 64 bits of instructions or data from the
pipeline buffers.
The register inside the flash wrapper that controls the wait states and the pipeline mode is
shown below.
Figure 2. Flash Read Control Register: FRDCNTL, Address = 0xFFF87000
The RWAIT field configures the number of data read wait states.
The ASWSTEN field enables the generation of 1 address wait state. The address bus is
latched one cycle before it is decoded for a pipeline hit or miss.
The ENPIPE field is sued to enable or disable the pipeline mode of the flash wrapper.
The sequence to configure the wait states and to enable the pipeline mode is as follows.
flashWREG->FRDCNTL = 0x01000000U
| (3U << 8U) // 3 data wait states
| (1U << 4U) // 1 address wait state enabled
| 1U; // Enable pipeline mode

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14 Getting Started With TMS570LS Microcontrollers
3.6 Configure flash bank and pump power modes
The flash banks and pump used on the TMS570LS series microcontrollers support three
different operating modes to optimize power consumption.
a. Active mode
Flash bank sense amplifiers and sense reference are enabled
All circuits of flash charge pump are enabled
b. Standby mode (only for flash banks)
Flash bank sense reference is enabled but sense amplifiers are disabled
c. Sleep Mode
Flash bank sense amplifiers and sense reference are disabled
All circuits of flash charge pump are disabled
The flash banks and charge pump are in the active state by default and after any system reset.
The flash wrapper allows the application to configure “fall back” power states for the flash banks
and charge pump. The flash banks and pump automatically switch the power mode to the
selected fall back state when there is no access to the flash banks detected within a user-
configurable time.
The flash wrapper also contains special timers to automatically sequence the flash banks and
pump between the active and the selected fall-back states. A read access to any flash bank
which is in a non-active power state will “wake up” both the selected bank and the charge pump
to active power state. Programming and erase operations are only allowed on banks in active
state.
The flash wrapper register that controls the flash banks‟ power states is shown below.
Figure 3. Flash Bank Fall-Back Control Register: FBFALLBACK, Address = 0xFFF87040
Each of the BANKPWRx fields configures the fall-back mode for a single flash bank. The
TMS570LS microcontrollers support up to 4 flash banks.
Configuration of fall back mode for the flash banks:

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Getting Started With TMS570LS Microcontrollers 15
enum flashWPowerModes
{
SYS_SLEEP = 0U, /** Flash bank power mode sleep */
SYS_STANDBY = 1U, /** Flash bank power mode standby */
SYS_ACTIVE = 3U /** flash bank power mode active */
};
flashWREG->FBFALLBACK = 0x00000000
| (SYS_SLEEP << 6U) // Bank3 falls back to SLEEP
| (SYS_SLEEP << 4U) // Bank2 falls back to SLEEP
| (SYS_SLEEP << 2U) // Bank1 falls back to SLEEP
| SYS_SLEEP; // Bank0 falls back to SLEEP
The above code fragment configures even the fall-back mode for each available flash bank to be
the sleep mode. The application can choose to configure these modes differently as required.
The power savings can be disabled completely by selecting the active state to also be the fall-
back power state, which is the default.
There are a few other registers that control the timing sequence for entry to a fall-back mode
and wake up to active mode. These are described now.
Figure 4. Flash Bank Access Control Register: FBAC, Address = 0xFFF8703C
The OTPPROTDIS field is not relevant to power modes.
The BAGP field configures the flash banks‟ Active Grace Period (AGP). This is the starting
count value for a down-counter. An access to a flash bank before this counter counts down
to 0 causes a reload of this counter to the configured AGP value. In effect, the AGP delays
the flash banks‟ entry into the selected fall-back mode by 0 to 255 HCLK/16 cycles. This
value must be greater than 1 when the fall-back mode is not ACTIVE.
The VREADST field controls the delay, in terms of HCLK cycles, between the time when the
charge pump generates the required read voltage (VREAD) and the time when the flash
bank starts its own power up sequence.
NOTE: The flash banks have hard-coded timings for transitioning from sleep to standby to active
power states. These timings are not configurable by the application.

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16 Getting Started With TMS570LS Microcontrollers
flashWREG->FMAC = 0x00000003; // Select flash bank3
flashWREG->FBAC |= 0x0000FF00; // Select 255 HCLK/16 cycles as the bank3 AGP
flashWREG->FMAC = 0x00000002; // Select flash bank2
flashWREG->FBAC |= 0x0000FF00; // Select 255 HCLK/16 cycles as the bank2 AGP
flashWREG->FMAC = 0x00000001; // Select flash bank1
flashWREG->FBAC |= 0x0000FF00; // Select 255 HCLK/16 cycles as the bank1 AGP
flashWREG->FMAC = 0x00000000; // Select flash bank0
flashWREG->FBAC |= 0x0000FF00; // Select 255 HCLK/16 cycles as the bank0 AGP
Figure 5. Flash Pump Access Control Register 1: FPAC1, Address = 0xFFF87048
The PSLEEP field configures the time that the flash pump takes for transitioning from the
sleep state to the standby state. This is specified in terms of HCLK/2 cycles. Please check
the TMS570LS datasheet to identify the minimum time required for the flash pump to switch
from the sleep state to the standby state.
The PUMPPWR field defines whether the flash pump falls back into sleep mode, or remains
active.
flashWREG->FPAC1 = 0x00640000; // PSLEEP = 100 HCLK/2 cycles,
// Pump fall-back state = SLEEP
Figure 6. Flash Pump Access Control Register 2: FPAC2, Address = 0xFFF8704C
The PAGP field defines the active grace period for the flash charge pump. This defines the
starting count for a down counter. An access to the flash memory reloads this counter with
the selected PAGP value. After the last access to flash memory, the down counter delays
the flash pump‟s entry to the selected fall-back mode by 0 to 65536 HCLK/16 cycles.
flashWREG->FPAC2 = 0x000000FF; // PSLEEP = 255 HCLK/16 cycles

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Getting Started With TMS570LS Microcontrollers 17
3.7 Configure PLLs
The TMS570LS series of microcontrollers contain a Frequency-Modulated Phase-Locked-Loop
(FMzPLL) macro that allows the input oscillator frequency to be multiplied to a higher frequency
than can be conveniently achieved with an external resonator or crystal. Additionally the
FMzPLL allows the flexibility to generate many different frequency options from a fixed crystal or
resonator.
The FMzPLL allows the application to superimpose a “modulation frequency” signal on the
selected base frequency signal output from the FMzPLL. This reduces the electromagnetic
energy of the output signal by spreading it across a controlled frequency range around the base
frequency. This mode is disabled by default, and the application can enable it in applications
sensitive to noise emissions.
The TMS570LS microcontrollers also contain a second non-modulating PLL macro. This is the
FPLL macro. The FPLL can be independently configured to generate a second high-frequency
clock source for specific uses.
3.7.1 FMzPLL
3.7.1.1 FMzPLL Block Diagram
Figure 7 shows a high-level block diagram of the FMzPLL macro.
Figure 7. FMzPLL Block Diagram
The oscillator circuit drives an external crystal or resonator, which generates the reference
input clock (CLKIN). The FMzPLL macro supports CLKIN from 5MHz to 20MHz.
The FMzPLL divides down this CLKIN by a value, NR, such that the divided clock (INTCLK)
is between 1.63MHz and 6.53MHz. NR can be between 1 and 64.
The FMzPLL multiplies INTCLK by a value NF, such that the multiplication result (VCOCLK)
is between 120MHz and 500MHz. NF can be between 92 and 184.
The VCOCLK is divided down by a value OD. The divided clock (Post-ODCLK) frequency
must not exceed the maximum device frequency. OD can be between 1 and 8.

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18 Getting Started With TMS570LS Microcontrollers
The post-ODCLK is further divided by a value R to generate the FMzPLL output clock
(PLLCLK). The PLLCLK frequency must not exceed the device maximum frequency
specified in the datasheet.
3.7.1.2 FMzPLL Slip Detector
The FMzPLL macro has a slip detector circuit that compares the CLKIN to the VCOCLK and
flags any 2-cycle slips. The application can choose the response to a PLL slip indication from
among 3 choices: do nothing, or cause a system reset, or bypass the FMzPLL such that the
CLKIN frequency itself is supplied as the output from the FMzPLL macro.
3.7.1.3 FMzPLL Configuration
The FMzPLL has two registers (PLLCTL1 and PLLCTL2) located within the System module on
the TMS570LS microcontrollers. These are described now.
Figure 8. PLL Control Register 1: PLLCTL1, Address = 0xFFFFFF70
Reset-On-Slip (ROS) selects whether a PLL slip condition causes a system reset or not.
–ROS = 1 causes a system reset when a PLL slip is flagged.
NOTE: The Bypass On Slip (BPOS) functionality must be disabled to use the ROS functionality.
Bypass-On-Slip (BPOS) defines the PLL behavior when a slip is flagged.
–BPOS = 10 ignores a PLL slip condition flagged by the FMzPLL macro.
–Writing any other value to BPOS causes the FMzPLL to be bypassed so that the CLKIN
is used as the output from the FMzPLL macro.
NOTE: If the ROS bit is also „1‟ when the FMzPLL is bypassed, then a system reset occurs and
the FMzPLL output is not bypassed.
PLLDIV defines the R-divider.
–R = PLLDIV + 1
–fPLLCLK = fpost-ODCLK / R
Reset-on-Oscillator-Fail (ROF) controls the response to an oscillator failure detected by the
clock monitor and is not relevant to the PLL configuration discussion.

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Getting Started With TMS570LS Microcontrollers 19
REFCLKDIV defines the NR-divider.
–NR = REFCLKDIV + 1
–fINTCLK = fCLKIN / NR
PLLMUL defines the NF multiplier
–NF = (PLLMUL / 256) + 1
–fVCOCLK = fINTCLK * NF
Figure 9. PLL Control Register 2: PLLCTL2, Address = 0xFFFFFF74
Setting the FM ENA bit enables the modulation frequency to be superimposed on the output
of the FMzPLL macro.
SPREADINGRATE defines the modulation frequency used.
–NS = SPREADINGRATE + 1
–Modulation frequency, fmod = fs = fINTCLK / (2 * NS)
BWADJ defines the FMzPLL modulation bandwidth adjustment.
–NB = BWADJ + 1
–fBW = fnom_BW / NB
NOTE: NB must be set to 7 when modulation is not used. This is also the default value.
ODPLL defines the OD-divider.
–OD = ODPLL + 1
–fpost-ODCLK = fVCOCLK / OD
SPR_AMOUNT defines the frequency modulation depth divider.
–NV = SPR_AMOUNT + 1

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20 Getting Started With TMS570LS Microcontrollers
3.7.1.4 Example FMzPLL configuration
systemREG1->PLLCTL1 = 0x00000000U
| 0x20000000U // No reset on slip, bypass on slip
| (0U << 24U) // R = 1
| (5U << 16U) // NR = 6
| (119U << 8U); // NF = 120
systemREG1->PLLCTL2 = 0x00000000U // Modulation disabled
| (255U << 22U) // NS = 256
| (7U << 12U) // NB = 8
| (1U << 9U) // OD = 2
| 61U; // NV = 62
This example configuration results in a FMzPLL output clock frequency of:
fPLLCLK = (fCLKIN / 6) * 120 / 2 / 1 = fCLKIN * 10
TI provides a GUI-based utility that allows the user to easily calculate the PLL control register
settings.
This utility can be found at: http://focus.ti.com/docs/toolsw/folders/print/fmzpll_calculator.html
3.7.2 FPLL
3.7.2.1 FPLL Block Diagram
Figure 10. FPLL Block Diagram
The FPLL generates a clock output signal using an external resonator or crystal.
The NR-divider divides the input frequency OSCIN by 1 or 2 to generate the PLL internal
clock INTCLK.
INTCLK is multiplied by a programmable value NF to generate an output clock. The
frequency of this output clock must be between 10MHz and 100MHz. The value of NF
ranges from 1 to 15.
The output clock is subsequently divided by an R-divider, which ranges from 1 to 8.
The output of the R-divider is available for use as a clock source for any device clock
domain.