Texas Instruments TMS570LS User manual

Application Report
Lit. Number –Month Year
1
Getting Started With TMS570LS Microcontrollers
Sunil Oak AEC-Automotive Microcontrollers
ABSTRACT
This application report provides a brief overview of the TMS570LS series of microcontrollers. It
describes the initialization procedure for the TMS570LS series of microcontrollers. The
document also shows code fragments from source files that are generated using the HALCoGen
tool. All code constructs used in this document are also defined in header files also generated by
the same utility.
Contents
1Block Diagram.................................................................................................................................3
2Overview of Features......................................................................................................................4
3Standard Initialization Sequence for TMS570LS Microcontrollers.............................................7
3.1 Enabling Floating Point Coprocessor (FPU) .............................................................................8
3.2 Initialization of Cortex-R4F Registers........................................................................................9
3.3 Initialize stack pointers for all CPU operating modes..............................................................11
3.4 Enable the Cortex-R4F CPU‟s Vectored Interrupt Controller (VIC) Port .................................12
3.5 Configure Flash Access ..........................................................................................................13
3.6 Configure flash bank and pump power modes........................................................................14
3.7 Configure PLLs........................................................................................................................17
3.7.1 FMzPLL.......................................................................................................................17
3.7.2 FPLL............................................................................................................................20
3.8 Enable Clock Sources.............................................................................................................22
3.8.1 Available Clock Sources on TMS570LS Microcontrollers ...........................................22
3.8.2 Control Registers for Enabling and Disabling Clock Sources......................................23
3.8.3 Example Clock Source Configuration..........................................................................24
3.9 Clock Domains........................................................................................................................25
3.9.1 Mapping Clock Domains to Clock Sources .................................................................26
3.9.2 Example Clock Domain Mapping ................................................................................27
3.9.3 Configuring VCLK and VCLK2 Frequencies................................................................27
3.10 Run CPU Self-Test..................................................................................................................29
3.11 Release Reset and Clocks to Peripherals...............................................................................30
3.12 Memories‟ Self-Test ................................................................................................................31
3.13 Memories‟ Auto-Initialization ...................................................................................................32
3.14 Vectored Interrupt Manager Configuration..............................................................................34
3.14.1 Example VIM RAM Configuration................................................................................34
3.14.2 Configure Interrupts to be Fast Interrupts or Normal Interrupts...................................36
3.14.3 Enabling Interrupts ......................................................................................................36
3.15 Additional Initializations Required by Compiler .......................................................................39
3.16 Call the Main Application.........................................................................................................39

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2Getting Started With TMS570LS Microcontrollers
Figures
Figure 1. Device Block Diagram........................................................................................................3
Figure 2. Flash Read Control Register: FRDCNTL, Address = 0xFFF87000...............................13
Figure 3. Flash Bank Fall-Back Control Register: FBFALLBACK, Address = 0xFFF87040 ......14
Figure 4. Flash Bank Access Control Register: FBAC, Address = 0xFFF8703C........................15
Figure 5. Flash Pump Access Control Register 1: FPAC1, Address = 0xFFF87048 ..................16
Figure 6. Flash Pump Access Control Register 2: FPAC2, Address = 0xFFF8704C..................16
Figure 7. FMzPLL Block Diagram ...................................................................................................17
Figure 8. PLL Control Register 1: PLLCTL1, Address = 0xFFFFFF70.........................................18
Figure 9. PLL Control Register 2: PLLCTL2, Address = 0xFFFFFF74.........................................19
Figure 10. FPLL Block Diagram ........................................................................................................20
Figure 11. PLL Control Register 3: PLLCTL3, Address = 0xFFFFE100.........................................21
Figure 12. Clock Source Disable Register: CSDIS, Address = 0xFFFFFF30 ................................23
Figure 13. Clock Source Disable Set Register: CSDISSET, Address = 0xFFFFFF34...................23
Figure 14. Clock Source Disable Clear Register: CSDISCLR, Address = 0xFFFFFF38...............24
Figure 15. GCLK, HCLK , VCLKx Source Register: GHVSRC, Address = 0xFFFFFF48...............26
Figure 16. Asynchronous Clock Source Register: VCLKASRC, Address = 0xFFFFFF4C ..........26
Figure 17. RTI Clock Source Register: RCLKSRC, Address = 0xFFFFFF50.................................27
Figure 18. Peripheral Clock Control Register: CLKCNTL, Address = 0xFFFFFFD0 ....................28
Figure 19. Memory Hardware Initialization Global Control Register: MINITGCR, Address =
0xFFFFFF5C......................................................................................................................32
Figure 20. Memory Self-Test / Initialization Control Register: MSIENA, Address = 0xFFFFFF6032
Figure 21. Memory Self-Test / Initialization Status Register: MSTCGSTAT, Address =
0xFFFFFF68......................................................................................................................33
Figure 22. VIM Interrupt Address Memory Map...............................................................................34
Figure 23. FIQ/IRQ Control Register 0: FIRQPR0, Address = 0xFFFFFE10 ..................................36
Figure 24. FIQ/IRQ Control Register 1: FIRQPR1, Address = 0xFFFFFE14 ..................................36
Figure 25. Interrupt Enable Set Register 0: REQENASET0, Address = 0xFFFFFE30 ..................37
Figure 26. Interrupt Enable Set Register 1: REQENASET1, Address = 0xFFFFFE34 ..................37
Figure 27. Interrupt Enable Clear Register 0: REQENACLR0, Address = 0xFFFFFE40...............37
Figure 28. Interrupt Enable Clear Register 1: REQENACLR1, Address = 0xFFFFFE44...............38
Tables
Table 1. Clock Sources on TMS570LS Microcontrollers.............................................................22
Table 2. Clock Domains on TMS570LS Microcontrollers............................................................25

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Getting Started With TMS570LS Microcontrollers 3
1Block Diagram
Figure 1 shows a high-level block diagram of the TMS570LS series microcontroller.
Figure 1. Device Block Diagram
Flash
2.0MB
with ECC
CRC
OSC
NHET
SYS
LIN2
MiBSPI1
DCAN1
OSCIN
OSCOUT
TRST
TMS
TCK
TDI
TDO
RST
PORRST
TEST
NHET[31:0]
LIN2RX
LIN2TX
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1CLK
MIBSPI1SCS[3:0]
CAN1RX
CAN1TX
FLTP1
ECLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI3CLK
DCAN2 CAN2RX
CAN2TX
128 Words
128 Buffers
MIBSPI3SCS[3:0]
VIM
HET TU
8DCP
64 Messages
64 Messages
DMA
16 Channels
Primary SCR
ETM
ETMTRACECTL
ETMTRACECLKOUT CCM-R4
RTP
DMM
RTCK
RTPDATA[15:0]
RTPSYNC
RTPCLK
1Port
MIBSPI1ENA
with Parity
with Parity
with Parity
with Parity
VCCP1
withParity
withMPU
ETMDATA[31:0]
MIBSPI3ENA
FLTP2
with MPU
RTPENA
8 Transfer
Groups
64 Channel
withParity
2Channel
Clock
Monitor
MiBSPI3
128 Buffers
with Parity
8 Transfer
Groups
Flexray
8k Byte
with Parity
FRAYRX1
FRAYTX1
FRAYTXEN1
FRAYRX2
FRAYTX2
FRAYTXEN2
DCAN3 CAN3RX
CAN3TX32 Messages
with Parity
RAM
160kB
with ECC
FMzPLL
Kelvin_GND
DAP
DMMENA
DMMSYNC
DMMCLK
DMMDATA[1:0] withParity
Periph Bridge
Cortex-R4F
Msg RAM
Flexray
with MPU
withParity
RTI
SCR
2
TU
SCR
1
Note:
Priorities
SCR2 : round robin
SCR : round robin
SCR1 : 1=DMA, 2=DMM, 3=DAP
DMMDATA[15:2]*
MiBADC2
64 Words
with Parity
AD2IN[7:0]
AD2EVT
MiBSPIP5 MIBSPI5SIMO[3:0]*
MIBSPI5SOMI[3:0]*
MIBSPI5CLK*
MIBSPI5SCS[3:0]*
MIBSPI5ENA*
128 Buffers
with Parity
8 Transfer
Groups
32 Regions
with DMMDATA[15:2] pins
64 Words
with
ICEPick
2RAMblocks
ESM
ERROR
MiBADC1
64 Words
withParity
AD1IN[7:0]
VSSAD
ADREFHI
ADREFLO
AD1EVT
12Bit 12Bit
with MPU
Cortex-R4F
with MPU
GIO GIOA[7:0] /INT[7:0]
GIOB[7:0]
LIN1 LIN1RX
LIN1TX
STC
LBIST
EMIFADD[21:0]
EMIFDATA[15:0]
EMIFCS[3:0]
EMIFWE
EMIFOE
EMIF
EMIFBADD[1:0]
VCCAD
ADSIN[15:8]
P
O
M
*MIBSPIP5 pins are multiplexed
ETMTRACECLKIN
EMIFDQM[1:0]
SCR
PCR
FPLL
for Flexray
VMON
VccIO
Vcc

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4Getting Started With TMS570LS Microcontrollers
2Overview of Features
The TMS570LS series is a high-performance microcontroller family which has been certified for
use in IEC 61508 SIL3 safety systems.
The microcontrollers included in the TMS570LS Series are:
–TMS570LS20216
–TMS570LS20206
–TMS570LS10216
–TMS570LS10206
–TMS570LS10116
–TMS570LS10106
TMS570LS Series microcontrollers contain the following:
Dual ARM Cortex™-R4F processors operating in lock-step
–1.6 DMIPS/MHz
–CPU clock speeds up to 160MHz, providing up to 250 DMIPS
–Big-Endian
–Core-Compare Module (CCM-R4) to monitor lock-step operation
–Supports Built-In Self-Test (BIST)
Integrated Memory
–Up to 2MB Flash Memory
Non-volatile, electrically-erasable and programmable with 64-bit data bus interface
Single 3.3V supply needed for all read, program and erase operations
Connected to Tightly-Coupled Memory interface (TCM A) of the Cortex™-R4F CPU
Protects accesses with ECC (Single Error Correction Double Error Detection) logic
Supports accesses up to 160MHz in pipelined mode
–Up to 160KB SRAM
Supports single-cycle accesses at the maximum specified clock speed
Allows read/write accesses in byte, half-word (16 bits), and word (32 bits) sizes
Protects accesses with ECC (Single Error Correction Double Error Detection) logic
External Memory Interface (EMIF)
–Provides 8- or 16-bit interface to external asynchronous memories, 22 address lines
–Supports up to 4 chip selects
–Each chip select can address up to 32MB in 16-bit mode or 16MB in 8-bit mode

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Getting Started With TMS570LS Microcontrollers 5
TMS570 High-Performance Architecture for Safety-Critical Applications
–Consistent memory map across entire microcontroller family
–Real-Time Interrupt (RTI) for use as OS timer
Up to 6 configurable periodic interrupts
–Vectored Interrupt Manager (VIM)
Supports vectored interrupt controller (NVIC) port on the Cortex™-R4F CPU
Reduces interrupt latency even if NVIC port is not used
–2-Channel Cyclic Redundancy Checker (CRC)
Allows integrity checks for memories
Direct Memory Access (DMA) controller
–16 channels
–32 hardware requests configured by control packets
–Control packet information protected by parity error detection
–Built-in Memory Protection Unit (MPU) dedicated to prevent erroneous DMA transfers
Enhanced High-End Timer (NHET)
–Programmable timer coprocessor with its own assembly microcode
–128-word instruction memory with parity protection
–32 programmable channels for output compare or input capture functions
–Unused channels can be used as general-purpose I/O signals
–Dedicated transfer unit (HTU) with 8 programmable transfer configurations
–Control packet information protected by parity error detection
–Built-in Memory Protection Unit (MPU) dedicated to prevent erroneous HTU transfers
Analog-to-Digital Converters (ADC)
–Two 12-bit-resolution Successive Approximation Resistor A2D converters
–Dedicated memory to store up to 64 conversion results, with parity protection
–24 total input channels, 8 shared channels
Communication Modules
–Dual-channel FlexRay™ Controller
8 KB message RAM with parity protection
Dedicated transfer unit (FTU)
Parity protection for transfer unit configuration memory
Dedicated MPU to protect against erroneous transfers by FTU
–Three Multi-Buffered Serial Peripheral Interface (MibSPI) Controllers

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6Getting Started With TMS570LS Microcontrollers
4 chip selects and 1 enable for each MibSPI
128 transmit and receive buffers with parity protection for each MibSPI
One MibSPI supports unique parallel interface mode with up to 4-bit data
–Two Local Interconnect Network (LIN) Interface Controllers
Compliant to LIN specification version 2.0
Support the standard Serial Communication Interface (SCI) mode
–Three Controller Area Network (CAN) Controllers
Two controllers with 64 mailboxes, one controller with 32 mailboxes
Parity protection for mailbox memory
Trace and Calibration Interfaces
–Embedded Trace Macrocell (ETM-R4) for Cortex™-R4F
Provides trace for instruction and data accesses by the Cortex™-R4F CPU
–Parameter Overlay Module (POM)
Re-routes flash accesses to external memory via the EMIF
Allows application to update parameters without re-programming the flash
–Data Modification Module (DMM)
Provides ability to modify data anywhere within the 4GB addressable space
–RAM Trace Port (RTP)
Provides a high-speed trace of RAM accesses

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Getting Started With TMS570LS Microcontrollers 7
3Standard Initialization Sequence for TMS570LS Microcontrollers
A typical basic sequence to be followed for initialization and configuration of key features on the
TMS570LS Series microcontrollers is summarized below and detailed in the following sections.
This is not a mandatory sequence. Applications that are non-safety-critical can choose to not
use the ECC feature for flash and RAM accesses, for example.
Enable the Floating Point Unit (FPU) inside the Cortex-R4F CPU
Initialize the CPU registers and FPU registers
Initialize stack pointers for all operating modes
Enable CPU‟s dedicated vectored interrupt controller (VIC) port
Set up flash wrapper for required wait states and pipelined mode
Set up flash bank and pump power modes
Configure PLL control registers
Enable desired clock sources
Map device clock domains to desired clock sources
Run the Built-In Self-Test for the CPU
Release peripherals from reset and enable clocks to all peripherals
Run self-tests on all device memories using Programmable Built-In Self-test (PBIST)
Perform auto-initialization for all on-chip SRAMs
Program Vectored Interrupt Manager memory to map all interrupt service routine addresses
Configure IRQ / FIQ interrupt priorities for all interrupt channels
Enable the desired interrupts
Initialize copy table, global variables, and constructors
Call the main application
The following sections describe each of the above steps in more detail. Code examples are also
provided.

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8Getting Started With TMS570LS Microcontrollers
3.1 Enabling Floating Point Coprocessor (FPU)
The floating point coprocessor is disabled upon a CPU reset and must be enabled.
First access to the FPU must be enabled.
MRC p15, #0x0, r0, c1, c0, #2
MOV r3, #0xf00000
ORR r0, r0, r3
MCR p15, #0x0, r0, c1, c0, #2
MRC p15, #0x0, r0, c0, c0
Enable the FPU
MOV r0, #0x40000000
FMXR FPEXC, r0

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Getting Started With TMS570LS Microcontrollers 9
3.2 Initialization of Cortex-R4F Registers
The TMS570LS series of microcontrollers include dual Cortex-R4F CPUs running in a lock-step
operation mode. A Core Compare Module (CCM-R4) compares the output signals from each
R4F CPU. Any difference in the two CPUs‟ outputs is flagged as a fault of a high severity level.
The CPU internal core registers need to be initialized to a predefined state in order to prevent an
error from being flagged during system initialization.
Initialize CPU registers R0 through R12
mov r0, lr
mov r1, #0x03D0
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
Initialize CPU banked registers
orr r13, r1, #0x0001
msr cpsr_cxsf, r13
msr spsr_cxsf, r13
mov lr, r0
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
orr r13, r1, #0x0002
msr cpsr_c, r13
msr spsr_cxsf, r13
mov lr, r0
orr r13, r1, #0x0007
msr cpsr_c, r13
msr spsr_cxsf, r13
mov lr, r0
orr r13, r1, #0x000B
msr cpsr_c, r13
msr spsr_cxsf, r13
mov lr, r0
orr r13, r1, #0x0003
msr cpsr_c, r13
msr spsr_cxsf, r13

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10 Getting Started With TMS570LS Microcontrollers
Initialize the FPU registers
fmdrr d0, r1, r1
fmdrr d1, r1, r1
fmdrr d2, r1, r1
fmdrr d3, r1, r1
fmdrr d4, r1, r1
fmdrr d5, r1, r1
fmdrr d6, r1, r1
fmdrr d7, r1, r1
fmdrr d8, r1, r1
fmdrr d9, r1, r1
fmdrr d10, r1, r1
fmdrr d11, r1, r1
fmdrr d12, r1, r1
fmdrr d13, r1, r1
fmdrr d14, r1, r1
fmdrr d15, r1, r1
Initialize CPU return stack
bl $+4
bl $+4
bl $+4
bl $+4
bx r0