Texas Instruments C2620 Product manual

CC26xx SimpleLink™ Wireless MCU
Technical Reference Manual
Literature Number: SWCU117A
February 2015–Revised March 2015

Contents
Revision History.......................................................................................................................... 10
Preface....................................................................................................................................... 11
1 Architectural Overview........................................................................................................ 13
1.1 Target Applications......................................................................................................... 14
1.2 Overview..................................................................................................................... 14
1.3 Functional Overview ....................................................................................................... 17
1.3.1 ARM Cortex-M3 ................................................................................................... 17
1.3.2 On-Chip Memory .................................................................................................. 18
1.3.3 Radio................................................................................................................ 19
1.3.4 AES Engine With 128-Bit Key Support......................................................................... 19
1.3.5 General-Purpose Timers ......................................................................................... 20
1.3.6 Direct Memory Access............................................................................................ 20
1.3.7 System Control and Clock ....................................................................................... 21
1.3.8 Serial Communications Peripherals............................................................................. 21
1.3.9 Programmable IOs................................................................................................ 24
1.3.10 Sensor Controller ................................................................................................ 24
1.3.11 Random Number Generator .................................................................................... 25
1.3.12 cJTAG and JTAG ................................................................................................ 25
1.3.13 Power Supply System ........................................................................................... 25
2 The Cortex-M3 Processor.................................................................................................... 28
2.1 The Cortex-M3 Processor Introduction.................................................................................. 29
2.2 Block Diagram .............................................................................................................. 29
2.3 Overview..................................................................................................................... 30
2.3.1 System-Level Interface ........................................................................................... 30
2.3.2 Integrated Configurable Debug.................................................................................. 30
2.3.3 Trace Port Interface Unit ......................................................................................... 31
2.3.4 Cortex-M3 System Component Details......................................................................... 31
2.4 Programming Model ....................................................................................................... 31
2.4.1 Processor Mode and Privilege Levels for Software Execution.............................................. 32
2.4.2 Stacks............................................................................................................... 32
2.4.3 Exceptions and Interrupts........................................................................................ 32
2.4.4 Data Types......................................................................................................... 32
2.5 Coretex-M3 Core Registers............................................................................................... 33
2.5.1 Core Register Map................................................................................................ 34
2.5.2 Core Register Descriptions ...................................................................................... 34
2.6 Instruction Set Summary .................................................................................................. 47
2.7 Cortex-M3 Processor Registers.......................................................................................... 50
2.7.1 CPU_ITM Registers............................................................................................... 51
2.7.2 CPU_DWT Registers ............................................................................................. 92
2.7.3 CPU_FPB Registers............................................................................................. 117
2.7.4 CPU_SCS Registers ............................................................................................ 129
2.7.5 CPU_TPIU Registers............................................................................................ 207
3 Cortex™-M3 Peripherals.................................................................................................... 220
3.1 Cortex™-M3 Peripherals Introduction.................................................................................. 221
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3.2 Functional Description.................................................................................................... 221
3.2.1 SysTick............................................................................................................ 221
3.2.2 NVIC............................................................................................................... 222
3.2.3 System Control Block (SCB) ................................................................................... 223
3.2.4 Instrumentation Trace Macrocell Unit (ITM).................................................................. 223
3.2.5 Flash Patch and Breakpoint Unit (FPB) ...................................................................... 223
3.2.6 Trace Port Interface Unit (TPIU)............................................................................... 224
3.2.7 Data Watchpoint and Trace Unit (DWT)...................................................................... 224
4 Interrupts and Events........................................................................................................ 227
4.1 Exception Model .......................................................................................................... 228
4.1.1 Exception States................................................................................................. 228
4.1.2 Exception Types ................................................................................................. 228
4.1.3 Exception Handlers.............................................................................................. 231
4.1.4 Vector Table...................................................................................................... 231
4.1.5 Exception Priorities .............................................................................................. 232
4.1.6 Interrupt Priority Grouping ...................................................................................... 232
4.1.7 Exception Entry and Return .................................................................................... 233
4.2 Fault Handling............................................................................................................. 235
4.2.1 Fault Types ....................................................................................................... 235
4.2.2 Fault Escalation and Hard Faults.............................................................................. 236
4.2.3 Fault Status Registers and Fault Address Registers........................................................ 236
4.2.4 Lockup............................................................................................................. 236
4.3 Event Fabric............................................................................................................... 237
4.3.1 Introduction ....................................................................................................... 237
4.3.2 Event Fabric Overview.......................................................................................... 238
4.4 AON Event Fabric ........................................................................................................ 238
4.4.1 Common Input Event List....................................................................................... 239
4.4.2 Event Subscribers ............................................................................................... 239
4.5 MCU Event Fabric ........................................................................................................ 240
4.5.1 Common Input Event List....................................................................................... 241
4.5.2 Event Subscribers ............................................................................................... 244
4.6 Interrupts and Events Registers ........................................................................................ 245
4.6.1 AON_EVENT Registers......................................................................................... 246
4.6.2 EVENT Registers................................................................................................ 270
5 JTAG Interface ................................................................................................................. 389
5.1 Top Level Debug System................................................................................................ 390
5.2 cJTAG...................................................................................................................... 392
5.2.1 JTAG Commands................................................................................................ 394
5.2.2 Programming Sequences....................................................................................... 396
5.3 ICEPick™.................................................................................................................. 397
5.3.1 Secondary TAPs................................................................................................. 397
5.3.2 ICEPick™ Registers............................................................................................. 399
5.3.3 ROUTER Scan Chain........................................................................................... 402
5.3.4 TAP Routing Registers ......................................................................................... 403
5.4 ICEMelter™................................................................................................................ 408
5.5 Serial Wire Viewer (SWV) ............................................................................................... 408
5.6 Halt In Boot (HIB)......................................................................................................... 408
5.7 Debug and Shutdown .................................................................................................... 409
5.8 Debug Features Supported Through WUC TAP ..................................................................... 409
5.9 Profiler Register........................................................................................................... 409
6 Power, Reset, and Clock Management................................................................................. 411
6.1 Introduction ................................................................................................................ 412
6.1.1 System CPU Mode .............................................................................................. 413
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6.1.2 Supply System ................................................................................................... 413
6.1.3 Digital Power Partitioning....................................................................................... 415
6.1.4 Clock Management.............................................................................................. 417
6.1.5 Power Modes..................................................................................................... 422
6.1.6 Reset .............................................................................................................. 426
6.2 PRCM Registers .......................................................................................................... 427
6.2.1 PRCM Registers ................................................................................................. 428
6.2.2 AON_SYSCTL Registers ....................................................................................... 488
6.2.3 AON_WUC Registers ........................................................................................... 493
6.2.4 DDI_0_OSC Registers.......................................................................................... 509
7 Versatile Instruction Memory System (VIMS)........................................................................ 529
7.1 VIMS Configurations ..................................................................................................... 531
7.1.1 VIMS Modes...................................................................................................... 531
7.1.2 VIMS Flash Line Buffering...................................................................................... 534
7.1.3 VIMS Arbitration.................................................................................................. 534
7.1.4 VIMS Cache TAG Prefetch..................................................................................... 534
7.2 VIMS Software (SW) Remarks.......................................................................................... 534
7.2.1 Flash Program or Update....................................................................................... 534
7.2.2 VIMS Retention .................................................................................................. 534
7.3 VIMS Registers ........................................................................................................... 537
7.3.1 STAT Register (Offset = 0h) [reset = X] ...................................................................... 538
7.3.2 CTL Register (Offset = 4h) [reset = X]........................................................................ 539
7.4 ROM........................................................................................................................ 540
7.5 EEFUSE ................................................................................................................... 540
7.6 FLASH...................................................................................................................... 540
7.6.1 FLASH Memory Protection..................................................................................... 540
7.6.2 Memory Programming .......................................................................................... 540
7.6.3 FLASH Memory Programming................................................................................. 541
7.6.4 FLASH Read Timings .......................................................................................... 541
7.6.5 Power Mode Operations........................................................................................ 541
7.7 VIMS Registers ........................................................................................................... 541
7.7.1 FLASHMEM Registers.......................................................................................... 542
7.7.2 FLASH Registers ................................................................................................ 543
7.8 ROM Functions ........................................................................................................... 669
7.9 SRAM ...................................................................................................................... 670
8 Bootloader....................................................................................................................... 671
8.1 Bootloader Functionality ................................................................................................. 672
8.1.1 Bootloader Disabling ............................................................................................ 672
8.1.2 Bootloader Backdoor............................................................................................ 672
8.2 Bootloader Interfaces..................................................................................................... 672
8.2.1 Packet Handling.................................................................................................. 673
8.2.2 Transport Layer .................................................................................................. 674
8.2.3 Serial Bus Commands .......................................................................................... 676
9 Device Configuration......................................................................................................... 685
9.1 Customer Configuration (CCFG) ....................................................................................... 686
9.1.1 CCFG Registers ................................................................................................. 687
9.2 Factory Configuration (FCFG) .......................................................................................... 713
9.2.1 FCFG1 Registers ................................................................................................ 714
10 Cryptography ................................................................................................................... 797
10.1 AES Cryptoprocessor Overview ........................................................................................ 798
10.1.1 Functional Description ......................................................................................... 798
10.1.2 Power Management and Sleep Modes ...................................................................... 799
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10.1.3 Hardware Description .......................................................................................... 799
10.1.4 Module Description............................................................................................. 800
10.1.5 Performance..................................................................................................... 810
10.1.6 Programming Guidelines ...................................................................................... 811
10.1.7 Conventions and Compliances ............................................................................... 820
10.2 Cryptography Registers.................................................................................................. 822
10.2.1 CRYPTO Registers............................................................................................. 823
11 I/O Control ....................................................................................................................... 867
11.1 Introduction ................................................................................................................ 868
11.2 IOC Overview ............................................................................................................. 868
11.3 I/O Mapping and Configuration ......................................................................................... 869
11.3.1 Basic I/O Mapping.............................................................................................. 869
11.3.2 MAP AUXIO from the Sensor Controller to DIO Pin ....................................................... 869
11.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN......................................................... 870
11.4 Edge Detection on Pin (DIO)............................................................................................ 870
11.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT............................... 870
11.5 AON IOC State Latching When Powering Off the MCU Domain .................................................. 870
11.6 Unused I/O Pins........................................................................................................... 871
11.7 GPIO........................................................................................................................ 871
11.8 I/O Pin Mapping........................................................................................................... 872
11.9 Peripheral PORTIDs...................................................................................................... 873
11.10 I/O Pin...................................................................................................................... 873
11.10.1 Physical Pin.................................................................................................... 873
11.10.2 Pin Configuration.............................................................................................. 874
11.11 I/O Control Registers..................................................................................................... 875
11.11.1 AON_IOC Registers .......................................................................................... 876
11.11.2 IOC Registers.................................................................................................. 883
11.11.3 GPIO Registers .............................................................................................. 1012
12 Micro Direct Memory Access (µDMA) ................................................................................ 1035
12.1 μDMA Introduction ...................................................................................................... 1036
12.2 Block Diagram ........................................................................................................... 1036
12.3 Functional Description.................................................................................................. 1037
12.3.1 Channel Assignments ........................................................................................ 1037
12.3.2 Priority .......................................................................................................... 1039
12.3.3 Arbitration Size ................................................................................................ 1039
12.3.4 Request Types ................................................................................................ 1039
12.3.5 Channel Configuration........................................................................................ 1040
12.3.6 Transfer Modes................................................................................................ 1041
12.3.7 Transfer Size and Increments ............................................................................... 1050
12.3.8 Peripheral Interface........................................................................................... 1050
12.3.9 Software Request ............................................................................................. 1050
12.3.10 Interrupts and Errors ........................................................................................ 1051
12.4 Initialization and Configuration......................................................................................... 1051
12.4.1 Module Initialization........................................................................................... 1051
12.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 1052
12.4.3 Configuring Channel Assignments.......................................................................... 1052
12.5 µDMA Registers......................................................................................................... 1052
12.5.1 UDMA Registers............................................................................................... 1053
13 Timers ........................................................................................................................... 1073
13.1 General-Purpose Timers ............................................................................................... 1074
13.2 Block Diagram ........................................................................................................... 1074
13.3 Functional Description.................................................................................................. 1075
13.3.1 GPTM Reset Conditions ..................................................................................... 1076
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13.3.2 Timer Modes................................................................................................... 1076
13.3.3 Wait-for-Trigger Mode ........................................................................................ 1083
13.3.4 Synchronizing GP Timer Blocks............................................................................. 1083
13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values ...................................... 1084
13.4 Initialization and Configuration......................................................................................... 1084
13.4.1 One-Shot and Periodic Timer Modes....................................................................... 1084
13.4.2 Input Edge-Count Mode...................................................................................... 1085
13.4.3 Input Edge-Timing Mode..................................................................................... 1085
13.4.4 PWM Mode..................................................................................................... 1086
13.4.5 Producing DMA Trigger ...................................................................................... 1086
13.5 General-Purpose Timer Registers .................................................................................... 1086
13.5.1 GPT Registers................................................................................................. 1087
14 Real-Time Clock.............................................................................................................. 1124
14.1 Introduction............................................................................................................... 1125
14.2 Functional Specifications............................................................................................... 1125
14.2.1 Functional Overview .......................................................................................... 1125
14.2.2 Free-Running Counter........................................................................................ 1125
14.2.3 Channels ....................................................................................................... 1125
14.2.4 Events .......................................................................................................... 1126
14.3 RTC Registers........................................................................................................... 1126
14.3.1 Register Access ............................................................................................... 1126
14.3.2 Entering and Wakeup From Sleep ......................................................................... 1127
14.3.3 [AON_RTC:SYNC] Register ................................................................................. 1127
14.4 Real-Time Clock Registers............................................................................................. 1127
14.4.1 AON_RTC Registers.......................................................................................... 1128
15 Watchdog Timer.............................................................................................................. 1142
15.1 WDT Introduction........................................................................................................ 1143
15.2 WDT Functional Description........................................................................................... 1143
15.3 WDT Initialization and Configuration.................................................................................. 1144
15.4 Watchdog Timer Registers............................................................................................. 1144
15.4.1 WDT Registers ................................................................................................ 1145
16 Random Number Generator.............................................................................................. 1155
16.1 Overview.................................................................................................................. 1156
16.2 Block Diagram ........................................................................................................... 1156
16.3 TRNG Software Reset.................................................................................................. 1157
16.4 Interrupt Requests....................................................................................................... 1157
16.5 TRNG Operation Description .......................................................................................... 1158
16.5.1 TRNG Shutdown .............................................................................................. 1158
16.5.2 TRNG Alarms.................................................................................................. 1159
16.5.3 TRNG Entropy................................................................................................. 1159
16.6 TRNG Low-level Programing Guide .................................................................................. 1160
16.6.1 Initialization..................................................................................................... 1160
16.7 Random Number Generator ........................................................................................... 1162
16.7.1 TRNG Registers............................................................................................... 1163
17 AUX – Sensor Controller with Digital and Analog Peripherals .............................................. 1186
17.1 Introduction............................................................................................................... 1187
17.1.1 AUX Hardware Overview..................................................................................... 1188
17.2 Memory Mapping........................................................................................................ 1189
17.2.1 Alias of Commonly Used Registers......................................................................... 1189
17.3 IO Mapping............................................................................................................... 1191
17.4 Modules................................................................................................................... 1191
17.4.1 Sensor Controller.............................................................................................. 1191
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17.4.2 GPIO Control .................................................................................................. 1200
17.4.3 AUX Timers.................................................................................................... 1203
17.4.4 Time-to-Digital Converter..................................................................................... 1203
17.4.5 Semaphores ................................................................................................... 1204
17.4.6 Oscillator Configuration Interface (DDI).................................................................... 1204
17.4.7 Analog Configuration Interface (ADI)....................................................................... 1204
17.4.8 Analog MUX ................................................................................................... 1205
17.4.9 ADC............................................................................................................. 1205
17.4.10 Comparators.................................................................................................. 1208
17.4.11 Current source ............................................................................................... 1208
17.5 Power Management..................................................................................................... 1208
17.5.1 Startup.......................................................................................................... 1208
17.5.2 Power Mode Management................................................................................... 1208
17.5.3 Wakeup Events................................................................................................ 1209
17.5.4 MCU Bus Connection......................................................................................... 1210
17.6 Clock Management ..................................................................................................... 1210
17.6.1 System Clocks................................................................................................. 1210
17.6.2 Sensor Controller Clock...................................................................................... 1211
17.6.3 Peripheral Clocks ............................................................................................. 1211
17.7 Use Cases................................................................................................................ 1211
17.7.1 RTC Calibration ............................................................................................... 1211
17.7.2 Capacitive Sensing............................................................................................ 1211
17.7.3 Pulse Counting ................................................................................................ 1211
17.8 AUX – Sensor Controller Registers................................................................................... 1211
17.8.1 AUX_AIODIO Registers...................................................................................... 1212
17.8.2 AUX_TDC Registers.......................................................................................... 1221
17.8.3 AUX_EVCTL Registers....................................................................................... 1235
17.8.4 AON_WUC Registers......................................................................................... 1257
17.8.5 AUX_TIMER Registers....................................................................................... 1273
17.8.6 AUX_SMPH Registers........................................................................................ 1282
17.8.7 AUX_ANAIF Registers ....................................................................................... 1292
17.8.8 ADI_4_AUX Registers........................................................................................ 1299
18 Battery Monitor and Temperature Sensor........................................................................... 1311
18.1 Introduction............................................................................................................... 1312
18.2 Functional Description.................................................................................................. 1312
18.3 BATMON Registers..................................................................................................... 1312
18.3.1 AON_BATMON Registers.................................................................................... 1313
19 Universal Asynchronous Receivers and Transmitters (UARTS) ............................................ 1327
19.1 Universal Asynchronous Receiver/Transmitter...................................................................... 1328
19.2 Block Diagram ........................................................................................................... 1329
19.3 Signal Description....................................................................................................... 1329
19.4 Functional Description.................................................................................................. 1329
19.4.1 Transmit and Receive Logic................................................................................. 1330
19.4.2 Baud-Rate Generation........................................................................................ 1330
19.4.3 Data Transmission ............................................................................................ 1330
19.4.4 Modem Handshake Support................................................................................. 1331
19.4.5 FIFO Operation................................................................................................ 1332
19.4.6 Interrupts ....................................................................................................... 1332
19.4.7 Loopback Operation .......................................................................................... 1333
19.5 Interface to DMA ........................................................................................................ 1333
19.6 Initialization and Configuration......................................................................................... 1334
19.7 UARTS Registers ....................................................................................................... 1335
19.7.1 UART Registers ............................................................................................... 1336
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20 Synchronous Serial Interface (SSI).................................................................................... 1353
20.1 Synchronous Serial Interface.......................................................................................... 1354
20.2 Block Diagram ........................................................................................................... 1355
20.3 Signal Description....................................................................................................... 1356
20.4 Functional Description.................................................................................................. 1356
20.4.1 Bit Rate Generation........................................................................................... 1356
20.4.2 FIFO Operation................................................................................................ 1356
20.4.3 Interrupts ....................................................................................................... 1357
20.4.4 Frame Formats ................................................................................................ 1358
20.5 DMA Operation .......................................................................................................... 1364
20.6 Initialization and Configuration......................................................................................... 1365
20.7 SSI Registers ............................................................................................................ 1366
20.7.1 SSI Registers .................................................................................................. 1367
21 Inter-Integrated Circuit (I2C) Interface ................................................................................ 1378
21.1 Inter-Integrated Circuit Interface....................................................................................... 1379
21.2 Block Diagram ........................................................................................................... 1379
21.3 Functional Description.................................................................................................. 1379
21.3.1 I2C Bus Functional Overview ................................................................................ 1380
21.3.2 Available Speed Modes ...................................................................................... 1382
21.3.3 Interrupts ....................................................................................................... 1382
21.3.4 Loopback Operation .......................................................................................... 1383
21.3.5 Command Sequence Flow Charts.......................................................................... 1383
21.4 Initialization and Configuration......................................................................................... 1391
21.5 I2C Registers............................................................................................................. 1391
21.5.1 I2C Registers .................................................................................................. 1392
22 Integrated Interchip Sound (I2S) Module............................................................................ 1411
22.1 Introduction .............................................................................................................. 1412
22.2 Digital Audio Interface .................................................................................................. 1412
22.3 Frame Configuration .................................................................................................... 1413
22.4 Pin Configuration........................................................................................................ 1413
22.5 Clock Configuration ..................................................................................................... 1413
22.5.1 WCLK, BCLK, and MCLK Division Ratio................................................................... 1414
22.6 Serial Interface Formats................................................................................................ 1414
22.6.1 I2S............................................................................................................... 1414
22.6.2 Left Justified (LJF) ............................................................................................ 1415
22.6.3 Right Justified (RJF) .......................................................................................... 1415
22.6.4 DSP ............................................................................................................. 1416
22.7 Memory Interface........................................................................................................ 1417
22.7.1 Word Lengths.................................................................................................. 1417
22.7.2 Audio Channels................................................................................................ 1417
22.7.3 Memory Buffers and Pointers................................................................................ 1418
22.8 Samplestamp Generator ............................................................................................... 1418
22.8.1 Counters and Registers ...................................................................................... 1419
22.8.2 Starting Input and Output Pins .............................................................................. 1420
22.8.3 Samplestamp Capturing...................................................................................... 1420
22.9 Usage..................................................................................................................... 1421
22.9.1 Start-up Sequence ............................................................................................ 1421
22.9.2 Termination Sequence ....................................................................................... 1422
22.10 I2S Registers ............................................................................................................ 1422
22.10.1 I2S Registers................................................................................................. 1423
23 Radio............................................................................................................................. 1454
23.1 RF Core................................................................................................................... 1455
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23.1.1 High-Level Description and Overview ...................................................................... 1455
23.2 Radio Doorbell........................................................................................................... 1456
23.2.1 Operational Description ...................................................................................... 1457
23.3 RF Core HAL ............................................................................................................ 1457
23.3.1 Hardware Support............................................................................................. 1457
23.3.2 Firmware Support ............................................................................................. 1457
23.3.3 Command Definitions......................................................................................... 1468
23.3.4 Protocol-Independent Direct and Immediate Commands................................................ 1481
23.3.5 Immediate Commands for Data Queue Manipulation.................................................... 1487
23.4 Data Queue Usage...................................................................................................... 1491
23.4.1 Operations on Data Queues Only Available for Internal Radio CPU Operations..................... 1491
23.4.2 Radio CPU Usage Model .................................................................................... 1493
23.5 IEEE 802.15.4 ........................................................................................................... 1494
23.5.1 IEEE 802.15.4 Commands................................................................................... 1494
23.5.2 Interrupts ....................................................................................................... 1501
23.5.3 Data Handling.................................................................................................. 1501
23.5.4 Radio Operation Commands ................................................................................ 1502
23.5.5 Immediate Commands ....................................................................................... 1514
23.6 Bluetooth Low Energy .................................................................................................. 1515
23.6.1 Bluetooth Low Energy Commands.......................................................................... 1515
23.6.2 Interrupts ....................................................................................................... 1524
23.6.3 Data Handling.................................................................................................. 1524
23.6.4 Radio Operation Command Descriptions.................................................................. 1525
23.6.5 Immediate Commands ....................................................................................... 1546
23.7 Radio Registers.......................................................................................................... 1546
23.7.1 RFC_DBELL Registers....................................................................................... 1547
23.7.2 RFC_PWR Registers ......................................................................................... 1565
23.7.3 RFC_RAT Registers.......................................................................................... 1568
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Revision History
Changes from February 21, 2015 to March 5, 2015 ........................................................................................................ Page
• Changed Functional Description section............................................................................................... 7
• Changed Cortex-M3 Processor registers............................................................................................. 50
• Changed Interrupts and Events registers........................................................................................... 245
• Changed PRCM registers............................................................................................................. 427
• Changed VIMS registers .............................................................................................................. 541
• Changed Device Configuration registers............................................................................................ 686
• Changed Detailed Memory Map table............................................................................................... 800
• Changed Cryptography registers..................................................................................................... 822
• Changed I/O Control registers........................................................................................................ 875
• Updated image. ....................................................................................................................... 1043
• Changed µDMA registers............................................................................................................ 1052
• Changed RTC registers.............................................................................................................. 1127
• Changed Watchdog registers ....................................................................................................... 1144
• Changed Random Number Generator registers.................................................................................. 1162
• Changed AUX – Sensor Controller registers...................................................................................... 1211
• Changed BATMON registers........................................................................................................ 1312
• Changed Functional Description section .......................................................................................... 1327
• Changed UART feature list.......................................................................................................... 1328
• Changed Signals for UART table................................................................................................... 1329
• Changed Functional Description section .......................................................................................... 1329
• Changed Functional Description section .......................................................................................... 1330
• Changed Functional Description section .......................................................................................... 1331
• Changed Functional Description section .......................................................................................... 1332
• Changed Functional Description section .......................................................................................... 1333
• Changed Initialization and Configurations section................................................................................ 1334
• Changed UART registers............................................................................................................ 1335
• Changed SSI Signals table.......................................................................................................... 1356
• Changed SSI registers............................................................................................................... 1366
• Changed I2C registers ............................................................................................................... 1391
• Changed I2S registers ............................................................................................................... 1422
• Changed Radio chapter.............................................................................................................. 1455
• Changed Radio registers ............................................................................................................ 1546
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Preface
SWCU117A–February 2015–Revised March 2015
Read This First
About This Document
This technical reference manual provides information on how to use the CC26xx and the CC13xx
SimpleLink™ ultra-low power wireless microcontroller devices. The CC26xx and the CC13xx families
share the same MCU architecture and most of the peripherals, but the CC13xx radio is designed for use
in the sub-1 GHz frequency bands while the CC26xx radio operates in the 2.4-GHz ISM frequency band.
This document covers the whole family of devices, so please see the individual device data sheet for
supported modules and features.
Audience
This manual is intended for system software developers, hardware designers, and application developers.
About This Manual
This document is organized into sections that correspond to each major feature. It explains the features
and functionality of each module, and explains how to use them. For each feature, references are given to
the corresponding operating systems driver documentation. This document does not contain performance
characteristics of the device or modules. These are gathered in the corresponding device data sheet.
Related Documents
The following related documents are available on the CC26xx product pages at www.ti.com:
• CC2620 Data Sheet and Errata
• CC2630 Data Sheet and Errata
• CC2640 Data Sheet and Errata
• CC2650 Data Sheet and Errata
• CC1310 Data Sheet and Errata
This list of documents was current as of publication date. Check the web site for additional documentation,
including application notes and white papers.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required
to take whatever measures may be required to correct this interference.
11
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Related Documents www.ti.com
Devices
The CC26xx and the CC13xx family of devices includes both 2.4-GHz and Sub-1 GHz radios and a variety
of different memory sizes, peripherals and package options. All devices are centered around an ARM
Cortex-M series processor that handles the application layer and protocol stack, as well as an
autonomous radio core centered around an ARM Cortex-M0 processor that handles all the low-level radio
control and processing. Network processor options are available.
The availability of several a wide range of different radio and MCU system combination makes these
families very well suited for almost any low-power RF node implementation.
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The following link connects to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki – Texas Instruments Embedded Processors Wiki
TI BLE Wiki – Texas Instruments Bluetooth Smart Wiki
Established to assist developers using the many Embedded Processors from TI to get started, help each
other innovate, and foster the growth of general knowledge about the hardware and software surrounding
these devices.
Register, Field, and Bit Calls
The naming convention applied for a call consists of:
• For a register call: <Module name>.<Register name>; for example: UART.UASR
• For a bit field call:
–<Module name>.<Register name>[End:Start] <Field name> field; for example, UART.UASR[4:0]
SPEED bit field
–<Field name> field <Module name>.<Register name>[End:Start]; for example, SPEED bit field
UART.UASR[4:0]
• For a bit call:
–<Module name>.<Register name>[pos] <Bit name> bit; for example, UART.UASR[5]
BIT_BY_CHAR bit
–<Bit name> bit <Module name>.<Register name>[pos]; for example, BIT_BY_CHAR bit
UART.UASR[5]
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Chapter 1
SWCU117A–February 2015–Revised March 2015
Architectural Overview
The CC26xx SimpleLink ultra-low power wireless MCU platforms provide solutions for a wide range of
applications. To help the user develop these applications, this user's guide focuses on the use of the
different building blocks of the devices. For detailed device descriptions, complete feature lists, and
performance numbers, see the data sheet. To provide easy access to relevant information, the following
subsections guide the reader to the different chapters in this guide.
The CC26xx SimpleLink ultra-low power wireless MCU platform system-on-chips (SoCs) are optimized for
ultra low power, while providing fast and capable MCU systems to enable short processing times and high
integration. The combination of an ARM®Cortex®-M3 processing core of up to 48-MHz, flash memory,
and a wide selection of peripherals makes the CC26xx device family ideal for single-chip implementation
or network processor implementations of lower power RF nodes.
Topic ........................................................................................................................... Page
1.1 Target Applications ............................................................................................ 14
1.2 Overview........................................................................................................... 14
1.3 Functional Overview........................................................................................... 17
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Target Applications www.ti.com
1.1 Target Applications
The CC26xx SimpleLink ultra-low power wireless MCU platforms are positioned for low-power wireless
applications such as:
• Consumer electronics
• Mobile phone accessories
• Sports and fitness equipment
• HID applications
• Home and building automation
• Lighting control
• Alarm and security
• Electronic shelf labeling
• Proximity tags
• Medical
• Remote controls
• Wireless sensor networks
1.2 Overview
Figure 1-1 shows the different building blocks of the CC26xx device.
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Figure 1-1. CC26xx Block Diagram
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Overview www.ti.com
The CC26xx devices have the following features:
• ARM Cortex-M3 processor core
– 48-MHz RC oscillator and 24-MHz xtal oscillator with internal doubler
– 32-kHz xtal oscillator, 32-kHz RC oscillator or low-power 24-MHz xtal derivate clock for timing
maintenance while in low-power modes
– ARM Cortex SysTick timer
– Nested vectored interrupt controller (NVIC)
• On-chip memory
– Flash with 8KB of 4-way set-associative cache RAM for speed and low power
– System RAM with configurable retention in 4-KB blocks
• Power management
– Wide supply voltage range
– Efficient on-chip DC-DC converter for reduced power consumption
– High granularity clock gating and power gating of device parts
– Flexible frequency of operation
• Flexible low-power modes allowing low energy consumption in duty cycled applications
• Sensor interface
– Autonomous, intelligent sensor interface that can wake up independently of the main CPU system
to perform sensor readings, collect data, and determine if the main CPU should be woken
– 12-bit analog-to-digital converter (ADC) with eight analog input channels
– Low-power analog comparator
– SPI or I2C master bit-banged
• Advanced serial integration
– Universal asynchronous receiver/transmitter (UART)
– Inter-integrated circuit (I2C) module
– Synchronous serial interface modules (SSIs)
– Audio interface I2S module
• System integration
– Direct memory access (DMA) controller
– Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and
synchronization
– 32-kHz real-time clock (RTC)
– Watchdog timer
– On-chip temperature and supply voltage sensing
– GPIO with normal or high-drive capabilities
– GPIOs with analog capability for ADC and comparator
– Fully flexible digital pin muxing allows use as GPIO or any peripheral function
• IEEE 1149.7 compliant 2-pin cJTAG with legacy 1149.1 JTAG support
• 4-mm × 4-mm, 5-mm × 5-mm, and 7-mm × 7-mm QFN packages
For applications requiring extreme conservation of power, the CC26xx device features a power-
management system to efficiently power down the CC26xx device to a low-power state during extended
periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (a real-time clock
[RTC]), with interrupt and 20KB of RAM with retention in all power modes positions the CC26xx
microcontroller perfectly for battery applications.
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In addition, the CC26xx microcontroller offers the advantages of ARM's widely available development
tools, SoC infrastructure IP applications, and a large user community. Additionally, the microcontroller
uses ARMThumb®-compatible Thumb®-2 instruction set to reduce memory requirements and, thereby,
cost.
TI offers a complete solution to get to market quickly, with evaluation and development boards, white
papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and
distributor network.
1.3 Functional Overview
The following sections provide an overview of the features of the CC26xx microcontroller.
1.3.1 ARM Cortex-M3
The following sections provide an overview of the ARM Cortex-M3 processor core and instruction set, the
integrated system timer (SysTick), and the NVIC.
1.3.1.1 Processor Core
The CC26xx is designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor
provides the core for a high-performance, low-cost platform that meets the needs of minimal memory
implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size, usually associated with 8- and 16-bit devices, typically in the range of
a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling efficient packing of data into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system, and memories
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes
• Compact JTAG interface reduces the number of pins required for debugging
• Ultra-low power consumption with integrated sleep modes
• Up to 48-MHz operation
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1.3.1.2 System Timer (SysTick)
ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-
write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways; for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using system clock 11
• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter
• A simple counter used to measure time to completion and time used
• An internal clock-source control based on missing or meeting durations
1.3.1.3 Nested Vector Interrupt Controller
The CC26xx controller includes the ARM NVIC. The NVIC and Cortex-M3 prioritize and handle all
exceptions in handler mode. The processor state is automatically stored to the stack on an exception and
automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector
is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor supports tail-
chaining, that is, back-to-back interrupts can be performed without the overhead of state saving and
restoration. Software can set eight priority levels on seven exceptions (system handlers) and CC26xx
interrupts.
• Deterministic, fast interrupt processing
– Always 12 cycles, or just 6 cycles with tail-chaining
• External nonmaskable interrupt (NMI) signal available for immediate execution of NMI handler for
safety-critical applications
• Dynamically reprioritizable interrupts
• Exceptional interrupt handling through hardware implementation of required register manipulations
1.3.1.4 System Control Block
The system control block (SCB) provides system implementation information and system control
(configuration, control, and reporting of system exceptions).
1.3.2 On-Chip Memory
The following sections describe the on-chip memory modules.
1.3.2.1 SRAM
The CC26xx provides low leakage on-chip SRAM with optional retention in all power modes. Retention
can be configured per block, and the device contains two blocks of 6KB and two blocks of 4KB.
Additionally, the flash cache RAM can be reconfigured to operate as normal system RAM. Because read-
modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in
the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM
and peripheral space) can use address aliases to access individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.
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1.3.2.2 Flash Memory
The flash block provides an in-circuit, programmable, nonvolatile program memory for the device. The
flash memory is organized as a set of 4-KB pages that can be individually erased. Erasing a block causes
the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In
addition to holding program code and constants, the nonvolatile memory allows the application to save
data that must be preserved so that it is available after restarting the device. Using this feature lets the
user use saved network-specific data to avoid the need for a full start-up and network find-and-join
process.
1.3.2.3 ROM
The ROM is preprogrammed with a boot sequence, device driver functions, low-level protocol stack
components, and a serial bootloader (SPI or UART).
1.3.3 Radio
The CC26xx device family provides a highly integrated low-power 2.4-GHz radio transceiver with support
for multiple modulations and packet formats. The radio subsystem provides an interface between the MCU
and the radio, which makes it possible to issue commands, read status, and automate and sequence radio
events.
1.3.4 AES Engine With 128-Bit Key Support
The security core of the CC26xx features an Advanced Encryption Standard (AES) module with 128-bit
key support, local key storage, and DMA capability.
• CCM, CTR, CBC-MAC, ECB modes of operation
• 118 Mbps throughput
• Secure key storage memory
• Low latency
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1.3.5 General-Purpose Timers
General-purpose timers can be used to count or time external events that drive the timer-input pins. Each
16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer.
The general-purpose timer module (GPTM) contains four 16- or 32-bit GPTM blocks with the following
functional options:
• 16- or 32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM
signal
• Count up or down
• Four 32-bit counters or up to eight 16-bit counters
• Up to eight capture/compare pins
• Up to four PWM pins (one PWM pin per 32-bit timer)
• Daisy-chaining of timer modules allows a single timer to initiate multiple timing events.
• Timer synchronization allows selected timers to start counting on the same clock cycle.
• User-enabled stalling when the microcontroller asserts CPU halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the
interrupt service routine
• Efficient transfers using the µDMA controller
1.3.5.1 Watchdog Timer
The watchdog timer is used to regain control when the system fails because of a software error or an
external device fails to respond properly. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
1.3.5.2 Always-on Domain
The AON domain contains circuitry that is always enabled, except for the shutdown mode (where the
digital supply is off). This domain includes the following:
• The RTC can be used to wake the CC26xx from any state where it is active. The RTC contains three
match registers and one compare register. With software support, the RTC can be used for clock and
calendar operation. The RTC is clocked from the 32-kHz RC oscillator or the 32 kHz crystal oscillator.
• The battery monitor and temperature sensors are accessible by SW. The battery monitor and
temperature sensors provide continuous monitoring of battery state as well as coarse temperature.
1.3.6 Direct Memory Access
The CC26xx microcontroller includes a DMA controller, known as μDMA. The μDMA controller provides a
way to offload data transfer tasks from the Cortex-M3 processor, allowing more efficient use of the
processor and the available bus bandwidth. The μDMA controller can perform transfers between memory
and peripherals. Channels in the μDMA are dedicated for each supported on-chip module and can be
programmed to automatically perform transfers between peripherals and memory, as the peripheral is
ready to transfer more data.
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