Texas Instruments TMDSEVM6678L Product manual

1



TMDSEVM6678LEVM
TechnicalReferenceManual
Version2.01

LiteratureNumber:SPRUH58
RevisedMarch2012




DocumentCopyright
PublicationTitle:
TMDSEVM6678LTechnicalReferenceManualAll
RightsReserved.Reproduction,adaptation,or
translationwithoutpriorwrittenpermissionis
prohibited,exceptasallowedundercopyrightlaws.

2

EVALUATIONBOARD/KIT/MODULE(EVM)WARNINGS,RESTRICTIONSANDDISCLAIMER
NotforDiagnosticUse:ForFeasibilityEvaluationOnlyinLaboratory/Development
Environments
TheEVMmaynotbeusedfordiagnosticpurposes.
ThisEVMisintendedsolelyforevaluationanddevelopmentpurposes.Itisnotintendedfor
useandmaynotbeusedasall,orpartofanendequipmentproduct.
ThisEVMshouldbeusedsolelybyqualifiedengineersandtechnicianswhoarefamiliarwith
therisksassociatedwithhandlingelectricalandmechanicalcomponents,systemsand
subsystems.
YourObligationsandResponsibilities
PleaseconsulttheEVMdocumentation,includingbutnotlimitedtoanyuserguides,setup
guidesorgettingstartedguides,andotherwarningspriortousingtheEVM.Anyuseofthe
EVMoutsideofthespecifiedoperatingrangemaycausedangertousersand/orproduce
unintendedresults,inaccurateoperation,andpermanentdamagetotheEVMand
associatedelectronics.Youacknowledgeandagreethat:
YouareresponsibleforcompliancewithallapplicableFederal,Stateandlocalregulatory
requirements(includingbutnotlimitedtoFoodandDrugAdministrationregulations,UL,
CSA,VDE,CE,RoHSandWEEE,)thatrelatetoyouruse(andthatofyouremployees,
contractorsordesignees)oftheEVMforevaluation,testingandotherpurposes.
Youareresponsibleforthesafetyofyouandyouremployeesandcontractorswhen
usingorhandlingtheEVM.Further,youareresponsibleforensuringthatanycontacts
orinterfacesbetweentheEVMandanyhumanbodyaredesignedtobesafeandto
avoidtheriskofelectricalshock.
Youwilldefend,indemnifyandholdTI,itslicensorsandtheirrepresentativesharmless
fromandagainstanyandallclaims,damages,losses,expenses,costsandliabilities
(collectively,“Claims”)arisingoutof,orinconnectionwithanyuseoftheEVMthatis
notinaccordancewiththetermsofthisagreement.Thisobligationshallapplywhether
Claimsariseunderthelawoftortorcontractoranyotherlegaltheory,andevenifthe
EVMfailstoperformasdescribedorexpected.
Warning
TheEVMboardmaygetveryhotduringuse.Specifically,theDSP,itsheat
sinkandpowersupplycircuitsallheatupduringoperation.Thiswillnotharm
theEVM.Usecarewhentouchingtheunitwhenoperatingorallowittocool
afterusebeforehandling.Ifunitisoperatedinanenvironmentthatlimits
freeairflow,afanmaybeneeded.

3
Preface
AboutthisDocument
ThisdocumentisaTechnicalReferenceManualfortheTMS320C6678EvaluationModule
(TMDSEVM6678L)designedanddevelopedbyAdvantechLimitedforTexasInstruments,Inc.
NotationalConventions
Thisdocumentusesthefollowingconventions:
Programlistings,programexamples,andinteractivedisplaysareshowninamonospaced
font.Examplesuseboldforemphasis,andinteractivedisplaysuseboldtodistinguish
commandsthatyouenterfromitemsthatthesystemdisplays(suchasprompts,command
output,errormessages,etc.).
Squarebrackets([and])identifyanoptionalparameter.Ifyouuseanoptionalparameter,
youspecifytheinformationwithinthebrackets.Unlessthesquarebracketsareinabold
typeface,donotenterthebracketsthemselves.
Underlined,italicizednon‐boldtextinacommandisusedtomarkplaceholdertextthat
shouldbereplacedbytheappropriatevaluefortheuser’sconfiguration.

4
Trademarks
TheTexasInstrumentslogoandTexasInstrumentsareregisteredtrademarksofTexas
Instruments.TrademarksofTexasInstrumentsinclude:TI,XDS,CodeComposer,Code
ComposerStudio,ProbePoint,CodeExplorer,DSP/BIOS,RTDX,OnlineDSPLab,TMS320,
TMS320C54x,TMS320C55x,TMS320C62x,TMS320C64x,TMS320C67x,TMS320C5000,and
TMS320C6000.

MS‐DOS,Windows,WindowsXP,andWindowsNTaretrademarksofMicrosoft
Corporation.
UNIXisaregisteredtrademarkofTheOpenGroupintheUnitedStatesandothercountries.
Allotherbrand,productnames,andservicenamesaretrademarksorregisteredtrademarks
oftheirrespectivecompaniesororganizations.


5
DocumentRevisionHistory
Release Chapter DescriptionofChange
1.00All TheFirstRelease fordraft
2.00AllTheSecondReleaseforRev1.0production
2.01AllTheThirdReleaseforRev3.0production
 
Acronyms
Acronym Description
AMCorAdvancedMC AdvancedMezzanineCard
CCS CodeComposerStudio
DDR3DoubleDataRate3Interface
DSP DigitalSignalProcessor
DTE DataTerminalEquipment
EEPROM ElectricallyErasableProgrammableReadOnlyMemory
EMAC EthernetMediaAccessController
EMIF ExternalMemoryInterface
EVM EvaluationModule
FPGA FieldProgrammableGateArray
RFUReservedforFutureUse
I2C InterIntegratedCircuit
IPMB IntelligentPlatformManagementBus
IPMI IntelligentPlatformManagementInterface
JTAG JointTestActionGroup
LED LightEmittingDiode
MCH MicroTCACarrierHub
MTCAorMicroTCA MicroTelecommunicationComputingArchitecture
MMC ModuleManagementController
PICMG® PCIIndustrialComputerManufacturersGroup
PCIEPCIexpress
SDRAM SynchronousDynamicRandomAccessMemory
SERDES Serializer‐Deserializer
SGMII SerialGigabitMediaIndependentInterface
SRIO SerialRapidIO
TSIPTelecomSerialInterfacePort
UART UniversalAsynchronousReceiver/Transmitter
USB UniversalSerialBus
XDS560v2 TexasInstruments’SystemTraceEmulator

6
TableofContents
1.Overview..............................................................................................................................11
1.1KeyFeatures...............................................................................................................11
1.2FunctionalOverview..................................................................................................12
1.3BasicOperation..........................................................................................................12
1.4BootModeandBootConfigurationSwitchSetting..................................................13
1.5PowerSupply.............................................................................................................14
2.IntroductiontotheTMDSEVM6678Lboard........................................................................15
2.1MemoryMap.............................................................................................................15
2.2EVMBootModeandBootConfigurationSwitchSettings........................................18
2.3JTAG‐EmulationOverview........................................................................................18
2.4ClockDomains............................................................................................................19
2.5I2CBootEEPROM/SPINORFlash.............................................................................20
2.6FPGA...........................................................................................................................21
2.7GigabitEthernetConnections....................................................................................22
2.8SerialRapidIO(SRIO)Interface..................................................................................22
2.9DDR3ExternalMemoryInterface..............................................................................23
2.1016‐bitAsynchronousExternalMemoryInterface(EMIF‐16)...................................23
2.11HyperLinkInterface..................................................................................................24
2.12PCIeInterface...........................................................................................................25
2.13TelecomSerialInterfacePort(TSIP)........................................................................25
2.14UARTInterface.........................................................................................................26
2.15ModuleManagementController(MMC)forIPMI..................................................26
2.16ExpansionHeader....................................................................................................27
3.TMDSEVM6678LBoardPhysicalSpecifications...................................................................28
3.1BoardLayout..............................................................................................................28
3.2ConnectorIndex.........................................................................................................29
3.2.1560V2_PWR1,XDS560v2MezzaninePowerConnector..............................30
3.2.2AMC1,AMCEdgeConnector.......................................................................30
3.2.3COM1,UART3PinConnector.......................................................................32
3.2.4COM_SEL1,UARTRouteSelectConnector..................................................32
3.2.5DC_IN1,DCPowerInputJackConnector.....................................................33
3.2.6EMU1,TI60‐PinDSPJTAGConnector..........................................................33
3.2.7FAN1,FANConnector...................................................................................34
3.2.8HyperLink1,HyperLinkConnector...............................................................35
3.2.9LAN1,EthernetConnector...........................................................................37
3.2.10PMBUS1,PMBUSConnectorforSmart‐ReflexControl.............................37
3.2.11TAP_FPGA1,FPGAJTAGConnector(ForFactoryUseOnly).......................38
3.2.12SBW_MMC1,MSP430SpyBiWireConnector(ForFactoryUseOnly).......39
3.2.13TEST_PH1,ExpansionHeader(EMIF‐16,SPI,GPIO,TimerI/O,I2C,and
UART).......................................................................................................................39
3.2.14USB1,Mini‐USBConnector........................................................................41
3.3DIPandPushbuttonSwitches....................................................................................41

7
3.3.1RST_FULL1,FullReset..................................................................................41
3.3.2RST_COLD1,ColdReset................................................................................42
3.3.3RST_WARM1,WarmReset...........................................................................42
3.3.4SW3,SW4,SW5,andSW6,DSPbootmodeandConfiguration..................42
3.3.4SW9,DSPPCIESSEnableandUserDefinedSwitchConfiguration..............44
3.4TestPoints..................................................................................................................45
3.5SystemLEDs...............................................................................................................47
4.SystemPowerRequirements...............................................................................................48
4.1PowerRequirements.................................................................................................48
4.2ThePowerSupplyDistribution..................................................................................50
4.3ThePowerSupplyBootSequence.............................................................................54
5.TMDSEVM6678LFPGAFUNCTIONALDESCRIPTION............................................................59
5.1FPGAoverview...........................................................................................................59
5.2FPGAsignalsdescription............................................................................................60
5.3Sequenceofoperation...............................................................................................
66
5.3.1Power‐OnSequence........................................................................................67
5.3.2PowerOffSequence........................................................................................67
5.3.3BootConfigurationTiming..............................................................................68
5.3.4BootConfigurationForcedinI2CBoot...........................................................69
5.4Resetdefinition..........................................................................................................69
5.4.1ResetBehavior................................................................................................69
5.4.2ResetSwitchesandTriggers............................................................................70
5.5SPIprotocol................................................................................................................71
5.5.1FPGA‐DSPSPIProtocol....................................................................................71
5.5.2FPGA‐CDCE62005(ClockGenerator)SPIProtocol..........................................73
5.5.3TheFPGA‐programmingCDCE62005fromtheDSP.......................................74
5.5.4CDCE62005programmingsequencesontheFPGA........................................76
5.5.5CDCE62005defaultvalueontheEVM.........................................................77
5.6FPGAConfigurationRegisters....................................................................................78
5.6.1FPGAConfigurationRegistersSummary.........................................................78
5.6.2FPGAConfigurationRegistersDescriptions....................................................79


8
ListofFigures
Figure1.1:BlockDiagramofTMDSEVM6678LEVM...............................................................12
Figure1.2:TMDSEVM6678LEVMLayout................................................................................13
Figure2.1:TMDSEVM6678LEVMJTAGemulation.................................................................19
Figure2.2:TMDSEVM6678LEVMClockDomains...................................................................20
Figure2.3:TMDSEVM6678LEVMFPGAConnections.............................................................21
Figure2.4:TMDSEVM6678LEVMEthernetRouting...............................................................22
Figure2.5:TMDSEVM6678LEVMSRIOPortConnections......................................................22
Figure2.6:TMDSEVM6678LEVMSDRAM...............................................................................23
Figure2.7:TMDSEVM6678LEVMEMIF‐16connections.........................................................24
Figure2.8:TMDSEVM6678LEVMHyperLinkconnections......................................................24
Figure2.9:TMDSEVM6678LEVMPCIEPortConnections.......................................................25
Figure2.10:TMDSEVM6678LEVMTSIPconnections.............................................................26
Figure2.11:TMDSEVM6678LEVMUARTConnections...........................................................26
Figure2.12:TMDSEVM6678LEVMMMCConnectionsforIPMI.............................................27
Figure3.1:TMDSEVM6678LEVMBoardAssemblyLayout–TOPview..................................28
Figure3.2:TMDSEVM6678LEVMBoardlayout–Bottomview..............................................29
Figure3.3:COM_SEL1Jumpersetting.....................................................................................33
Figure3.4:TheHyperLinkConnector.....................................................................................35
Figure3.5:TAP_FPGA1functiondiagram...............................................................................39
Figure3.6:SW3,SW4,SW5,andSW6defaultsettings..........................................................42
Figure3.7:SW9defaultsettings.............................................................................................44
Figure3.8:TMDSEVM6678Ltestpointsontopside..............................................................45
Figure3.9:TMDSEVM6678Ltestpointsonthebottomside..................................................45
Figure3.10:TMDSEVM6678LEVMBoardLEDs......................................................................47
Figure4.1:AlltheAMCpowersupplyonTMDSEVM6678LEVM............................................51
Figure4.2:TheCVDDandVCC1V0(CVDD1)powerdesignonTMDSEVM6678LEVM...........52
Figure4.3:TheVCC3_AUXpowerdesignonTMDSEVM6678LEVM......................................53
Figure4.4:TheVCC1V5powerdesignonTMDSEVM6678LEVM...........................................53
Figure4.5:TheVCC5powerdesignonTMDSEVM6678LEVM...............................................54
Figure4.6:InitialPowerUpSequenceTimingDiagram..........................................................57
Figure4.7:InitialPowerDownSequenceTimingDiagram.....................................................58
Figure5.1:Power‐OnResetBootConfigurationTiming..........................................................68

9
Figure5.2:Reset‐FullSwitch/TriggerBootConfigurationTiming............................................69
Figure5.3:TheSPIaccessformtheTMS320C6678totheFPGA(WRITE/highlevel)............72
Figure5.4:TheSPIaccessformtheTMS320C6678totheFPGA(WRITE)...............................72
Figure5.5:TheSPIaccessformtheTMS320C6678totheFPGA(READ/highlevel)..............72
Figure5.6:TheSPIaccessformtheTMS320C6678totheFPGA(READ)................................73
Figure5.7:TheSPIaccessformtheFPGAtotheCDCE62005(WRITE)...................................73
Figure5.8:TheSPIaccessformtheFPGAtotheCDCE62005(READ).....................................73


10
ListofTables
Table2.1:TMS320C6678MemoryMap..................................................................................16
Table3.1:TMDSEVM6678LEVMBoardConnectors..............................................................29
Table3.2:XDS560v2PowerConnectorpinout......................................................................30
Table3.3:AMCEdgeConnector...............................................................................................30
Table3.4:UARTConnectorpinout..........................................................................................32
Table3.5:UARTPathSelectConnectorpinout.......................................................................
33
Table3.6:DSPJTAGConnectorpinout....................................................................................34
Table3.7:FAN1Connectorpinout.........................................................................................35
Table3.8:TheHyperLinkConnector.......................................................................................36
Table3.9:EthernetConnectorpinout....................................................................................37
Table3.10:PMBUS1pinout...................................................................................................38
Table3.11:FPGAJTAGConnectorpinout..............................................................................38
Table3.12:MSP430JTAGConnectorpinout..........................................................................39
Table3.13:ExpansionHeaderpinout....................................................................................40
Table3.14:Mini‐USBConnectorpinout.................................................................................41
Table3.15:TMDSEVM6678LEVMBoardSwitches.................................................................41
Table3.16:SW3‐SW6,DSPConfigurationSwitch...................................................................
43
Table3.17:SW9,DSPPCIExpressEnableandUserSwitch.....................................................44
Table3.18:TMDSEVM6678LEVMBoardTestPoints.............................................................46
Table3.19:TMDSEVM6678LTEEVMBoardLEDs.....................................................................47
Table4.1:EVMVoltageTable..................................................................................................49
Table4.2:EachCurrentRequirementsoneachdeviceofEVMboard...................................50
Table4.3:Thepower‐upanddowntimingontheTMDSEVM6678L......................................56
Table5.1:TMDSEVM6678LEVMFPGAPinDescription..........................................................60
Table5.2:CLK2,CDCE62005Registerconfigurations..............................................................77
Table5.3:CLK3,CDCE62005Registerconfigurations..............................................................77
Table5.4:TMS320C6678EVMFPGAMemoryMap...............................................................78
Table5.7:FPGAConfigurationRegistersSummary................................................................78


11
1.Overview
ThischapterprovidesanoverviewoftheTMDSEVM6678Lalongwiththekeyfeaturesand
blockdiagram.
1.1KeyFeatures
1.2FunctionalOverview
1.3BasicOperation
1.4ConfigurationSwitchSettings
1.5PowerSupply

1.1KeyFeatures
TheTMDSEVM6678Lisahighperformance,cost‐efficient,standalonedevelopment
platformthatenablesuserstoevaluateanddevelopapplicationsfortheTexasInstruments’
TMS320C6678DigitalSignalProcessor(DSP).TheEvaluationModule(EVM)alsoservesasa
hardwarereferencedesignplatformfortheTMS320C6678DSP.TheEVM’sform‐factoris
equivalenttoasingle‐widePICMG®AMC.0R2.0AdvancedMCmodule.
Schematics,codeexamplesandapplicationnotesareavailabletoeasethehardware
developmentprocessandtoreducethetimetomarket.
ThekeyfeaturesoftheTMDSEVM6678LEVMare:
zTexasInstruments'multi‐coreDSP–TMS320C6678
z512MbytesofDDR3‐1333Memory
z64MbytesofNANDFlash
z16MBSPINORFLASH
zTwoGigabitEthernetportssupporting10/100/1000Mbpsdata‐rate–oneon
AMCconnectorandoneRJ‐45connector
z170pinB+styleAMCInterfacecontainingSRIO,PCIe,GigabitEthernetandTDM
zHighPerformanceconnectorforHyperLink
z128K‐byteI2CEEPROMforbooting
z2UserLEDs,5BanksofDIPSwitchesand4Software‐controlledLEDs
zRS232Serialinterfaceon3‐PinheaderorUARTovermini‐USBconnector
zEMIF,Timer,SPI,UARTon80‐pinexpansionheader
zOn‐BoardXDS100typeEmulationusingHigh‐speedUSB2.0interface
zTI60‐PinJTAGheadertosupportallexternalemulatortypes
zModuleManagementController(MMC)forIntelligentPlatformManagement
Interface(IPMI)

12
zOptionalXDS560v2SystemTraceEmulationMezzanineCard
zPoweredbyDCpower‐brickadaptor(12V/3.0A)orAMCCarrierbackplane
zPICMG®AMC.0R2.0singlewidth,fullheightAdvancedMCmodule

1.2FunctionalOverview
TheTMS320C66x™DSPs(includingtheTMS320C6678device)arethehighest‐performance
fixed/floating‐pointDSPgenerationintheTMS320C6000™DSPplatform.The
TMS320C6678deviceisbasedonthethird‐generationhigh‐performance,advanced
VelociTI™very‐long‐instruction‐word(VLIW)architecturedevelopedbyTexasInstruments
(TI),designedspecificallyforhighdensitywireline/wirelessmediagatewayinfrastructure.
ItisanidealsolutionforIPbordergateways,videotranscodingandtranslation,video‐server
andintelligentvoiceandvideorecognitionapplications.TheC66xdevicesarebackward
code‐compatiblefrompreviousdevicesthatarepartoftheC6000™DSPplatform.
ThefunctionalblockdiagramofTMDSEVM6678Lisshowninthefigurebelow:

Figure1.1:BlockDiagramofTMDSEVM6678LEVM

1.3BasicOperation
TheTMDSEVM6678LplatformisdesignedtoworkwithTI’sCodeComposerStudio(CCS)
developmentenvironmentandshipswithaversionspecificallytailoredforthisboard.CCS
caninterfacewiththeboardviaon‐boardemulationcircuitryusingtheUSBcablesupplied
alongwiththisEVMorthroughanexternalemulator.
TheEVMcomeswiththeTexa sInstrumentsMulticoreSoftwareDevelopmentKit(MCSDK)
forSYS/BIOSOS.TheBIOSMCSDKprovidesthecorefoundationalbuildingblocksthat
UsercontrolledLED‐4
SYSPG_D1LED
D1
TSIPx2 Level‐Shifter
DIP_SWITCH
JTAG
SBW_MMC1
UCD9222_PMbus
DEBUG_LED
TMS320C6678
N25Q128A21BSF40F
UART
MAC1
MDIO
JTAG&EMU[0:1]
EMU[2:17]
MAC0
EMIF
PCIEx2
I2C
DDR3 HyperLink
GPIO[0:15](1.8V)
MiscellaneousI/Oconn.
EMIF16(1.8V) DSP_UART(3.3V) DSP_SPI(1.8V) DSP_I2C(1.8V)
RS232
MAX3221EAE
DSP_UART
FT2232HL
USB‐JTAG
CH‐B
CH‐A
DSP_SGMII_P1&MDIO
DSP_UART
ENETPHY
Mini‐USB
USB
RJ45
88E1111‐B2
TSIPx2
SRIOx4
SGMIIx1
SRIOx4
PCIEx2
SPI
GPIO
MMC
EMIF
IPMB‐L
AMC_State
#0
PWRCONN
POWER12V
DSP
fromMMC
AMC_State
AT25128B
SPI
GPIO[0:15]
DIPSW
SPIEEPROM
RAM
Others
FPGA
Power
PowerCont rol
(MSP430)
PHY
DDR3‐1333
DDR3‐1333
1.64MX16/512MB
2.128MX16/1GB
w/ECC
(XILINX)
JTAG MMC
DSP_SPI#1
FPGA
XC3S200AN DSP_GPIO
HyperLink
ROM_SPI
CLK_SPI3
CLK_SPI2
50Gbps
DSP
iPass+HD
DSP_I2C
toFPGA
TSIPx2
PowerControl
128k‐bit
Con trol
Sequence
FPGAJTAG JTAG
NOR128M‐bit
SPIFlash
60‐PinEMUCONN.
HyperLinkCONN.
JTAG&EMU[0:1]
EMU[2:17]
JTAG&
EMU[0:1]
COM1connector
2.54mm
CDCE62005
CLK#1
CLK#2
CDCE62005
DSP_SGMII_P1&MDIO
M24M01‐HRMN6TP
EEPROM
128k‐byte
BM_GPIO(0~15)/
PCIESSEN/Userdefine

NUResistors
NANDFLASH
512Mb64MX8)
NUMONYX
NAND512R3A2DZA6E
D2
SWITCH
(TS3L301)
LEVEL SHIFT
SWITCH
(TS3L301)
AMCJTAG
AMCJTAG
1.1GbX16
2.1GbX8
DDR3(ECC)

13
facilitateapplicationsoftwaredevelopmentonTI'shighperformanceandmulticoreDSPs.
TheMCSDKalsoincludesanout‐of‐boxdemonstration;seethe"MCSDKGettingStarted
Guide".
Tostartoperatingtheboard,followinstructionsintheQuickStartGuide.Thisguide
providesinstructionforproperconnectionsandconfigurationforrunningthePOSTand
OOBDemos.AftercompletingthePOSTandOOBDemos,proceedwithinstallingCCSand
theEVMsupportfilesbyfollowingtheinstructionsontheDVD.Thisprocesswillinstallall
thenecessarydevelopmenttools,driversanddocumentation.
Aftertheinstallationhascompleted,followthestepsbelowtorunCodeComposerStudio.
1.Power‐ontheboardusingthepowerbrickadaptor(12V/3.0A)suppliedalongwiththis
EVMorinsertingthisEVMboardintoaMicroTCAchassisorAMCcarrierbackplane.
2.ConnectUSBcablefromhostPCtoEVMboard.
3.LaunchCodeComposerStudiofromhostPCbydoubleclickingonitsicononthePC
desktop.
DetailedinformationabouttheEVMincludingexamplesandreferencematerialsare
availableintheDVDincludedwiththisEVMkit.

Figure1.2:TMDSEVM6678LEVMLayout

1.4BootModeandBootConfigurationSwitchSetting
TheTMDSEVM6678Lhas18slidingDIPswitches(BoardRef.SW3toSW6andSW9)to
determinebootmode,bootconfiguration,devicenumber,Endianmode,CorePacPLLclock
selectionandPCIeModeselectionoptionslatchedatresetbytheDSP.

PHYFPGA
60‐pinJTAG
Emulator
64MBNAND
SBW
_
MMC
HyperLink
TMS320C6678
DCIN12V
FAN1
512MBDDR3‐1333
80‐pinExpansionHeader
TAP_FPGA1
PMBUS1
Gigabit
EthernetJack
SW6SW5SW4 SW3SW9
COM1
USB
Emulator
COM_SEL1
560V2_PWR
RST_FULL1
RST_WARM1
RST_COLD1

14
1.5PowerSupply
TheTMDSEVM6678Lcanbepoweredfromasingle+12V/3.0ADC(36W)externalpower
supplyconnectedtotheDCpowerjack(DC_IN1).Internally,+12Vinputisconvertedinto
requiredvoltagelevelsusinglocalDC‐DCconverters.
•CVDD(+0.90V~+1.05V)usedfortheDSPCorelogic
•+1.0VisusedforDSPinternalmemoryandHyperLink/SRIO/SGMII/PCIeSERDES
terminationofDSP
•+1.5VisusedforDDR3buffersofDSP,HyperLink/SRIO/SGMII/PCIeSERDESregulators
inDSPandDDR3DRAMchips
•+1.8VisusedforDSPPLLs,DSPLVCMOSI/OsandFPGAI/OsdrivingtheDSP
•+2.5VisusedforGigabitEthernetPHYcore
•+1.2VisusedforFPGAcoreandGigabitEthernetPHYcore
•+3.3VisusedforFPGAI/Os
•+5Vand+3.3VisusedtopoweroptionalXDS560v2mezzaninecard
•TheDCpowerjackconnectorisa2.5mmbarrel‐typeplugwithcenter‐tipaspositive
polarity
TheTMDSEVM6678LcanalsodrawpowerfromtheAMCedgeconnector(AMC1).Ifthe
boardisinsertedintoaPICMG®MicroTCA.0R1.0compliantsystemchassisorAMCCarrier
backplane,anexternal+12VsupplyfromDCjack(DC_IN1)isnotrequired.


15
2.IntroductiontotheTMDSEVM6678Lboard
ThischapterprovidesanintroductionanddetailsofinterfacesfortheTMDSEVM6678L
board.Itcontains:
2.1MemoryMap
2.2EVMBootmodeandBootconfigurationswitchsettings
2.3JTAG‐EmulationOverview
2.4ClockDomains
2.5I2CbootEEPROM/SPINORFlash
2.6FPGA
2.7GigabitEthernetPHY
2.8SerialRapidIO(SRIO)Interfaces
2.9DDR3ExternalMemoryInterfaces
2.1016‐bitAsynchronousExternalMemoryInterface
2.11HyperLinkInterface
2.12PCIeInterface
2.13TelecomSerialInterfacePort(TSIP)
2.14UARTInterfaces
2.15ModuleManagementControllerforIPMI
2.16AdditionalHeaders

2.1MemoryMap
ThememorymapoftheTMS320C6678deviceisasshowninTable1.Theexternalmemory
configurationregisteraddressrangesintheTMS320C6678devicebeginatthehexaddress
location0x70000000forEMIFAandhexaddresslocation0x80000000forDDR3Memory
Controller.


16
Table2.1:TMS320C6678MemoryMap
AddressRangeBytes MemoryBlockDescription
0x00800000–0x0087FFFF512K LocalL2SRAM
0x00E00000–0x00E07FFF32K LocalL1PSRAM
0x00F00000–0x00F07FFF32K L1DSRAM
0x01800000–0x01BFFFFF4M C66xCorePacRegisters
0x01E00000–0x01E3FFFF256K TelecomSerialInterfacePort(TSIP)0
0x01E80000–0x01EBFFFF256K TelecomSerialInterfacePort(TSIP)1
0x02000000–0x0209FFFF640K PacketAcceleratorSubsystemConfiguration
0x02310000–0x023101FF512 PLLController
0x02320000–0x023200FF256 GPIO
0x02330000–0x023303FF1K SmartRlex
0x02350000–0x02350FFF4K PowerSleepController(PSC)
0x02360000–0x023603FF1K MemoryProtectionUnit(MPU)0
0x02368000–0x023683FF1K MemoryProtectionUnit(MPU)1
0x02370000–0x023703FF1K MemoryProtectionUnit(MPU)2
0x02378000–0x023783FF1K MemoryProtectionUnit(MPU)3
0x02530000–0x0253007F128 I2CData&Control
0x02540000–0x0254003F64 UART
0x02600000–0x02601FFF8K SecondaryInterruptController(INTC)0
0x02604000–0x02605FFF8K SecondaryInterruptController(INTC)1
0x02608000–0x02609FFF8K SecondaryInterruptController(INTC)2
0x0260C000–0x0260DFFF8K SecondaryInterruptController(INTC)3
0x02620000–0x026207F2K Chip‐LevelRegisters(bootcfg)
0x02640000–0x026407FF2K Semaphore
0x02700000–0x02707FFF32K EDMAChannelController(TPCC)0
0x02720000–0x02727FFF32K EDMAChannelController(TPCC)1
0x02740000–0x02747FFF32K EDMAChannelController(TPCC)2
0x02760000–0x027603FF1K EDMATPCC0TransferController(TPTC)0
0x02768000–0x027683FF1K EDMATPCC0TransferController(TPTC)1
0x02770000–0x027703FF1K EDMATPCC1TransferController(TPTC)0
0x02778000–0x027783FF1K EDMATPCC1TransferController(TPTC)1
0x02780000–0x027803FF1K EDMATPCC1TransferController(TPTC)2
0x02788000–0x027883FF1K EDMATPCC1TransferController(TPTC)3
0x02790000–0x027903FF1K EDMATPCC2TransferController(TPTC)0
0x02798000–0x027983FF1K EDMATPCC2TransferController(TPTC)1
0x027A0000–0x027A03FF1K EDMATPCC2TransferController(TPTC)2
0x027A8000–0x027A83FF1K EDMATPCC2TransferController(TPTC)3
0x027D0000–0x027D3FFF16K TIEmbeddedTraceBuffer(TETB)core0
0x027E0000–0x027E3FFF16K TIEmbeddedTraceBuffer(TETB)core1
0x027F0000–0x027F3FFF16K TIEmbeddedTraceBuffer(TETB)core2
0x02800000–0x02803FFF16K TIEmbeddedTraceBuffer(TETB)core3
0x02810000–0x02813FFF16K TIEmbeddedTraceBuffer(TETB)core4

17
AddressRangeBytes MemoryBlockDescription
0x02820000–0x02823FFF16K TIEmbeddedTraceBuffer(TETB)core5
0x02830000–0x02833FFF16K TIEmbeddedTraceBuffer(TETB)core6
0x02840000–0x02843FFF16K TIEmbeddedTraceBuffer(TETB)core7
0x02850000–0x02857FFF32K TIEmbeddedTraceBuffer(TETB)—system
0x02900000–0x02907FFF32K SerialRapidIO(SRIO)Configuration
0x02A00000–0x02BFFFFF2M QueueManagerSubsystemConfiguration
0x08000000–0x0800FFFF64K ExtendedMemoryController(XMC)
Configuration
0x0BC00000
–
0x0BCFFFFF1M MulticoreSharedMemoryController(MSMC)
Config
0x0C000000–0x0C3FFFFF4M MulticoreSharedMemory
0x10800000–0x1087FFFF512K Core0L2SRAM
0x10E00000–0x10E07FFF32K Core0L1PSRAM
0x10F00000–0x10F07FFF32K Core0L1DSRAM
0x11800000–0x1187FFFF512K Core1L2SRAM
0x11E00000–0x11E07FFF32K Core1L1PSRAM
0x11F00000–0x11F07FFF32K Core1L1DSRAM
0x12800000–0x1287FFFF512K Core2L2SRAM
0x12E00000–0x12E07FFF32K Core2L1PSRAM
0x12F00000–0x12F07FFF32K Core2L1DSRAM
0x13800000–0x1387FFFF512K Core3L2SRAM
0x13E00000–0x13E07FFF32K Core3L1PSRAM
0x13F00000–0x13F07FFF32K Core3L1DSRAM
0x14800000–0x1487FFFF512K Core4L2SRAM
0x14E00000–0x14E07FFF32K Core4L1PSRAM
0x14F00000–0x14F07FFF32K Core4L1DSRAM
0x15800000–0x1587FFFF512K Core5L2SRAM
0x15E00000–0x15E07FFF32K Core5L1PSRAM
0x15F00000–0x15F07FFF32K Core5L1DSRAM
0x16800000–0x1687FFFF512K Core6L2SRAM
0x16E00000–0x16E07FFF32K Core6L1PSRAM
0x16F00000–0x16F07FFF32K Core6L1DSRAM
0x17800000–0x1787FFFF512K Core7L2SRAM
0x17E00000–0x17E07FFF32K Core7L1PSRAM
0x17F00000–0x17F07FFF32K Core7L1DSRAM
0x20000000–0x200FFFFF1M SystemTraceManager(STM)Configuration
0x20B00000‐0x20B1FFFF128K BootROM
0x20BF0000‐0x20BF03FF1K SPI
0x20C00000
–
0x20C000FF256 EMIF‐16Configuration
0x21000000
–
0x210000FF256 DDR3EMIFConfiguration
0x21400000–0x214003FF1K HyperLinkConfiguration
0x21800000–0x21807FFF32K PCIeConfiguration
0x21400000–0x214003FF1K HyperLinkConfig

18
AddressRangeBytes MemoryBlockDescription
0x40000000–0x4FFFFFFF2M HyperLinkdata
0x60000000–0x6FFFFFFF256M PCIeData
0x70000000–0x73FFFFFF64M EMIF16CS2DataNANDMemory
0x74000000–0x77FFFFFF64M EMIF16CS3DataNANDMemory
0x78000000–0x7BFFFFFF64M EMIF16CS4DataNORMemory
0x7C000000–0x7FFFFFFF64M EMIF16CS5DataSRAMMemory
0x80000000–0x8FFFFFFF256M DDR3_Data
0x90000000–0x9FFFFFFF256M DDR3_Data
0xA0000000–0xAFFFFFFF256M DDR3_Data
0xB0000000–0xBFFFFFFF256M DDR3_Data
0xC0000000–0xCFFFFFFF256M DDR3_Data
0xD0000000–0xDFFFFFFF256M DDR3_Data
0xE0000000–0xEFFFFFFF256M DDR3_Data
0xF0000000–0xFFFFFFFF256M DDR3_Data

2.2EVMBootModeandBootConfigurationSwitchSettings
TheTMDSEVM6678LhasfiveconfigurationDIPswitches:SW3,SW4,SW5,SW6andSW9
thatcontain17individualvalueslatchedwhenresetisreleased.Thisoccurswhenpoweris
appliedtheboard,aftertheuserpressestheFULL_RESETpushbuttonorafteraPORresetis
requestedfromtheMMC.
SW3determinesgeneralDSPconfiguration,LittleorBigEndianmodeandbootdevice
selection.
SW4,SW5,SW6andSW9determineDSPbootdeviceconfiguration,CorePacPLLsettingand
PCIemodeselectionandenable.
MoreinformationaboutusingtheseDIPswitchesiscontainedinSection3.3ofthis
document.FormoreinformationonDSPsupportedBootModes,refertoTMS320C6678
DataManualandC66xBootLoaderUserGuide.

2.3JTAG‐EmulationOverview
TheTMDSEVM6678Lhason‐boardembeddedJTAGemulationcircuitry;henceusersdonot
requireanyexternalemulatortoconnectEVMwithCodeComposerStudio.Userscan
connectCCSwiththetargetDSPontheEVMthroughtheUSBcablesuppliedalongwiththis
board.
IncaseuserswishtoconnectanexternalemulatortotheEVM,theTI60‐pinJTAGheader
(EMU1)isprovidedforhighspeedreal‐timeemulation.TheTI60‐pinJTAGsupportsall

19
standardTIDSPemulators.Anadapterwillberequiredforusewithsomeemulators.
Theon‐boardembeddedJTAGemulatoristhedefaultconnectiontotheDSP.However
whenanexternalemulatorisconnectedtoEVM,theboardcircuitryswitchesautomatically
togiveemulationcontroltotheexternalemulator.
Whentheon‐boardemulatorandexternalemulatorbothareconnectedatthesametime,
theexternalemulatorhaspriorityandtheon‐boardemulatorisdisconnectedfromtheDSP.
ThethirdwayofaccessingtheDSPisthroughtheJTAGportontheAMCedgeconnector,
userscanconnecttheDSPthroughtheAMCbackplaneiftheydon’tusetheXDS100
on‐boardemulatorandthe60‐pinheaderwiththeexternalemulator.
TheJTAGinterfaceamongtheDSP,on‐boardemulator,externalemulatorandtheAMC
edgeconnectorisshowninthebelowfigure.

Figure2.1:TMDSEVM6678LEVMJTAGemulation

2.4ClockDomains
TheEVMincorporatesavarietyofclockstotheTMS320C6678aswellasotherdevices
whichareconfiguredautomaticallyduringthepowerupconfigurationsequence.Thefigure
belowillustratesclockingforthesystemintheEVMmodule.
PleasenotethatthePCIEclockinputontheDSPcanbeselectedbytheBM_GPIO_10,the
SW5.bit3ofslidingswitch,toswitchthePCIEclocksourcefromtheCDCE62005(set
BM_GPIO_10at“ON”withlogiclow)orfromtheFCLKontheAMCedgefinger(set
BM_GPIO_10at“OFF”withlogichigh).UserscouldalsoselectthePCIEclockbysetting
theoffset0x50hontheFPGAfromtheDSPifneeded.
AnewfeatureontheRev3.0EVMboardsupportsexternalclockreference.Thisisneeded
forsomeapplicationsusingtheHyperLinkSERDESinterface.Theexternalreferenceclock
COM1
UART
RS232
MAX3221EAE
DSP
TMS320C6678
USB1
USB‐JTAG
FT2232HL
COM_SEL1
EMU_DETPIN
EMU_DETz
SEL
SWITCH
(TS3L301)
EMU1
High‐Speed +1.8V
JTAG
JTAG
LevelShifter
+3.3V
FT2232HL_RESET#
+1.8V
JTAG
USB
+1.8V
RS232
Consoleport
SN74AVC4T24
JTAGEMU[0..1]
EMU[2..18]
SEL
SWITCH
(TS3L301)
High‐Speed
LevelShifter
+3.3V
JTAG
USB JTAG
+V3.3
AMCJTAG
UART
+3.3V
UART
+1.8V
AMC
edgeconnector

20
isdrivenintotheclockgenerationdeviceratherthanusingthelocalcrystal.
ForthetimingsynchronizationontheHyperLinkSERDES,acommon25MHztimingsourceis
fedfromtheAMCedgefingertotheclockgenerator,CLK2,thatdrivesa100MHzsource
clocktotheCLK3fortheMCM_CLKinputontheDSP.ItissuppliedontheAMCconnector
attheTCLKBinput.


Figure2.2:TMDSEVM6678LEVMClockDomains

2.5I2CBootEEPROM/SPINORFlash
TheI2CmodulesontheTMS320C6678maybeusedbytheDSPtocontrollocalperipheral
ICs(DACs,ADCs,etc.)ormaybeusedtocommunicatewithothercontrollersinasystemor
toimplementauserinterface.
TheI2CbusisconnectedtooneSEEPROMandtothe80‐pinexpansionheader(TEST_PH1).
TherearetwobanksintheI2CSEEPROMwhichrespondseparatelyataddresses0x50and
0x51.Thesebankscanbeloadedwithdemonstrationprograms.Currently,thebankat0x50
containstheI2CbootcodeandPLLinitializationprocedureandthebankat0x51contains
thesecondlevelboot‐loaderprogram.Thesecondlevelboot‐loadercanbeusedtorunthe
POSTprogramorlaunchtheOOBdemonstrationfromNORflashmemory.
Theserialperipheralinterconnect(SPI)moduleprovidesaninterfacebetweentheDSPand
otherSPI‐compliantdevices.Theprimaryintentofthisinterfaceistoallowforconnectionto
SEC_RE
PCIe_CLKp/n(from
FCLK:100MHz
CLK2
CLK3
CLK2sourceclock
(fromAMC)
TCLKB:
AUXIN
SEC_RE
25MHz
AUXIN
PRI_RE
XTAL
100.00MHz
66.667MH
CDCE62005
MUX
SEL(Controlledby
IN1
IN2
SRIO_SGMII_CLKp/n
PCIe_CLKp/n
MCM_CLKp/n
CORE_CLKp/n
PA_SS_CLKp/n
DDR_CLKp/n
DSP
TMS320C667
Support common HyperLink timing at
25MHz PRI_RE
312.50MHz
312.50MHz
100.00MHz
100.00MHz
U0
U3
U2
U1
U4
U1
U0
CDCE62005
100.00MHz
U4
U3
U2