NXP Semiconductors LPC29 Series User manual

UM10316
LPC29xx User manual
Rev. 3 — 19 October 2010 User manual
Document information
Info Content
Keywords LPC2917/01; LPC2919/01; LPC2926; LPC2927; LPC2929; LPC2921;
LPC2923; LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN,
USB
Abstract This document extends the LPC29xx data sheets with additional details to
support both hardware and software development. It focuses on functional
description and typical application use.

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10316
LPC29xx User manual
Revision history
Rev Date Description
3 20101019
Modifications: •Editorial updates to CGU, PMU, VIC, USB OTG, and Flash/EEPROM chapters.
•Table 103 “LPC2930 boot configuration” added.
•Part LPC2926 added.
•Editorial updates.
•Description of USBCmdCode register updated.
•Description of CMD bit in Set Device Status register updated.
2 20091116
Modifications: •LIN chapter updated with description and register map of the UART mode.
•Corrected description of NMMEN bit (bit 0) in the RS485CTRL register: 0 = RS-485 mode disabled.
1 = RS-485 mode enabled. Default value: 0.
•LPC2930/39 pin configuration table: pin 29 description corrected; P1[31] changed to P1[30].
•LPC2930/39 pin configuration table: USB_OVRCR1 function added to pin 31.
•Connection of ADC inputs to ADC channels corrected.
•UART function updated: The fractional divider can not be used in auto-baud mode.
•Editorial updates.
1 20090522 Initial LPC29xx user manual edition

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User manual Rev. 3 — 19 October 2010 3 of 566
1. Introduction
The LPC29xx combine an 125 MHz ARM968E-S CPU core, Full Speed USB 2.0 OTG
and device, CAN and LIN, up to 56 kB SRAM, up to 768 kB flash memory, external
memory interface, two or three 10-bit ADCs, and multiple serial and parallel interfaces in a
single chip targeted at consumer, industrial, medical, and communication. To optimize
system power consumption, the LPC29xx has a very flexible Clock Generation Unit
(CGU) that provides dynamic clock gating and scaling.
2. About this user manual
This document describes the following parts: LPC2917/01, LPC2919/01, LPC2921,
LPC2923, LPC2925, LPC2926, LPC2927, LPC2929, LPC2930, and LPC2939.
Differences between the various parts as they apply to each block or peripheral are listed
at the beginning of each chapter. For an overview of features see Table 1–2.
3. General features
Remark: See Table 1–2 for feature details for each LPC29xx part.
•ARM968E-S processor running at frequencies of up to 125 MHz maximum.
•Multi-layer AHB system bus at 125 MHz with four separate layers.
•On-chip memory:
–Two Tightly Coupled Memories (TCM), up to 32 kB Instruction (ITCM), up to 32 kB
Data TCM (DTCM).
–Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
–8 kB ETB SRAM.
–Up to 768 kB flash-program memory with 16 kB EEPROM.
•Dual-master, eight-channel GPDMA controlleron the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
•External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
•Serial interfaces:
–USB 2.0 full-speed device/OTG controller with dedicated DMA controller and
on-chip PHY for device and Host (LPC2930/39 only) functions.
–Two-channel CAN controller supporting Full-CAN and extensive message filtering
–Two LIN master controllers with full hardware support for LIN communication.
–Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485
support.
UM10316
Chapter 1: LPC29xx Introductory information
Rev. 3 — 19 October 2010 User manual

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 4 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
–Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations
deep; Tx FIFO and Rx FIFO.
–Two I2C-bus interfaces.
•Other peripherals:
–Up to three ADCs: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement
range and one, 8-channel 10-bit ADC with 5.0 V measurement range provide a
total of up to 24 analog inputs, with conversion times as low as 2.44 μs per
channel. Each channel provides a compare function to minimize interrupts.
–Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external
signal input.
–Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
–Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality.
–Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
–Quadrature encoder interface that can monitor one external quadrature encoder.
–32-bit watchdog with timer change protection, running on safe clock.
•Up to 108 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper.
•Vectored Interrupt Controller (VIC) with 16 priority levels.
•Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake-up
features.
•Configurable clock-out pin for driving external system clocks.
•Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
•Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
•Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules:
–On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring.
–On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz - max. PLL input 25 MHz.
–On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
–Generation of up to 11 base clocks.
–Seven fractional dividers.
•Highly configurable system Power Management Unit (PMU):
clock control of individual modules.
allows minimization of system operating power consumption in any configuration.
•Standard ARM test and debug interface with real-time in-circuit emulator.
•Boundary-scan test supported.
•ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage.
•Dual power supply:

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 5 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
–CPU operating voltage: 1.8 V ±5%.
–I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
•Available in 100-pin,144-pin, and 208-pin LQFP packages.
•−40 °C to 85 °C ambient operating temperature range.
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC2917FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2919FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2921FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2923FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2925FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2926FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2927FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2929FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2930FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1
LPC2939FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1

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UM10316 © NXP B.V. 2010. All rights reserved. User manual Rev. 3 — 19 October 2010 6 of 566 NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
4.1 Ordering options
Remark: Note that parts LPC2927 and LPC2929 are not fully pin compatible with parts LPC2917/01 and LPC2919/01 or
LPC2917 and LPC2919. On the LPC2927/29 the MSCSS and timer blocks have a reduced pinout.
4.2 Comparison with LPC2917/19 devices
Table 2. LPC29xx part overview
Part
number Flash SRAM (incl
ETB)
TCM
(I/D) CAN LIN/ UART Pins UART RS485 SPI 3V3 ADC 5 V ADC SMC USB device USB host USB OTG ETM QEI I2C-bus Clkout pin
LPC2939 768 kB 56 kB 32/32 kB 2 2 208 2 3 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes
LPC2930 - 56 kB 32/32 kB 2 2 208 2 3 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes
LPC2929 768 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2927 512 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2926 256 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2925 512 kB 40 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2923 256 kB 24 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2921 128 kB 24 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2919/01 768 kB 56 kB 16/16 kB 2 2 144 2 3 2 No Yes No No No Yes Yes Yes Yes
LPC2917/01 512 kB 56 kB 16/16 kB 2 2 144 2 3 2 No Yes No No No Yes Yes Yes Yes
Table 3. Feature comparison
Parts GPDMA UART
RS485
mode
I2C QEI CAN LIN USB
OTG/
device
Flash EEPROM SRAM
total ETB SRAM 5V ADC
LPC2917/19 no no no no 2 2 no 512/768 kB no 80 kB no no
LPC2917/19/01 yes yes yes yes 2 2 no 512/768 kB yes 88 kB 8 kB no
LPC2927/29 yes yes yes yes 2 2 yes 512/768 kB yes 120 kB 8 kB yes

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User manual Rev. 3 — 19 October 2010 7 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
4.3 LPC29xx USB options
Table 4. LPC29xx USB options
Part On-chip controller Ports On-chip PHY
Device Host OTG
LPC2917/01 - - - - -
LPC2919/01 - - - - -
LPC2921 Full-speed - - 1 Device
LPC2923 Full-speed - - 1 Device
LPC2925 Full-speed - - 1 Device
LPC2926 Full-speed - Full-speed 1 Device
LPC2927 Full-speed - Full-speed 1 Device
LPC2929 Full-speed - Full-speed 1 Device
LPC2930 Full-speed Full-speed Full-speed 2 Device, host
LPC2939 Full-speed Full-speed Full-speed 2 Device, host

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 8 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
5. Block diagram
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 1. LPC2917/19/01 block diagram
002aad959
ARM968E-S
DTCM
16 kB
ITCM
16 kB
TEST/DEBUG
INTERFACE
slave
slave
slave
slave
slave
slave
slave
slave
EXTERNAL STATIC
MEMORY CONTROLLER
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
512/768 kB 16 kB EEPROM
EMBEDDED SRAM 32 kB
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
LIN0/1
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/2/3
TIMER 0/1/2/3
SPI0/1/2
RS485 UART0/1
WDT
master
master
slave
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
AHB TO APB
BRIDGE
CLOCK
GENERATION
UNIT CGU0/1
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT
LPC2917/01
LPC2919/01
JTAG
interface
8 kB SRAM
slave
slave
1 ×master
2 × slave
AHB
MULTI
LAYER
MATRIX

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 9 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 2. LPC2921/23/25 block diagram
EMBEDDED FLASH
512/256/128 kB
002aae224
ARM968E-S
DTCM
16 kB
ITCM
16 kB
TEST/DEBUG
INTERFACE
slave
master
1 master
2 slaves
master GPDMA CONTROLLER
GPDMA REGISTERS
16 kB
EEPROM
EMBEDDED SRAM 16 kB
(LPC2925 only)
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/5
TIMER 0/1/2/3
SPI0/1/2
RS-485 UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER master
slave USB DEVICE
CONTROLLER
slave
slave
slave
slave
slave
slave
slave
slave
slave
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
UART/LIN0/1
AHB TO APB
BRIDGE
AHB
MULTI-
LAYER
MATRIX
LPC2921/2923/2925
JTAG
interface
8 kB SRAM
general subsystem
power, clock, and
reset subsystem
MSC subsystem
networking subsystem
peripheral subsystem
CLOCK
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 10 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 3. LPC2926/27/29 block diagram
002aae143
ARM968E-S
DTCM
32 kB
ITCM
32 kB
TEST/DEBUG
INTERFACE
slave
master
1 master
2 slaves
master
EXTERNAL STATIC
MEMORY CONTROLLER
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
512/768 kB 16 kB EEPROM
EMBEDDED SRAM 32 kB
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
UART/LIN0/1
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/2/3/5
TIMER 0/1/2/3
SPI0/1/2
RS485 UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER master
slave USB OTG/DEVICE
CONTROLLER
slave
slave
slave
slave
slave
slave
slave
slave
slave
slave
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
5 V ADC0
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
AHB TO APB
BRIDGE
CLOCK
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT
AHB
MULTI-
LAYER
MATRIX
LPC2926/27/2929
JTAG
interface
8 kB SRAM
general subsystem
power. clock, and
reset subsystem
MSC subsystem
networking subsystem
peripheral subsystem