NXP Semiconductors LPC29 Series User manual

UM10316
LPC29xx User manual
Rev. 3 — 19 October 2010 User manual
Document information
Info Content
Keywords LPC2917/01; LPC2919/01; LPC2926; LPC2927; LPC2929; LPC2921;
LPC2923; LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN,
USB
Abstract This document extends the LPC29xx data sheets with additional details to
support both hardware and software development. It focuses on functional
description and typical application use.

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10316
LPC29xx User manual
Revision history
Rev Date Description
3 20101019
Modifications: •Editorial updates to CGU, PMU, VIC, USB OTG, and Flash/EEPROM chapters.
•Table 103 “LPC2930 boot configuration” added.
•Part LPC2926 added.
•Editorial updates.
•Description of USBCmdCode register updated.
•Description of CMD bit in Set Device Status register updated.
2 20091116
Modifications: •LIN chapter updated with description and register map of the UART mode.
•Corrected description of NMMEN bit (bit 0) in the RS485CTRL register: 0 = RS-485 mode disabled.
1 = RS-485 mode enabled. Default value: 0.
•LPC2930/39 pin configuration table: pin 29 description corrected; P1[31] changed to P1[30].
•LPC2930/39 pin configuration table: USB_OVRCR1 function added to pin 31.
•Connection of ADC inputs to ADC channels corrected.
•UART function updated: The fractional divider can not be used in auto-baud mode.
•Editorial updates.
1 20090522 Initial LPC29xx user manual edition

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User manual Rev. 3 — 19 October 2010 3 of 566
1. Introduction
The LPC29xx combine an 125 MHz ARM968E-S CPU core, Full Speed USB 2.0 OTG
and device, CAN and LIN, up to 56 kB SRAM, up to 768 kB flash memory, external
memory interface, two or three 10-bit ADCs, and multiple serial and parallel interfaces in a
single chip targeted at consumer, industrial, medical, and communication. To optimize
system power consumption, the LPC29xx has a very flexible Clock Generation Unit
(CGU) that provides dynamic clock gating and scaling.
2. About this user manual
This document describes the following parts: LPC2917/01, LPC2919/01, LPC2921,
LPC2923, LPC2925, LPC2926, LPC2927, LPC2929, LPC2930, and LPC2939.
Differences between the various parts as they apply to each block or peripheral are listed
at the beginning of each chapter. For an overview of features see Table 1–2.
3. General features
Remark: See Table 1–2 for feature details for each LPC29xx part.
•ARM968E-S processor running at frequencies of up to 125 MHz maximum.
•Multi-layer AHB system bus at 125 MHz with four separate layers.
•On-chip memory:
–Two Tightly Coupled Memories (TCM), up to 32 kB Instruction (ITCM), up to 32 kB
Data TCM (DTCM).
–Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
–8 kB ETB SRAM.
–Up to 768 kB flash-program memory with 16 kB EEPROM.
•Dual-master, eight-channel GPDMA controlleron the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
•External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
•Serial interfaces:
–USB 2.0 full-speed device/OTG controller with dedicated DMA controller and
on-chip PHY for device and Host (LPC2930/39 only) functions.
–Two-channel CAN controller supporting Full-CAN and extensive message filtering
–Two LIN master controllers with full hardware support for LIN communication.
–Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485
support.
UM10316
Chapter 1: LPC29xx Introductory information
Rev. 3 — 19 October 2010 User manual

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NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
–Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations
deep; Tx FIFO and Rx FIFO.
–Two I2C-bus interfaces.
•Other peripherals:
–Up to three ADCs: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement
range and one, 8-channel 10-bit ADC with 5.0 V measurement range provide a
total of up to 24 analog inputs, with conversion times as low as 2.44 μs per
channel. Each channel provides a compare function to minimize interrupts.
–Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external
signal input.
–Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
–Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality.
–Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
–Quadrature encoder interface that can monitor one external quadrature encoder.
–32-bit watchdog with timer change protection, running on safe clock.
•Up to 108 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper.
•Vectored Interrupt Controller (VIC) with 16 priority levels.
•Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake-up
features.
•Configurable clock-out pin for driving external system clocks.
•Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
•Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
•Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules:
–On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring.
–On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz - max. PLL input 25 MHz.
–On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
–Generation of up to 11 base clocks.
–Seven fractional dividers.
•Highly configurable system Power Management Unit (PMU):
clock control of individual modules.
allows minimization of system operating power consumption in any configuration.
•Standard ARM test and debug interface with real-time in-circuit emulator.
•Boundary-scan test supported.
•ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage.
•Dual power supply:

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NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
–CPU operating voltage: 1.8 V ±5%.
–I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
•Available in 100-pin,144-pin, and 208-pin LQFP packages.
•−40 °C to 85 °C ambient operating temperature range.
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC2917FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2919FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2921FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2923FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2925FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2926FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2927FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2929FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 ×20 ×1.4 mm SOT486-1
LPC2930FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1
LPC2939FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1

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UM10316 © NXP B.V. 2010. All rights reserved. User manual Rev. 3 — 19 October 2010 6 of 566 NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
4.1 Ordering options
Remark: Note that parts LPC2927 and LPC2929 are not fully pin compatible with parts LPC2917/01 and LPC2919/01 or
LPC2917 and LPC2919. On the LPC2927/29 the MSCSS and timer blocks have a reduced pinout.
4.2 Comparison with LPC2917/19 devices
Table 2. LPC29xx part overview
Part
number Flash SRAM (incl
ETB)
TCM
(I/D) CAN LIN/ UART Pins UART RS485 SPI 3V3 ADC 5 V ADC SMC USB device USB host USB OTG ETM QEI I2C-bus Clkout pin
LPC2939 768 kB 56 kB 32/32 kB 2 2 208 2 3 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes
LPC2930 - 56 kB 32/32 kB 2 2 208 2 3 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes
LPC2929 768 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2927 512 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2926 256 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2925 512 kB 40 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2923 256 kB 24 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2921 128 kB 24 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2919/01 768 kB 56 kB 16/16 kB 2 2 144 2 3 2 No Yes No No No Yes Yes Yes Yes
LPC2917/01 512 kB 56 kB 16/16 kB 2 2 144 2 3 2 No Yes No No No Yes Yes Yes Yes
Table 3. Feature comparison
Parts GPDMA UART
RS485
mode
I2C QEI CAN LIN USB
OTG/
device
Flash EEPROM SRAM
total ETB SRAM 5V ADC
LPC2917/19 no no no no 2 2 no 512/768 kB no 80 kB no no
LPC2917/19/01 yes yes yes yes 2 2 no 512/768 kB yes 88 kB 8 kB no
LPC2927/29 yes yes yes yes 2 2 yes 512/768 kB yes 120 kB 8 kB yes

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User manual Rev. 3 — 19 October 2010 7 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
4.3 LPC29xx USB options
Table 4. LPC29xx USB options
Part On-chip controller Ports On-chip PHY
Device Host OTG
LPC2917/01 - - - - -
LPC2919/01 - - - - -
LPC2921 Full-speed - - 1 Device
LPC2923 Full-speed - - 1 Device
LPC2925 Full-speed - - 1 Device
LPC2926 Full-speed - Full-speed 1 Device
LPC2927 Full-speed - Full-speed 1 Device
LPC2929 Full-speed - Full-speed 1 Device
LPC2930 Full-speed Full-speed Full-speed 2 Device, host
LPC2939 Full-speed Full-speed Full-speed 2 Device, host

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User manual Rev. 3 — 19 October 2010 8 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
5. Block diagram
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 1. LPC2917/19/01 block diagram
002aad959
ARM968E-S
DTCM
16 kB
ITCM
16 kB
TEST/DEBUG
INTERFACE
slave
slave
slave
slave
slave
slave
slave
slave
EXTERNAL STATIC
MEMORY CONTROLLER
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
512/768 kB 16 kB EEPROM
EMBEDDED SRAM 32 kB
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
LIN0/1
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/2/3
TIMER 0/1/2/3
SPI0/1/2
RS485 UART0/1
WDT
master
master
slave
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
AHB TO APB
BRIDGE
CLOCK
GENERATION
UNIT CGU0/1
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT
LPC2917/01
LPC2919/01
JTAG
interface
8 kB SRAM
slave
slave
1 ×master
2 × slave
AHB
MULTI
LAYER
MATRIX

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NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 2. LPC2921/23/25 block diagram
EMBEDDED FLASH
512/256/128 kB
002aae224
ARM968E-S
DTCM
16 kB
ITCM
16 kB
TEST/DEBUG
INTERFACE
slave
master
1 master
2 slaves
master GPDMA CONTROLLER
GPDMA REGISTERS
16 kB
EEPROM
EMBEDDED SRAM 16 kB
(LPC2925 only)
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/5
TIMER 0/1/2/3
SPI0/1/2
RS-485 UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER master
slave USB DEVICE
CONTROLLER
slave
slave
slave
slave
slave
slave
slave
slave
slave
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
UART/LIN0/1
AHB TO APB
BRIDGE
AHB
MULTI-
LAYER
MATRIX
LPC2921/2923/2925
JTAG
interface
8 kB SRAM
general subsystem
power, clock, and
reset subsystem
MSC subsystem
networking subsystem
peripheral subsystem
CLOCK
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 10 of 566
NXP Semiconductors UM10316
Chapter 1: LPC29xx Introductory information
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 3. LPC2926/27/29 block diagram
002aae143
ARM968E-S
DTCM
32 kB
ITCM
32 kB
TEST/DEBUG
INTERFACE
slave
master
1 master
2 slaves
master
EXTERNAL STATIC
MEMORY CONTROLLER
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
512/768 kB 16 kB EEPROM
EMBEDDED SRAM 32 kB
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
UART/LIN0/1
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/2/3/5
TIMER 0/1/2/3
SPI0/1/2
RS485 UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER master
slave USB OTG/DEVICE
CONTROLLER
slave
slave
slave
slave
slave
slave
slave
slave
slave
slave
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
5 V ADC0
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
AHB TO APB
BRIDGE
CLOCK
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT
AHB
MULTI-
LAYER
MATRIX
LPC2926/27/2929
JTAG
interface
8 kB SRAM
general subsystem
power. clock, and
reset subsystem
MSC subsystem
networking subsystem
peripheral subsystem

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Chapter 1: LPC29xx Introductory information
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 4. LPC2930 block diagram
002aae257
ARM968E-S
DTCM
32 kB
ITCM
32 kB
TEST/DEBUG
INTERFACE
slave
master
1 master
2 slaves
master
EXTERNAL STATIC
MEMORY CONTROLLER
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED SRAM 32 kB
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
UART/LIN0/1
PWM0/1/2/3
3.3 V ADC1/2
EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/2/3/4/5
TIMER 0/1/2/3
SPI0/1/2
RS485 UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER master
slave USB HOST/OTG/DEVICE
CONTROLLER
slave
slave
slave
slave
slave
slave
slave
slave
slave
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
5 V ADC0
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
AHB TO APB
BRIDGE
CLOCK
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT
AHB
MULTI-
LAYER
MATRIX
LPC2930
JTAG
interface
8 kB SRAM
general subsystem
power. clock, and
reset subsystem
MSC subsystem
networking subsystem
peripheral subsystem

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Chapter 1: LPC29xx Introductory information
Grey-shaded blocks represent peripherals with connections to the GPDMA.
Fig 5. LPC2939 block diagram
002aae254
ARM968E-S
DTCM
32 kB
ITCM
32 kB
TEST/DEBUG
INTERFACE
slave
master
1 master
2 slaves
master
EXTERNAL STATIC
MEMORY CONTROLLER
GPDMA CONTROLLER
GPDMA REGISTERS
EMBEDDED FLASH
768 kB 16 kB EEPROM
EMBEDDED SRAM 32 kB
SYSTEM CONTROL
TIMER0/1 MTMR
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
UART/LIN0/1
PWM0/1/2/3
3.3 V ADC1/2 EVENT ROUTER
EMBEDDED SRAM 16 kB
GENERAL PURPOSE I/O
PORTS 0/1/2/3/4/5
TIMER 0/1/2/3
SPI0/1/2
RS485 UART0/1
WDT
AHB TO APB
BRIDGE
AHB TO DTL
BRIDGE
VECTORED
INTERRUPT
CONTROLLER master
slave USB HOST/OTG/DEVICE
CONTROLLER
slave
slave
slave
slave
slave
slave
slave
slave
slave
slave
AHB TO DTL
BRIDGE
AHB TO APB
BRIDGE
5 V ADC0
QUADRATURE
ENCODER
CHIP FEATURE ID
AHB TO APB
BRIDGE
I2C0/1
AHB TO APB
BRIDGE
CLOCK
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
RESET
GENERATION
UNIT
AHB
MULTI-
LAYER
MATRIX
LPC2939
JTAG
interface
8 kB SRAM
general subsystem
power. clock, and
reset subsystem
MSC subsystem
networking subsystem
peripheral subsystem

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Chapter 1: LPC29xx Introductory information
6. Functional blocks
This chapter gives an overview of the functional blocks, clock domains, and power modes.
See Table 1–2 for availability of peripherals and blocks for specific LPC29xx parts.
The functional blocks are explained in detail in the following chapters. Several blocks are
gathered into subsystems and one or more of these blocks and/or subsystems are put into
a clock domain. Each of these clock domains can be configured individually for power
management (i.e. clock on or off and whether the clock responds to sleep and wake-up
events).
Table 5. Functional blocks and clock domains
Short Description Comment
Clock domain AHB
ARM ARM9TDMI-S 32-bit RISC processor
SMC Static Memory Controller For external (static) memory banks
SRAM Internal Static Memory -
Clock domain Flash
Flash - Internal Flash Memory
FMC Flash Memory Controller Controller for the internal flash memory
Clock domain USB
USB USB OTG controller -
Clock domain DMA controller
GPDMA General Purpose DMA
controller
Clock domain VIC
VIC Vectored Interrupt Controller Prioritized/vectored interrupt handling
Clock domain general subsystem
CFID Digital Chip ID Identifies the device and its possibilities
ER Event Router Routes wake-up events and external
interrupts (to CGU/VIC)
SCU System Control Unit Configures memory map and I/O
functions
Clock domain peripheral subsystem
GPIO General-Purpose
Input/Output Directly controls I/O pins
TMR Timer Provides match output and capture
inputs
UART Universal Asynchronous
Receiver/Transmitter Standard 550 serial port
WDT Watchdog Timer to guard (software) execution
SPI Serial Peripheral Interface Supports various industry-standard SPI
protocols
Clock domain modulation and sampling-control subsystem
ADC Analog-to-Digital Converter 10-bit Analog-to-Digital Converter
PWM Pulse-Width Modulator Synchronized Pulse-Width Modulator

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Chapter 1: LPC29xx Introductory information
7. Architectural overview
The LPC29xx consists of:
•An ARM968E-S processor with real-time emulation support
•An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
•Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem).
•Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
•One ARM Peripheral Bus for event router and system control.
The LPC29xx configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the APB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
8. ARM968E-S processor
The ARM968E-S is a general purpose 32-bit RISC processor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective controller
core.
TMR Timer Dedicated Sampling and Control Timer
QEI Quadrature encoder
interface -
Clock domain networking subsystem
CAN Gateway Includes acceptance filter
LIN Master controller LIN master controller
I2C I2C-bus
Clock domain power control subsystem
CGU0 Clock Generation Unit Controls clock sources and clock
domains
CGU1 clock generation unit USB clocks and clock out
RGU reset generation unit -
PMU power management unit -
Table 5. Functional blocks and clock domains …continued
Short Description Comment

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Chapter 1: LPC29xx Introductory information
Amongst the most compelling features of the ARM968E-S are:
•Separate directly connected instruction and data Tightly Coupled Memory (TCM)
interfaces
•Write buffers for the AHB and TCM buses
•Enhanced 16 ×32 multiplier capable of single-cycle MAC operations and 16-bit fixed-
point DSP instructions to accelerate signal-processing algorithms and applications.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline
architecture. Typically, in a three-stage pipeline architecture, while one instruction is being
executed its successor is being decoded and a third instruction is being fetched from
memory. In the five-stage pipeline additional stages are added for memory access and
write-back cycles.
The ARM968E-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions or to applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM968E-S processor has two instruction sets:
•Standard 32-bit ARMv5TE set
•16-bit THUMB set
The THUMB set's 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM's performance advantage over a
traditional 16-bit controller using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM controller connected to a 16-bit memory system.
The ARM968E-S processor is described in detail in the ARM968E-S data sheet.
9. On-chip flash memory system
The LPC29xx includes up to 768 kB flash memory. This memory can be used for both
code and data storage. Flash memory can be programmed in-system via a serial port
(e.g., CAN).
10. On-chip static RAM
In addition to the two 16 kB or 32 kB TCMs, the LPC29xx includes two static RAM
memories: one of up to 32 kB and one of 16 kB. Both may be used for code and/or data
storage.

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 16 of 566
1. How to read this chapter
The memory configuration varies for the different LPC29xx parts (see Table 2–6). In
addition to the memory blocks, peripheral register blocks in memory region 7 are available
only if the peripheral is implemented. See Table 2–7 for part specific registers. All other
peripheral registers are available on all LPC29xx parts.
2. Memory-map view of the AHB
The LPC29xx uses an AHB multilayer bus with the CPU and the GPDMA as the bus
masters. The AHB slaves are connected to the AHB-lite multilayer bus.The ARM968E-S
CPU has access to all AHB slaves and hence to all address regions.
UM10316
Chapter 2: LPC29xx memory mapping
Rev. 3 — 19 October 2010 User manual
Table 6. LPC29xx memory configurations
Part number Flash SRAM TCM (I/D) SMC
SRAM @
0x8000 0000 SRAM @ 0x8000 8000 ETB (8 kB)
LPC2917/01 512 kB 32 kB 16 kB yes 16/16 kB 8 banks, 16 MB each
LPC2919/01 768 kB 32 kB 16 kB yes 16/16 kB 8 banks, 16 MB each
LPC2921 128 kB 16 kB - yes 16/16 kB -
LPC2923 256 kB 16 kB - yes 16/16 kB -
LPC2925 512 kB 16 kB 16 kB yes 16/16 kB -
LPC2926 256 kB 32 kB 16 kB yes 32/32 kB 8 banks, 16 MB each
LPC2927 512 kB 32 kB 16 kB yes 32/32 kB 8 banks, 16 MB each
LPC2929 768 kB 32 kB 16 kB yes 32/32 kB 8 banks, 16 MB each
LPC2930 - 32 kB 16 kB yes 32/32 kB 8 banks, 16 MB each
LPC2939 768 kB 32 kB 16 kB yes 32/32 kB 8 banks, 16 MB each
Table 7. LPC29xx configuration of peripheral registers
Part number peripheral
cluster #2 peripheral cluster #6 AHB peripherals
GPIO ADC0 ADC1 ADC2 USB
LPC291719/01 GPIO0/1/2/3 no yes yes no
LPC2919/01 GPIO0/1/2/3 no yes yes no
LPC2921 GPIO0/1/5 no yes yes yes
LPC2923 GPIO0/1/5 no yes yes yes
LPC2925 GPIO0/1/5 no yes yes yes
LPC2927 GPIO0/1/2/3/5 yes yes yes yes
LPC2929 GPIO0/1/2/3/5 yes yes yes yes
LPC2930 GPIO0/1/2/3/4/5 yes yes yes yes
LPC2939 GPIO0/1/2/3/4/5 yes yes yes yes

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 17 of 566
NXP Semiconductors UM10316
Chapter 2: LPC29xx memory mapping
3. Memory-map regions
The ARM9 processor has a 4 GB of address space. The LPC29xx has divided this
memory space into eight regions of 512 MB each. Each region is used for a dedicated
purpose.
An exception to this is region 0; several of the other regions (or a part of it) can be
shadowed in the memory map at this region. This shadowing can be controlled by
software via the programmable re-mapping registers (see Table 6–64).
Figure 2–6 gives a graphical overview of the LPC29xx memory map.
Table 8. LPC29xx memory regions
Memory region # Address Description
0 0x0000 0000 TCM area and shadow area
1 0x2000 0000 embedded flash area
2 0x4000 0000 external static memory area
3 0x6000 0000 external static memory controller area
4 0x8000 0000 internal SRAM area
5 0xA000 0000 not used
6 0xC000 0000 not used
7 0xE000 0000 bus-peripherals area

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UM10316 © NXP B.V. 2010. All rights reserved. User manual Rev. 3 — 19 October 2010 18 of 566 NXP Semiconductors UM10316
Chapter 2: LPC29xx memory mapping
(1) See Section 2–1 for part-specific implementation. Gray-shaded memory regions are accessible by the GPDMA controller.
Fig 6. LPC29xx system memory map: graphical overview
16 MB ext.static memory bank 0(1)
16 MB ext.static memory bank 1(1)
ext.static memory banks 7 to 2(1)
reserved
DMA interface toTCM
PCR/VIC control
0x0000 0000
0 GB
1 GB
4 GB
2 GB
0x4000 0000
0x4100 0000
0x4300 0000
0x4200 0000
0x2000 0000
0x6000 0000
0x6000 4000
0x8000 0000
0x8000 8000
0x8000 C000
0xE000 0000
0xE002 0000
0xE004 0000
0xE006 0000
0xE008 0000
0xE00A 0000
0xE00C 0000
0xE00E 0000
0xE010 0000
0xE014 0000
0xE018 3000
0xF000 0000
0xF080 0000
0xFFFF 8000
0xFFFF FFFF
reserved
reserved
reserved
reserved
reserved
reserved
reserved
peripheral subsystem #0
peripheral subsystem #2
peripheral subsystem #4
peripheral subsystem #6
0xE018 2000
0xE018 0000
32 kB AHB SRAM(1)
16 kB AHB SRAM(1)
reserved
USB controller(1)
DMA controller
8 kB ETB SRAM
ETB control
reserved
ITCM/DTCM
on-chip flash(1)
0x2020 4000
0x0000 0000
0x0040 0000
0x0000 8000
0x0040 8000
0x0080 0000
0x2000 0000
32 kB(1) ITCM
32 kB(1) DTCM
reserved
reserved
no physical memory
peripherals #6
MSCSS
subsystem
ITCM/DTCM
memory
EMI/SMC(1)
peripherals #2
peripheral
subsystem
0xE004 1000
0xE004 2000
0xE004 3000
0xE004 4000
0xE004 6000
0xE004 8000
0xE004 A000
0xE004 B000
0xE004 D000
0xE005 0000
0xE006 0000
0xE004 C000
0xE004 9000
0xE004 7000
0xE004 5000
0xE004 0000
SPI0
WDT
TIMER0
TIMER1
TIMER2
TIMER3
UART0
UART1
SPI1
SPI2
GPIO0
GPIO1
GPIO2(1)
GPIO3 to GPIO5(1)
peripherals #0
general
subsystem
0xE000 1000
0xE000 2000
0xE000 3000
0xE002 0000
0xE000 0000
CFID
SCU
event router
peripherals #4
networking
subsystem
0xE008 1000
0xE008 0000
CAN0
CAN1 0xE008 2000
0xE008 3000
0xE008 4000
0xE008 7000
0xE008 9000
0xE008 B000
0xE00A 0000
0xE008 A000
0xE008 8000
0xE008 6000
I2C0
I2C1
reserved
CAN ID LUT
CAN common regs
LIN0
LIN1
CAN AF regs
0xE00C 0000
0xE00C 1000
0xE00C 2000
0xE00C 3000
0xE00C 4000
0xE00C 5000
0xE00C 6000
0xE00C 7000
0xE00C 8000
0xE00C 9000
0xE00C A000
0xE00E 0000
ADC0 (5V)(1)
ADC1
ADC2
PWM0
PWM1
PWM3
quadrature encoder
PWM2
MSCSS timer0
MSCSS timer1
PCR/VIC
subsystem
0xFFFF 8000
0xFFFF 9000
0xFFFF A000
0xFFFF B000
0xFFFF C000
0xFFFF F000
0xFFFF FFFF
PMU
CGU1
reserved
reserved
reserved
reserved
reserved
VIC
CGU0
RGU
512 MB shadow area
remappable to
shadow area
LPC29xx
768 kB(1) on-chip
flash
flash controller
0x2000 0000
reserved
0x200C 0000
0x2020 0000
0x2020 4000
flash
memory

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 19 of 566
NXP Semiconductors UM10316
Chapter 2: LPC29xx memory mapping
3.1 Region 0: TCM/shadow area
The ARM968E-S processor has its exception vectors located at address logic 0. Since
flash is the only non-volatile memory available in the LPC29xx, the exception vectors in
the flash must be located at address logic 0 at reset (AHB_RST).
After booting a choice must be made for region 0. When enabled, the Tightly Coupled
Memories (TCMs) occupy fixed address locations in region 0 as indicated in Figure 2–6.
Information on how to enable the TCMs can be found in the ARM documentation, see
Ref. 31–2.
To enable memory re-mapping, the LPC29xx AHB system memory map provides a
shadow area (region 0) starting at address logic 0. This is a virtual memory region, i.e. no
actual memory is present at the shadow area addresses. A selectable region of the AHB
system memory map is, apart from its own specific region, also accessible via this shadow
area region.
Fig 7. Region 0 memory map
Region #0:TCM area
0x0000_0000 - 0x1FFF_FFFF
(Offset Address
0x0000 0000
0x1FFF FFFF
0x0000 4000/0
0x0040 0000
I-TCM region aliasses
I-TCM (16/32 kByte)
0x0080 0000
D-TCM region aliasses
D-TCM (16 kByte)
region #0 no physical memory
0x0040 4000/0

UM10316 © NXP B.V. 2010. All rights reserved.
User manual Rev. 3 — 19 October 2010 20 of 566
NXP Semiconductors UM10316
Chapter 2: LPC29xx memory mapping
After reset, the region 1 embedded flash area is always available at the shadow area.
After booting, any other region of the AHB system memory map (e.g. internal SRAM) can
be re-mapped to region 0 by means of the shadow memory mapping register. For more
details about the shadow area see Table 6–64.
3.2 Region 1: embedded flash area
Figure 2–8 gives a graphical overview of the embedded flash memory map.
Region 1 is reserved for the embedded flash. A data area of 2 Mbyte (to be prepared for a
larger flash-memory instance) and a configuration area of 4 kB are reserved for each
embedded flash instance. Although the LPC29xx contains only one embedded flash
instance, the memory aperture per instance is defined at 4 Mbyte.
3.3 Region 2: external static memory area
Region 2 is reserved for the external static memory. The LPC29xx provides I/O pins for
eight bank-select signals and 24 address lines. This implies that eight memory banks of
16 Mbytes each can be addressed externally.
3.4 Region 3: external static memory controller area
The external Static-Memory Controller configuration area is located at region 3
3.5 Region 4: internal SRAM area
Figure 2–6 gives a graphical overview of the internal SRAM memory map.
Fig 8. Region 1 embedded flash memory
+ 0x00000000
+ 0x1FFFFFFF
+ 0x00200000
FLASH IF1
Configuration Area (4 Kbyte)
+ 0x00200FFF
Embedded FLASH
memory area
512 Kbyte -
768 Kbyte
+ 0x0007FFFF - 0x000BFFF