Texas Instruments TMS320F28004x Product manual

TMS320F28004x Piccolo Microcontrollers
Technical Reference Manual
Literature Number: SPRUI33
November 4 2015–Revised January 2017

2SPRUI33–November 4 2015–Revised January 2017
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Contents
Contents
Preface....................................................................................................................................... 68
1 C28x Processor.................................................................................................................. 69
1.1 Overview..................................................................................................................... 70
1.1.1 Floating-Point Unit ................................................................................................ 70
1.1.2 Trigonometric Math Unit ......................................................................................... 70
1.1.3 Viterbi, Complex Math and CRC Unit (VCU) .................................................................. 71
2 System Control .................................................................................................................. 73
2.1 Introduction.................................................................................................................. 74
2.2 Power Management........................................................................................................ 74
2.2.1 Internal 1.2-V Switching Regulator (DC-DC) .................................................................. 74
2.3 Device Identification and Configuration Registers ..................................................................... 75
2.4 Resets ....................................................................................................................... 75
2.4.1 Reset Sources..................................................................................................... 75
2.4.2 External Reset (XRS)............................................................................................. 75
2.4.3 Power-On Reset (POR) .......................................................................................... 76
2.4.4 Debugger Reset (SYSRS) ....................................................................................... 76
2.4.5 Watchdog Reset (WDRS)........................................................................................ 76
2.4.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 76
2.4.7 DCSM Safe Code Copy Reset (SCCRESET)................................................................. 76
2.5 Peripheral Interrupts ....................................................................................................... 77
2.5.1 Interrupt Concepts................................................................................................. 77
2.5.2 Interrupt Architecture.............................................................................................. 77
2.5.3 Interrupt Entry Sequence......................................................................................... 78
2.5.4 Configuring and Using Interrupts................................................................................ 79
2.5.5 PIE Channel Mapping ............................................................................................ 81
2.5.6 Vector Tables...................................................................................................... 82
2.6 Exceptions and Non-Maskable Interrupts............................................................................... 89
2.6.1 Configuring and Using NMIs..................................................................................... 89
2.6.2 Emulation Considerations........................................................................................ 89
2.6.3 NMI Sources ....................................................................................................... 89
2.6.4 Illegal Instruction Trap (ITRAP).................................................................................. 90
2.6.5 Error Pin............................................................................................................ 90
2.7 Clocking ..................................................................................................................... 91
2.7.1 Clock Sources ..................................................................................................... 91
2.7.2 Derived Clocks..................................................................................................... 94
2.7.3 Device Clock Domains............................................................................................ 94
2.7.4 XCLKOUT.......................................................................................................... 95
2.7.5 Clock Connectivity................................................................................................. 95
2.7.6 Clock Source and PLL Setup.................................................................................... 97
2.7.7 Missing Clock Detection.......................................................................................... 99
2.8 32-Bit CPU Timers 0/1/2................................................................................................. 101
2.9 Watchdog Timer .......................................................................................................... 102
2.9.1 Servicing the Watchdog Timer................................................................................. 102
2.9.2 Minimum Window Check ....................................................................................... 103
2.9.3 Watchdog Reset or Watchdog Interrupt Mode............................................................... 103

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2.9.4 Watchdog Operation in Low Power Modes .................................................................. 104
2.9.5 Emulation Considerations ...................................................................................... 104
2.10 Low Power Modes........................................................................................................ 105
2.10.1 IDLE .............................................................................................................. 105
2.10.2 STANDBY ....................................................................................................... 105
2.10.3 HALT ............................................................................................................. 106
2.10.4 Flash Power-down Considerations........................................................................... 106
2.11 Memory Controller Module .............................................................................................. 108
2.11.1 Functional Description ......................................................................................... 108
2.12 Flash and OTP Memory ................................................................................................. 115
2.12.1 Features.......................................................................................................... 115
2.12.2 Flash Tools ...................................................................................................... 115
2.12.3 Default Flash Configuration ................................................................................... 116
2.12.4 Flash Bank, OTP and Pump .................................................................................. 116
2.12.5 Flash Module Controller (FMC)............................................................................... 116
2.12.6 Flash and OTP and Wakeup Power-Down Modes......................................................... 117
2.12.7 Flash and OTP Performance.................................................................................. 118
2.12.8 Flash Access Interface......................................................................................... 118
2.12.9 Erase/Program Flash........................................................................................... 121
2.12.10 Error Correction Code (ECC) Protection................................................................... 122
2.12.11 Reserved Locations Within Flash and OTP ............................................................... 125
2.12.12 Procedure to Change the Flash Control Registers ....................................................... 125
2.13 Dual Code Security Module (DCSM)................................................................................... 126
2.13.1 Functional Description ......................................................................................... 126
2.13.2 CSM Impact on Other On-Chip Resources ................................................................. 135
2.13.3 Incorporating Code Security in User Applications.......................................................... 137
2.14 Registers................................................................................................................... 142
2.14.1 System Control Base Addresses ............................................................................. 142
3 ROM Code and Peripheral Booting ..................................................................................... 534
3.1 Introduction ................................................................................................................ 535
3.2 Device Boot Philosophy.................................................................................................. 535
3.3 Device Boot Modes....................................................................................................... 535
3.3.1 Configuring Alternate Boot Mode Pins........................................................................ 536
3.3.2 Configuring Alternate Boot Mode Options.................................................................... 537
3.3.3 Boot Mode Example Use Cases............................................................................... 538
3.4 Device Boot Flow Diagrams............................................................................................. 540
3.4.1 Emulation Boot Flow Diagram ................................................................................. 541
3.4.2 Standalone Boot Flow Diagram................................................................................ 542
3.5 Device Reset and Exception Handling................................................................................. 543
3.5.1 Reset Causes and Handling.................................................................................... 543
3.5.2 Exceptions and Interrupts Handling ........................................................................... 543
3.6 Boot ROM Description ................................................................................................... 544
3.6.1 Boot ROM Registers ............................................................................................ 544
3.6.2 Boot ROM User OTP............................................................................................ 544
3.6.3 Entry Points....................................................................................................... 544
3.6.4 Wait Points........................................................................................................ 545
3.6.5 Memory Maps .................................................................................................... 545
3.6.6 ROM Tables...................................................................................................... 546
3.6.7 Boot Modes....................................................................................................... 547
3.6.8 Boot Data Stream Structure.................................................................................... 559
3.6.9 GPIO Assignments .............................................................................................. 561
3.6.10 DCSM Usage.................................................................................................... 562
3.6.11 Clock Initialization............................................................................................... 563

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3.6.12 Boot Status Information........................................................................................ 563
3.6.13 ROM Version.................................................................................................... 564
3.7 Application Notes for Using the Bootloaders.......................................................................... 565
3.7.1 The C2000 Hex Utility........................................................................................... 565
4 Control Law Accelerator (CLA)........................................................................................... 567
4.1 Control Law Accelerator (CLA) Overview ............................................................................. 568
4.2 CLA Interface.............................................................................................................. 570
4.2.1 CLA Memory ..................................................................................................... 570
4.2.2 CLA Memory Bus................................................................................................ 571
4.2.3 Shared Peripherals and EALLOW Protection................................................................ 571
4.2.4 CLA Tasks and Interrupt Vectors.............................................................................. 572
4.2.5 CLA Software Interrupt to CPU ................................................................................ 575
4.3 CLA, DMA, and CPU Arbitration........................................................................................ 575
4.3.1 CLA, DMA, and CPU Arbitration............................................................................... 575
4.3.2 CLA Message RAM ............................................................................................. 575
4.4 CLA Configuration and Debug .......................................................................................... 577
4.4.1 Building a CLA Application ..................................................................................... 577
4.4.2 Typical CLA Initialization Sequence........................................................................... 577
4.4.3 Debugging CLA Code........................................................................................... 579
4.4.4 CLA Illegal Opcode Behavior .................................................................................. 580
4.4.5 Resetting the CLA ............................................................................................... 581
4.5 Pipeline..................................................................................................................... 582
4.5.1 Pipeline Overview................................................................................................ 582
4.5.2 CLA Pipeline Alignment......................................................................................... 582
4.5.3 Parallel Instructions.............................................................................................. 586
4.6 Instruction Set............................................................................................................. 587
4.6.1 Instruction Descriptions ......................................................................................... 587
4.6.2 Addressing Modes and Encoding.............................................................................. 589
4.6.3 Instructions ....................................................................................................... 591
4.7 Registers................................................................................................................... 705
4.7.1 Control Law Accelerator Base Addresses.................................................................... 705
5 CLA Program ROM (CLAPROMCRC)................................................................................... 774
5.1 Overview................................................................................................................... 775
5.2 Functional Description.................................................................................................... 775
5.2.1 Start Address..................................................................................................... 775
5.2.2 Seed............................................................................................................... 775
5.2.3 Halt ................................................................................................................ 776
5.2.4 Result and Comparison......................................................................................... 776
6 General-Purpose Input/Output (GPIO) ................................................................................. 777
6.1 GPIO Overview ........................................................................................................... 778
6.2 Configuration Overview .................................................................................................. 779
6.3 Digital General-Purpose I/O Control.................................................................................... 780
6.4 Input Qualification......................................................................................................... 780
6.4.1 No Synchronization (Asynchronous Input) ................................................................... 780
6.4.2 Synchronization to SYSCLK Only ............................................................................. 781
6.4.3 Qualification Using a Sampling Window...................................................................... 781
6.5 GPIO and Peripheral Muxing............................................................................................ 784
6.6 Internal Pull-up Configuration Requirements.......................................................................... 784
6.7 Registers................................................................................................................... 786
6.7.1 GPIO Base Addresses.......................................................................................... 786
7 Crossbar (X-BAR) ............................................................................................................. 867
7.1 GPIO Input X-BAR........................................................................................................ 868

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7.2 ePWM and GPIO Output X-BAR ....................................................................................... 869
7.2.1 ePWM X-BAR .................................................................................................... 869
7.2.2 GPIO Output X-BAR............................................................................................. 872
7.2.3 X-BAR Flags...................................................................................................... 873
7.3 X-BAR Registers.......................................................................................................... 875
7.3.1 Crossbar Base Addresses...................................................................................... 875
8 Direct Memory Access (DMA)........................................................................................... 1097
8.1 Introduction............................................................................................................... 1098
8.2 Architecture .............................................................................................................. 1099
8.2.1 Block Diagram .................................................................................................. 1099
8.2.2 Peripheral Interrupt Event Trigger Sources................................................................. 1099
8.2.3 DMA Bus ........................................................................................................ 1103
8.3 Pipeline Timing and Throughput ...................................................................................... 1103
8.4 CPU and CLA Arbitration............................................................................................... 1104
8.5 Channel Priority.......................................................................................................... 1105
8.5.1 Round-Robin Mode ............................................................................................ 1105
8.5.2 Channel 1 High Priority Mode ................................................................................ 1106
8.6 Address Pointer and Transfer Control................................................................................ 1106
8.7 Overrun Detection Feature............................................................................................. 1111
8.8 Registers ................................................................................................................. 1112
8.8.1 DMA Base Addresses ......................................................................................... 1112
9 Analog Subsystem.......................................................................................................... 1145
9.1 Analog Subsystem ...................................................................................................... 1146
9.1.1 Features ........................................................................................................ 1146
9.1.2 Block Diagram .................................................................................................. 1146
9.2 Registers ................................................................................................................. 1154
9.2.1 Analog Subsystem Base Addresses......................................................................... 1154
10 Analog-to-Digital Converter (ADC)..................................................................................... 1169
10.1 Analog-to-Digital Converter (ADC).................................................................................... 1170
10.1.1 Features........................................................................................................ 1170
10.1.2 ADC Block Diagram........................................................................................... 1171
10.1.3 ADC Configurability........................................................................................... 1172
10.1.4 SOC Principle of Operation.................................................................................. 1173
10.1.5 SOC Configuration Examples ............................................................................... 1176
10.1.6 ADC Conversion Priority ..................................................................................... 1178
10.1.7 Burst Mode..................................................................................................... 1181
10.1.8 EOC and Interrupt Operation................................................................................ 1183
10.1.9 Post-Processing Blocks ...................................................................................... 1184
10.1.10 Power-Up Sequence ........................................................................................ 1187
10.1.11 ADC Calibration.............................................................................................. 1187
10.2 ADC Timings............................................................................................................. 1188
10.2.1 ADC Timing Diagrams........................................................................................ 1188
10.3 Additional Information................................................................................................... 1189
10.3.1 Ensuring Synchronous Operation........................................................................... 1189
10.3.2 Choosing an Acquisition Window Duration ................................................................ 1193
10.3.3 Achieving Simultaneous Sampling.......................................................................... 1193
10.3.4 Designing an External Reference Circuit .................................................................. 1194
10.3.5 Internal Temperature Sensor................................................................................ 1194
10.4 Registers ................................................................................................................. 1195
10.4.1 Analog to Digital Base Addresses .......................................................................... 1195
11 Programmable Gain Amplifier (PGA) ................................................................................. 1342
11.1 Programmable Gain Amplifier (PGA) Overview..................................................................... 1343

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11.1.1 Features........................................................................................................ 1343
11.1.2 Block Diagram................................................................................................. 1343
11.2 Linear Output Range.................................................................................................... 1344
11.3 Gain Modes .............................................................................................................. 1344
11.4 External Filtering ........................................................................................................ 1344
11.5 Error Calibration......................................................................................................... 1345
11.5.1 Offset Error..................................................................................................... 1345
11.5.2 Gain Error ...................................................................................................... 1345
11.6 Ground Routing.......................................................................................................... 1346
11.7 Lock Register ............................................................................................................ 1347
11.8 Examples................................................................................................................. 1348
11.8.1 Direct Amplifier ................................................................................................ 1348
11.8.2 RC Filter........................................................................................................ 1348
11.9 Analog Front End Integration.......................................................................................... 1348
11.9.1 ADC............................................................................................................. 1349
11.9.2 CMPSS ......................................................................................................... 1349
11.9.3 Buffered DAC.................................................................................................. 1349
11.9.4 Alternate Functions ........................................................................................... 1350
11.10 Registers................................................................................................................. 1351
11.10.1 Programmable Gain Amplifier Base Addresses ......................................................... 1351
12 Buffered Digital-to-Analog Converter (DAC) ....................................................................... 1360
12.1 Buffered Digital-to-Analog Converter (DAC) Overview............................................................. 1361
12.1.1 Features........................................................................................................ 1361
12.1.2 Block Diagram................................................................................................. 1361
12.2 Using the DAC........................................................................................................... 1361
12.2.1 Initialization Sequence........................................................................................ 1362
12.3 Lock Registers........................................................................................................... 1362
12.4 Registers ................................................................................................................. 1362
12.4.1 Buffered DAC Base Addresses ............................................................................. 1362
13 Comparator Subsystem (CMPSS)...................................................................................... 1371
13.1 CMPSS Overview ....................................................................................................... 1372
13.1.1 Features........................................................................................................ 1372
13.1.2 Block Diagram................................................................................................. 1372
13.2 Comparator............................................................................................................... 1373
13.3 Reference DAC.......................................................................................................... 1373
13.4 Ramp Generator......................................................................................................... 1375
13.4.1 Ramp Generator Overview .................................................................................. 1375
13.4.2 Ramp Generator Behavior................................................................................... 1375
13.4.3 Ramp Generator Behavior at Corner Cases............................................................... 1376
13.5 Digital Filter .............................................................................................................. 1377
13.5.1 Filter Initialization Sequence................................................................................. 1377
13.6 Using the CMPSS....................................................................................................... 1378
13.6.1 LATCHCLR, PWMSYNC and PWMBLANK Signals...................................................... 1378
13.6.2 Enabling and Disabling the CMPSS Clock ................................................................ 1378
13.7 Registers ................................................................................................................. 1379
13.7.1 CMPSS Base Addresses..................................................................................... 1379
14 Sigma Delta Filter Module (SDFM)..................................................................................... 1404
14.1 SDFM Module Overview ............................................................................................... 1405
14.1.1 SDFM Features................................................................................................ 1407
14.1.2 Block Diagram................................................................................................. 1408
14.2 Configuring Device Pins................................................................................................ 1413
14.3 Input Control Unit........................................................................................................ 1413
14.4 Primary (Data) Filter Unit............................................................................................... 1414

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14.4.1 32-bit or 16-bit Data Filter Output Representation........................................................ 1416
14.4.2 Data FIFO...................................................................................................... 1416
14.4.3 SDSYNC Event................................................................................................ 1417
14.5 Secondary (Comparator) Filter Unit................................................................................... 1419
14.6 Data Rate and Latency of the Sinc Filter............................................................................. 1420
14.7 Interrupt Unit ............................................................................................................. 1421
14.8 Registers ................................................................................................................. 1424
14.8.1 Sigma Delta Filter Base Addresses......................................................................... 1424
15 Enhanced Pulse Width Modulator (ePWM) ......................................................................... 1482
15.1 Introduction............................................................................................................... 1483
15.1.1 Submodule Overview......................................................................................... 1484
15.2 Configuring Device Pins................................................................................................ 1489
15.3 ePWM Submodules..................................................................................................... 1489
15.3.1 Overview ....................................................................................................... 1489
15.3.2 Time-Base (TB) Submodule ................................................................................. 1491
15.3.3 Counter-Compare (CC) Submodule ........................................................................ 1502
15.3.4 Action-Qualifier (AQ) Submodule ........................................................................... 1508
15.3.5 Dead-Band Generator (DB) Submodule ................................................................... 1523
15.3.6 PWM Chopper (PC) Submodule ........................................................................... 1529
15.3.7 Trip-Zone (TZ) Submodule................................................................................... 1533
15.3.8 Event-Trigger (ET) Submodule.............................................................................. 1538
15.3.9 Digital Compare (DC) Submodule .......................................................................... 1544
15.3.10 EPWM X-BAR................................................................................................ 1551
15.4 Applications to Power Topologies..................................................................................... 1555
15.4.1 Overview of Multiple Modules .............................................................................. 1555
15.4.2 Key Configuration Capabilities .............................................................................. 1555
15.4.3 Controlling Multiple Buck Converters With Independent Frequencies ................................. 1556
15.4.4 Controlling Multiple Buck Converters With Same Frequencies ......................................... 1558
15.4.5 Controlling Multiple Half H-Bridge (HHB) Converters .................................................... 1560
15.4.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)....................................... 1562
15.4.7 Practical Applications Using Phase Control Between PWM Modules.................................. 1565
15.4.8 Controlling a 3-Phase Interleaved DC/DC Converter .................................................... 1566
15.4.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter.................................... 1569
15.4.10 Controlling a Peak Current Mode Controlled Buck Module ............................................ 1570
15.4.11 Controlling H-Bridge LLC Resonant Converter.......................................................... 1571
15.5 Register Lock Protection ............................................................................................... 1572
15.6 Registers ................................................................................................................. 1574
15.6.1 Enhanced Pulse Width Modulator Base Addresses ..................................................... 1574
16 High-Resolution Pulse Width Modulator (HRPWM).............................................................. 1695
16.1 Introduction............................................................................................................... 1696
16.2 Operational Description of HRPWM .................................................................................. 1698
16.2.1 Controlling the HRPWM Capabilities ....................................................................... 1698
16.2.2 Configuring the HRPWM..................................................................................... 1701
16.2.3 Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay ............................... 1702
16.2.4 Principle of Operation......................................................................................... 1702
16.2.5 Deadband High Resolution Operation ..................................................................... 1712
16.2.6 Scale Factor Optimizing Software (SFO) .................................................................. 1713
16.2.7 HRPWM Examples Using Optimized Assembly Code. .................................................. 1713
16.3 Appendix A: SFO Library Software - SFO_TI_Build_V7.lib........................................................ 1719
16.3.1 Scale Factor Optimizer Function - int SFO() .............................................................. 1719
16.3.2 Software Usage ............................................................................................... 1720
17 Enhanced Capture (eCAP)................................................................................................ 1722

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17.1 Introduction............................................................................................................... 1723
17.2 Description ............................................................................................................... 1723
17.3 Configuring Device Pins for the eCAP ............................................................................... 1724
17.4 Capture and APWM Operating Mode ................................................................................ 1725
17.5 Capture Mode Description ............................................................................................. 1726
17.5.1 Event Prescaler................................................................................................ 1727
17.5.2 Edge Polarity Select and Qualifier .......................................................................... 1728
17.5.3 Continuous/One-Shot Control ............................................................................... 1728
17.5.4 32-Bit Counter and Phase Control.......................................................................... 1729
17.5.5 CAP1-CAP4 Registers ....................................................................................... 1730
17.5.6 Using SWSYNC with the ECAP Module ................................................................... 1730
17.5.7 Interrupt Control ............................................................................................... 1731
17.5.8 DMA Interrupt.................................................................................................. 1734
17.5.9 Shadow Load and Lockout Control......................................................................... 1734
17.5.10 APWM Mode Operation..................................................................................... 1734
17.6 Application of the ECAP Module ..................................................................................... 1735
17.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger.................................... 1735
17.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger...................... 1738
17.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger.................................. 1740
17.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger.................... 1742
17.7 Application of the APWM Mode ....................................................................................... 1744
17.7.1 Example 1 - Simple PWM Generation (Independent Channel/s)....................................... 1744
17.8 Registers ................................................................................................................. 1746
17.8.1 Enhanced Capture Base Addresses........................................................................ 1746
18 High Resolution Capture (HRCAP) .................................................................................... 1764
18.1 Introduction to the HRCAP Module ................................................................................... 1765
18.2 Description .............................................................................................................. 1765
18.3 Operational Details...................................................................................................... 1765
18.3.1 HRCAP Clocking.............................................................................................. 1766
18.3.2 HRCAP Initialization Sequence ............................................................................. 1766
18.3.3 HRCAP Interrupts............................................................................................. 1767
18.3.4 HRCAP Calibration............................................................................................ 1767
18.3.5 DriverLib Functions ........................................................................................... 1768
18.4 Known Exceptions....................................................................................................... 1768
18.5 Registers ................................................................................................................. 1769
18.5.1 High-Resolution Capture Base Addresses................................................................. 1769
19 Enhanced QEP (eQEP)..................................................................................................... 1781
19.1 Introduction............................................................................................................... 1782
19.2 Configuring Device Pins................................................................................................ 1784
19.3 Description ............................................................................................................... 1784
19.3.1 EQEP Inputs................................................................................................... 1784
19.3.2 Functional Description........................................................................................ 1785
19.3.3 eQEP Memory Map........................................................................................... 1786
19.4 Quadrature Decoder Unit (QDU)...................................................................................... 1787
19.4.1 Position Counter Input Modes............................................................................... 1787
19.4.2 eQEP Input Polarity Selection............................................................................... 1790
19.4.3 Position-Compare Sync Output ............................................................................. 1790
19.5 Position Counter and Control Unit (PCCU) .......................................................................... 1790
19.5.1 Position Counter Operating Modes ......................................................................... 1790
19.5.2 Position Counter Latch ....................................................................................... 1792
19.5.3 Position Counter Initialization................................................................................ 1794
19.5.4 eQEP Position-compare Unit................................................................................ 1795
19.6 eQEP Edge Capture Unit .............................................................................................. 1796

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19.7 eQEP Watchdog......................................................................................................... 1800
19.8 Unit Timer Base ......................................................................................................... 1800
19.9 QMA Module............................................................................................................. 1801
19.9.1 Modes of Operation........................................................................................... 1801
19.9.2 Interrupt and Error Generation .............................................................................. 1804
19.10 eQEP Interrupt Structure............................................................................................... 1804
19.11 Registers................................................................................................................. 1805
19.11.1 Enhanced QEP Base Addresses.......................................................................... 1805
20 Serial Peripheral Interface (SPI) ........................................................................................ 1840
20.1 SPI Module Overview................................................................................................... 1841
20.1.1 Features........................................................................................................ 1841
20.2 System-Level Integration............................................................................................... 1842
20.2.1 SPI Module Signals........................................................................................... 1842
20.2.2 Configuring Device Pins...................................................................................... 1843
20.2.3 SPI Interrupts .................................................................................................. 1843
20.2.4 DMA Support .................................................................................................. 1845
20.3 SPI Operation............................................................................................................ 1845
20.3.1 Introduction to Operation..................................................................................... 1845
20.3.2 Master Mode................................................................................................... 1846
20.3.3 Slave Mode .................................................................................................... 1847
20.3.4 Data Format.................................................................................................... 1848
20.3.5 Baud Rate Selection ......................................................................................... 1849
20.3.6 SPI Clocking Schemes ....................................................................................... 1850
20.3.7 SPI FIFO Description......................................................................................... 1851
20.3.8 SPI DMA Transfers ........................................................................................... 1852
20.3.9 SPI High-Speed Mode........................................................................................ 1853
20.3.10 SPI 3-Wire Mode Description .............................................................................. 1853
20.4 Programming Procedure ............................................................................................... 1855
20.4.1 Initialization Upon Reset ..................................................................................... 1855
20.4.2 Configuring the SPI ........................................................................................... 1855
20.4.3 Configuring the SPI for High-Speed Mode................................................................. 1856
20.4.4 Data Transfer Example....................................................................................... 1856
20.4.5 SPI STEINV Bit in Digital Audio Transfers................................................................. 1857
20.5 Registers ................................................................................................................. 1859
20.5.1 Serial Peripheral Interface Base Addresses............................................................... 1859
21 Serial Communications Interface (SCI) .............................................................................. 1878
21.1 Enhanced SCI Module Overview...................................................................................... 1879
21.2 Architecture .............................................................................................................. 1881
21.3 SCI Module Signal Summary.......................................................................................... 1881
21.4 Configuring Device Pins................................................................................................ 1881
21.5 Multiprocessor and Asynchronous Communication Modes........................................................ 1881
21.6 SCI Programmable Data Format...................................................................................... 1882
21.7 SCI Multiprocessor Communication .................................................................................. 1882
21.7.1 Recognizing the Address Byte .............................................................................. 1883
21.7.2 Controlling the SCI TX and RX Features .................................................................. 1883
21.7.3 Receipt Sequence............................................................................................. 1883
21.8 Idle-Line Multiprocessor Mode......................................................................................... 1883
21.8.1 Idle-Line Mode Steps......................................................................................... 1884
21.8.2 Block Start Signal ............................................................................................. 1885
21.8.3 Wake-UP Temporary (WUT) Flag .......................................................................... 1885
21.8.4 Receiver Operation ........................................................................................... 1885
21.9 Address-Bit Multiprocessor Mode..................................................................................... 1885
21.9.1 Sending an Address .......................................................................................... 1885

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21.10 SCI Communication Format........................................................................................... 1886
21.10.1 Receiver Signals in Communication Modes.............................................................. 1887
21.10.2 Transmitter Signals in Communication Modes........................................................... 1887
21.11 SCI Port Interrupts...................................................................................................... 1888
21.12 SCI Baud Rate Calculations........................................................................................... 1889
21.13 SCI Enhanced Features................................................................................................ 1889
21.13.1 SCI FIFO Description ....................................................................................... 1889
21.13.2 SCI Auto-Baud ............................................................................................... 1891
21.13.3 Autobaud-Detect Sequence................................................................................ 1891
21.14 Registers................................................................................................................. 1892
21.14.1 Serial Communications Interface Base Addresses...................................................... 1892
22 Inter-Integrated Circuit Module (I2C).................................................................................. 1912
22.1 Introduction to the I2C Module ........................................................................................ 1913
22.1.1 Features........................................................................................................ 1913
22.1.2 Features Not Supported...................................................................................... 1913
22.1.3 Functional Overview .......................................................................................... 1914
22.1.4 Clock Generation.............................................................................................. 1915
22.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 1916
22.2 Configuring Device Pins................................................................................................ 1917
22.3 I2C Module Operational Details ....................................................................................... 1917
22.3.1 Input and Output Voltage Levels............................................................................ 1917
22.3.2 Data Validity ................................................................................................... 1917
22.3.3 Operating Modes.............................................................................................. 1917
22.3.4 I2C Module START and STOP Conditions ................................................................ 1918
22.3.5 Serial Data Formats........................................................................................... 1919
22.3.6 NACK Bit Generation......................................................................................... 1921
22.3.7 Clock Synchronization........................................................................................ 1922
22.3.8 Arbitration ...................................................................................................... 1922
22.3.9 Digital Loopback Mode ....................................................................................... 1923
22.4 Interrupt Requests Generated by the I2C Module.................................................................. 1924
22.4.1 Basic I2C Interrupt Requests................................................................................ 1924
22.4.2 I2C FIFO Interrupts ........................................................................................... 1925
22.5 Resetting or Disabling the I2C Module............................................................................... 1926
22.6 Registers ................................................................................................................. 1927
22.6.1 Inter-Integrated Circuit Module Base Addresses.......................................................... 1927
23 Power Management Bus Module (PMBus).......................................................................... 1950
23.1 Introduction............................................................................................................... 1951
23.1.1 Features........................................................................................................ 1951
23.1.2 Functional Description........................................................................................ 1952
23.2 Configuring Device Pins................................................................................................ 1952
23.3 Slave Mode Operation.................................................................................................. 1952
23.3.1 Configuration................................................................................................... 1952
23.3.2 Message Handling ............................................................................................ 1953
23.4 Master Mode Operation ................................................................................................ 1961
23.4.1 Configuration................................................................................................... 1961
23.4.2 Message Handling ............................................................................................ 1962
23.5 Registers ................................................................................................................. 1970
23.5.1 Power Management Bus Base Addresses................................................................. 1970
24 Controller Area Network (CAN)......................................................................................... 1990
24.1 Overview.................................................................................................................. 1991
24.1.1 Features ....................................................................................................... 1991
24.1.2 Functional Description ....................................................................................... 1991
24.1.3 Block Diagram ................................................................................................ 1992

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24.2 Configuring Device Pins................................................................................................ 1993
24.3 Address/Data Bus Bridge .............................................................................................. 1993
24.4 Operating Modes........................................................................................................ 1994
24.4.1 Initialization .................................................................................................... 1994
24.4.2 CAN Message Transfer (Normal Operation) .............................................................. 1995
24.4.3 Test Modes .................................................................................................... 1996
24.5 Multiple Clock Source .................................................................................................. 1998
24.6 Interrupt Functionality .................................................................................................. 1998
24.6.1 Message Object Interrupts .................................................................................. 1999
24.6.2 Status Change Interrupts .................................................................................... 1999
24.6.3 Error Interrupts ................................................................................................ 1999
24.6.4 PIE Nomenclature for DCAN Interrupts .................................................................... 1999
24.7 DMA Functionality ...................................................................................................... 1999
24.8 Parity Check Mechanism .............................................................................................. 2000
24.8.1 Behavior on Parity Error ..................................................................................... 2000
24.9 Debug Mode ............................................................................................................ 2000
24.10 Module Initialization .................................................................................................... 2000
24.11 Configuration of Message Objects ................................................................................... 2001
24.11.1 Configuration of a Transmit Object for Data Frames ................................................... 2001
24.11.2 Configuration of a Transmit Object for Remote Frames ............................................... 2001
24.11.3 Configuration of a Single Receive Object for Data Frames ........................................... 2001
24.11.4 Configuration of a Single Receive Object for Remote Frames ....................................... 2002
24.11.5 Configuration of a FIFO Buffer ............................................................................ 2002
24.12 Message Handling ..................................................................................................... 2003
24.12.1 Message Handler Overview ............................................................................... 2003
24.12.2 Receive/Transmit Priority .................................................................................. 2003
24.12.3 Transmission of Messages in Event Driven CAN Communication ................................... 2003
24.12.4 Updating a Transmit Object ............................................................................... 2004
24.12.5 Changing a Transmit Object ............................................................................... 2004
24.12.6 Acceptance Filtering of Received Messages ............................................................ 2004
24.12.7 Reception of Data Frames ................................................................................. 2005
24.12.8 Reception of Remote Frames ............................................................................. 2005
24.12.9 Reading Received Messages ............................................................................. 2005
24.12.10 Requesting New Data for a Receive Object ........................................................... 2006
24.12.11 Storing Received Messages in FIFO Buffers .......................................................... 2006
24.12.12 Reading from a FIFO Buffer ............................................................................. 2006
24.13 CAN Bit Timing ......................................................................................................... 2007
24.13.1 Bit Time and Bit Rate ....................................................................................... 2008
24.13.2 Configuration of the CAN Bit Timing ..................................................................... 2012
24.14 Message Interface Register Sets .................................................................................... 2015
24.14.1 Message Interface Register Sets 1 and 2 ............................................................... 2016
24.14.2 IF3 Register Set ............................................................................................. 2017
24.15 Message RAM .......................................................................................................... 2018
24.15.1 Structure of Message Objects ............................................................................. 2018
24.15.2 Addressing Message Objects in RAM ................................................................... 2020
24.15.3 Message RAM Representation in Debug Mode ........................................................ 2021
24.16 Registers................................................................................................................. 2022
24.16.1 Controller Area Network Base Addresses................................................................ 2022
25 Local Interconnect Network (LIN) Module........................................................................... 2075
25.1 Introduction and Features.............................................................................................. 2076
25.1.1 LIN Features................................................................................................... 2076
25.1.2 Block Diagram................................................................................................. 2077
25.2 LIN Communication Formats .......................................................................................... 2079

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25.2.1 LIN Standards ................................................................................................. 2079
25.2.2 Message Frame ............................................................................................... 2080
25.2.3 Synchronizer................................................................................................... 2082
25.2.4 Baud Rate...................................................................................................... 2082
25.2.5 Header Generation............................................................................................ 2083
25.2.6 Extended Frames Handling.................................................................................. 2088
25.2.7 Timeout Control ............................................................................................... 2089
25.2.8 TXRX Error Detector (TED).................................................................................. 2090
25.2.9 Message Filtering and Validation ........................................................................... 2093
25.2.10 Receive Buffers.............................................................................................. 2095
25.2.11 Transmit Buffers............................................................................................. 2096
25.3 LIN Interrupts ............................................................................................................ 2097
25.3.1 Servicing Interrupts ........................................................................................... 2099
25.3.2 LIN DMA Interface ............................................................................................ 2099
25.4 LIN Configurations ...................................................................................................... 2101
25.4.1 Receiving Data ................................................................................................ 2101
25.4.2 Transmitting Data ............................................................................................. 2102
25.4.3 LIN Low-Power Mode......................................................................................... 2103
25.5 Registers ................................................................................................................. 2105
25.5.1 Local Interconnect Network Base Addresses ............................................................. 2105
26 Fast Serial Interface (FSI)................................................................................................. 2165
26.1 Introduction to the FSI Module ........................................................................................ 2166
26.1.1 Features ....................................................................................................... 2166
26.2 System-level Integration................................................................................................ 2166
26.2.1 CPU Interface.................................................................................................. 2166
26.2.2 Signal Description............................................................................................ 2168
26.2.3 Interrupts ....................................................................................................... 2169
26.2.4 CLA Task Triggering.......................................................................................... 2171
26.2.5 DMA Interface ................................................................................................. 2171
26.2.6 External Frame Trigger Mux................................................................................. 2171
26.3 FSI Operation............................................................................................................ 2172
26.3.1 Introduction to Operation..................................................................................... 2172
26.3.2 FSI Transmitter Module ...................................................................................... 2172
26.3.3 FSI Receiver Module ......................................................................................... 2178
26.3.4 Frame Format.................................................................................................. 2185
26.3.5 The Flush Sequence.......................................................................................... 2188
26.3.6 Internal Loopback ............................................................................................. 2189
26.3.7 CRC Generation............................................................................................... 2189
26.3.8 ECC Module ................................................................................................... 2190
26.4 Programmer's Model.................................................................................................... 2190
26.4.1 Establishing the Communication Link ..................................................................... 2190
26.4.2 Register Protection............................................................................................ 2192
26.4.3 Emulation Mode ............................................................................................... 2192
26.5 Registers ................................................................................................................. 2193
26.5.1 Fast Serial Interface Base Addresses...................................................................... 2193

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List of Figures
2-1. Device Interrupt Architecture ............................................................................................. 77
2-2. Interrupt Propagation Path................................................................................................ 78
2-3. Clocking System............................................................................................................ 91
2-4. System PLL ................................................................................................................. 91
2-5. Using GPIO18 when INTOSC2 is the SYSCLK source............................................................... 92
2-6. Single-ended 3.3V External Clock ....................................................................................... 93
2-7. External Crystal............................................................................................................. 93
2-8. External Resonator......................................................................................................... 94
2-9. CPU Timers................................................................................................................ 101
2-10. CPU Timer Interrupt Signals and Output Signal...................................................................... 101
2-11. Watchdog Timer Module ................................................................................................ 102
2-12. Memory Architecture ..................................................................................................... 108
2-13. Arbitration Scheme on Global Shared Memories..................................................................... 110
2-14. Arbitration Scheme on Local Shared Memories...................................................................... 110
2-15. FMC Interface with Core, Bank and Pump............................................................................ 116
2-16. Flash Prefetch Mode ..................................................................................................... 119
2-17. ECC Logic Inputs and Outputs.......................................................................................... 122
2-18. Storage of Zone-Select Bits in OTP ................................................................................... 131
2-19. Location of Zone-Select Block Based on Link-Pointer for Bank0 .................................................. 132
2-20. Location of Zone-Select Block Based on Link-Pointer for Bank1 .................................................. 133
2-21. CSM Password Match Flow (PMF)..................................................................................... 138
2-22. ECSL Password Match Flow (PMF).................................................................................... 140
2-23. NMAVFLG Register ...................................................................................................... 144
2-24. NMAVSET Register ...................................................................................................... 145
2-25. NMAVCLR Register ...................................................................................................... 146
2-26. NMAVINTEN Register.................................................................................................... 147
2-27. NMCPURDAVADDR Register .......................................................................................... 148
2-28. NMCPUWRAVADDR Register.......................................................................................... 149
2-29. NMCPUFAVADDR Register............................................................................................. 150
2-30. NMDMAWRAVADDR Register ......................................................................................... 151
2-31. NMCLA1RDAVADDR Register ......................................................................................... 152
2-32. NMCLA1WRAVADDR Register......................................................................................... 153
2-33. NMCLA1FAVADDR Register............................................................................................ 154
2-34. MAVFLG Register ........................................................................................................ 155
2-35. MAVSET Register ........................................................................................................ 156
2-36. MAVCLR Register ........................................................................................................ 157
2-37. MAVINTEN Register ..................................................................................................... 158
2-38. MCPUFAVADDR Register............................................................................................... 159
2-39. MCPUWRAVADDR Register............................................................................................ 160
2-40. MDMAWRAVADDR Register ........................................................................................... 161
2-41. CLKCFGLOCK1 Register................................................................................................ 163
2-42. CLKSRCCTL1 Register.................................................................................................. 165
2-43. CLKSRCCTL2 Register.................................................................................................. 167
2-44. CLKSRCCTL3 Register.................................................................................................. 168
2-45. SYSPLLCTL1 Register................................................................................................... 169
2-46. SYSPLLMULT Register.................................................................................................. 170
2-47. SYSPLLSTS Register.................................................................................................... 171

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2-48. SYSCLKDIVSEL Register ............................................................................................... 172
2-49. XCLKOUTDIVSEL Register............................................................................................. 173
2-50. LOSPCP Register ........................................................................................................ 174
2-51. MCDCR Register ......................................................................................................... 175
2-52. X1CNT Register........................................................................................................... 176
2-53. XTALCR Register......................................................................................................... 177
2-54. CPUSYSLOCK1 Register ............................................................................................... 179
2-55. PIEVERRADDR Register................................................................................................ 182
2-56. PCLKCR0 Register....................................................................................................... 183
2-57. PCLKCR2 Register....................................................................................................... 184
2-58. PCLKCR3 Register....................................................................................................... 186
2-59. PCLKCR4 Register....................................................................................................... 187
2-60. PCLKCR6 Register....................................................................................................... 188
2-61. PCLKCR7 Register....................................................................................................... 189
2-62. PCLKCR8 Register....................................................................................................... 190
2-63. PCLKCR9 Register....................................................................................................... 191
2-64. PCLKCR10 Register ..................................................................................................... 192
2-65. PCLKCR13 Register ..................................................................................................... 193
2-66. PCLKCR14 Register ..................................................................................................... 194
2-67. PCLKCR15 Register ..................................................................................................... 195
2-68. PCLKCR16 Register ..................................................................................................... 196
2-69. PCLKCR17 Register ..................................................................................................... 197
2-70. PCLKCR18 Register ..................................................................................................... 198
2-71. PCLKCR19 Register ..................................................................................................... 199
2-72. PCLKCR20 Register ..................................................................................................... 200
2-73. PCLKCR21 Register ..................................................................................................... 201
2-74. LPMCR Register.......................................................................................................... 202
2-75. GPIOLPMSEL0 Register................................................................................................. 203
2-76. GPIOLPMSEL1 Register................................................................................................. 205
2-77. TMR2CLKCTL Register.................................................................................................. 207
2-78. RESCCLR Register....................................................................................................... 208
2-79. RESC Register............................................................................................................ 209
2-80. TIM Register............................................................................................................... 212
2-81. PRD Register.............................................................................................................. 213
2-82. TCR Register.............................................................................................................. 214
2-83. TPR Register.............................................................................................................. 216
2-84. TPRH Register............................................................................................................ 217
2-85. DCCGCTRL Register .................................................................................................... 219
2-86. DCCREV Register........................................................................................................ 220
2-87. DCCCNTSEED0 Register ............................................................................................... 221
2-88. DCCVALIDSEED0 Register............................................................................................. 222
2-89. DCCCNTSEED1 Register ............................................................................................... 223
2-90. DCCSTATUS Register................................................................................................... 224
2-91. DCCCNT0 Register....................................................................................................... 225
2-92. DCCVALID0 Register .................................................................................................... 226
2-93. DCCCNT1 Register....................................................................................................... 227
2-94. DCCCLKSRC1 Register ................................................................................................. 228
2-95. DCCCLKSRC0 Register ................................................................................................. 229
2-96. B0_Z1_LINKPOINTER Register........................................................................................ 231

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List of Figures
2-97. Z1_OTPSECLOCK Register ............................................................................................ 232
2-98. Z1_BOOTDEF_HIGH Register ......................................................................................... 233
2-99. B0_Z1_LINKPOINTERERR Register .................................................................................. 234
2-100. Z1_BOOTPIN_CONFIG Register....................................................................................... 235
2-101. Z1_GPREG2 Register.................................................................................................... 236
2-102. Z1_BOOTDEF_LOW Register .......................................................................................... 237
2-103. Z1_CSMKEY0 Register.................................................................................................. 238
2-104. Z1_CSMKEY1 Register.................................................................................................. 239
2-105. Z1_CSMKEY2 Register.................................................................................................. 240
2-106. Z1_CSMKEY3 Register.................................................................................................. 241
2-107. Z1_CR Register........................................................................................................... 242
2-108. B0_Z1_GRABSECTR Register ......................................................................................... 243
2-109. Z1_GRABRAMR Register ............................................................................................... 246
2-110. B0_Z1_EXEONLYSECTR Register .................................................................................... 248
2-111. Z1_EXEONLYRAMR Register .......................................................................................... 251
2-112. B0_Z2_LINKPOINTER Register........................................................................................ 254
2-113. Z2_OTPSECLOCK Register ............................................................................................ 255
2-114. B0_Z2_LINKPOINTERERR Register .................................................................................. 256
2-115. Z2_CSMKEY0 Register.................................................................................................. 257
2-116. Z2_CSMKEY1 Register.................................................................................................. 258
2-117. Z2_CSMKEY2 Register.................................................................................................. 259
2-118. Z2_CSMKEY3 Register.................................................................................................. 260
2-119. Z2_CR Register........................................................................................................... 261
2-120. B0_Z2_GRABSECTR Register ......................................................................................... 262
2-121. Z2_GRABRAMR Register ............................................................................................... 265
2-122. B0_Z2_EXEONLYSECTR Register .................................................................................... 267
2-123. Z2_EXEONLYRAMR Register .......................................................................................... 270
2-124. B1_Z1_LINKPOINTER Register........................................................................................ 273
2-125. B1_Z1_LINKPOINTERERR Register .................................................................................. 274
2-126. B1_Z1_GRABSECTR Register ......................................................................................... 275
2-127. B1_Z1_EXEONLYSECTR Register .................................................................................... 278
2-128. B1_Z2_LINKPOINTER Register........................................................................................ 282
2-129. B1_Z2_LINKPOINTERERR Register .................................................................................. 283
2-130. B1_Z2_GRABSECTR Register ......................................................................................... 284
2-131. B1_Z2_EXEONLYSECTR Register .................................................................................... 287
2-132. FLSEM Register .......................................................................................................... 291
2-133. B0_SECTSTAT Register................................................................................................. 292
2-134. RAMSTAT Register....................................................................................................... 295
2-135. B1_SECTSTAT Register................................................................................................. 297
2-136. SECERRSTAT Register ................................................................................................. 300
2-137. SECERRCLR Register................................................................................................... 301
2-138. SECERRFRC Register................................................................................................... 302
2-139. PARTIDL Register........................................................................................................ 305
2-140. PARTIDH Register........................................................................................................ 306
2-141. REVID Register ........................................................................................................... 307
2-142. FUSEERR Register....................................................................................................... 308
2-143. SOFTPRES0 Register ................................................................................................... 309
2-144. SOFTPRES2 Register ................................................................................................... 310
2-145. SOFTPRES3 Register ................................................................................................... 311

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2-146. SOFTPRES4 Register ................................................................................................... 312
2-147. SOFTPRES6 Register ................................................................................................... 313
2-148. SOFTPRES7 Register ................................................................................................... 314
2-149. SOFTPRES8 Register ................................................................................................... 315
2-150. SOFTPRES9 Register ................................................................................................... 316
2-151. SOFTPRES10 Register.................................................................................................. 317
2-152. SOFTPRES13 Register.................................................................................................. 318
2-153. SOFTPRES14 Register.................................................................................................. 319
2-154. SOFTPRES15 Register.................................................................................................. 320
2-155. SOFTPRES16 Register.................................................................................................. 321
2-156. SOFTPRES17 Register.................................................................................................. 322
2-157. SOFTPRES18 Register.................................................................................................. 323
2-158. SOFTPRES19 Register.................................................................................................. 324
2-159. SOFTPRES20 Register.................................................................................................. 325
2-160. SOFTPRES21 Register.................................................................................................. 326
2-161. TAP_STATUS Register.................................................................................................. 327
2-162. CLA1TASKSRCSELLOCK Register ................................................................................... 329
2-163. DMACHSRCSELLOCK Register ....................................................................................... 330
2-164. CLA1TASKSRCSEL1 Register ......................................................................................... 331
2-165. CLA1TASKSRCSEL2 Register ......................................................................................... 332
2-166. DMACHSRCSEL1 Register ............................................................................................. 333
2-167. DMACHSRCSEL2 Register ............................................................................................. 334
2-168. FRDCNTL Register....................................................................................................... 336
2-169. FBAC Register ............................................................................................................ 337
2-170. FBFALLBACK Register .................................................................................................. 338
2-171. FBPRDY Register ........................................................................................................ 339
2-172. FPAC1 Register........................................................................................................... 340
2-173. FPAC2 Register........................................................................................................... 341
2-174. FMSTAT Register......................................................................................................... 342
2-175. FRD_INTF_CTRL Register.............................................................................................. 344
2-176. ECC_ENABLE Register.................................................................................................. 346
2-177. SINGLE_ERR_ADDR_LOW Register.................................................................................. 347
2-178. SINGLE_ERR_ADDR_HIGH Register................................................................................. 348
2-179. UNC_ERR_ADDR_LOW Register...................................................................................... 349
2-180. UNC_ERR_ADDR_HIGH Register..................................................................................... 350
2-181. ERR_STATUS Register.................................................................................................. 351
2-182. ERR_POS Register....................................................................................................... 353
2-183. ERR_STATUS_CLR Register........................................................................................... 354
2-184. ERR_CNT Register....................................................................................................... 355
2-185. ERR_THRESHOLD Register............................................................................................ 356
2-186. ERR_INTFLG Register................................................................................................... 357
2-187. ERR_INTCLR Register .................................................................................................. 358
2-188. FDATAH_TEST Register ................................................................................................ 359
2-189. FDATAL_TEST Register................................................................................................. 360
2-190. FADDR_TEST Register.................................................................................................. 361
2-191. FECC_TEST Register.................................................................................................... 362
2-192. FECC_CTRL Register.................................................................................................... 363
2-193. FOUTH_TEST Register.................................................................................................. 364
2-194. FOUTL_TEST Register .................................................................................................. 365

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2-195. FECC_STATUS Register................................................................................................ 366
2-196. DxLOCK Register......................................................................................................... 369
2-197. DxCOMMIT Register ..................................................................................................... 370
2-198. DxACCPROT0 Register ................................................................................................. 371
2-199. DxTEST Register ......................................................................................................... 372
2-200. DxINIT Register........................................................................................................... 373
2-201. DxINITDONE Register ................................................................................................... 374
2-202. LSxLOCK Register ....................................................................................................... 375
2-203. LSxCOMMIT Register.................................................................................................... 377
2-204. LSxMSEL Register ....................................................................................................... 379
2-205. LSxCLAPGM Register ................................................................................................... 381
2-206. LSxACCPROT0 Register ................................................................................................ 382
2-207. LSxACCPROT1 Register ................................................................................................ 384
2-208. LSxTEST Register........................................................................................................ 386
2-209. LSxINIT Register.......................................................................................................... 388
2-210. LSxINITDONE Register.................................................................................................. 389
2-211. GSxLOCK Register....................................................................................................... 390
2-212. GSxCOMMIT Register ................................................................................................... 391
2-213. GSxACCPROT0 Register ............................................................................................... 393
2-214. GSxACCPROT1 Register ............................................................................................... 395
2-215. GSxACCPROT2 Register ............................................................................................... 396
2-216. GSxACCPROT3 Register ............................................................................................... 397
2-217. GSxTEST Register ....................................................................................................... 398
2-218. GSxINIT Register ......................................................................................................... 400
2-219. GSxINITDONE Register ................................................................................................. 401
2-220. MSGxLOCK Register..................................................................................................... 402
2-221. MSGxCOMMIT Register................................................................................................. 403
2-222. MSGxTEST Register..................................................................................................... 404
2-223. MSGxINIT Register....................................................................................................... 405
2-224. MSGxINITDONE Register............................................................................................... 406
2-225. UCERRFLG Register..................................................................................................... 408
2-226. UCERRSET Register..................................................................................................... 409
2-227. UCERRCLR Register .................................................................................................... 410
2-228. UCCPUREADDR Register .............................................................................................. 411
2-229. UCDMAREADDR Register .............................................................................................. 412
2-230. UCCLA1READDR Register ............................................................................................. 413
2-231. CERRFLG Register....................................................................................................... 414
2-232. CERRSET Register....................................................................................................... 415
2-233. CERRCLR Register ...................................................................................................... 416
2-234. CCPUREADDR Register ................................................................................................ 417
2-235. CERRCNT Register ...................................................................................................... 418
2-236. CERRTHRES Register................................................................................................... 419
2-237. CEINTFLG Register ...................................................................................................... 420
2-238. CEINTCLR Register...................................................................................................... 421
2-239. CEINTSET Register ...................................................................................................... 422
2-240. CEINTEN Register........................................................................................................ 423
2-241. NMICFG Register......................................................................................................... 425
2-242. NMIFLG Register ......................................................................................................... 426
2-243. NMIFLGCLR Register.................................................................................................... 428

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2-244. NMIFLGFRC Register.................................................................................................... 429
2-245. NMIWDCNT Register .................................................................................................... 430
2-246. NMIWDPRD Register .................................................................................................... 431
2-247. NMISHDFLG Register.................................................................................................... 432
2-248. ADCA_AC Register....................................................................................................... 435
2-249. ADCB_AC Register....................................................................................................... 436
2-250. ADCC_AC Register....................................................................................................... 437
2-251. CMPSS1_AC Register ................................................................................................... 438
2-252. CMPSS2_AC Register ................................................................................................... 439
2-253. CMPSS3_AC Register ................................................................................................... 440
2-254. CMPSS4_AC Register ................................................................................................... 441
2-255. CMPSS5_AC Register ................................................................................................... 442
2-256. CMPSS6_AC Register ................................................................................................... 443
2-257. CMPSS7_AC Register ................................................................................................... 444
2-258. DACA_AC Register....................................................................................................... 445
2-259. DACB_AC Register....................................................................................................... 446
2-260. PGA1_AC Register....................................................................................................... 447
2-261. PGA2_AC Register....................................................................................................... 448
2-262. PGA3_AC Register....................................................................................................... 449
2-263. PGA4_AC Register....................................................................................................... 450
2-264. PGA5_AC Register....................................................................................................... 451
2-265. PGA6_AC Register....................................................................................................... 452
2-266. PGA7_AC Register....................................................................................................... 453
2-267. EPWM1_AC Register .................................................................................................... 454
2-268. EPWM2_AC Register .................................................................................................... 455
2-269. EPWM3_AC Register .................................................................................................... 456
2-270. EPWM4_AC Register .................................................................................................... 457
2-271. EPWM5_AC Register .................................................................................................... 458
2-272. EPWM6_AC Register .................................................................................................... 459
2-273. EPWM7_AC Register .................................................................................................... 460
2-274. EPWM8_AC Register .................................................................................................... 461
2-275. EQEP1_AC Register ..................................................................................................... 462
2-276. EQEP2_AC Register ..................................................................................................... 463
2-277. ECAP1_AC Register ..................................................................................................... 464
2-278. ECAP2_AC Register ..................................................................................................... 465
2-279. ECAP3_AC Register ..................................................................................................... 466
2-280. ECAP4_AC Register ..................................................................................................... 467
2-281. ECAP5_AC Register ..................................................................................................... 468
2-282. ECAP6_AC Register ..................................................................................................... 469
2-283. ECAP7_AC Register ..................................................................................................... 470
2-284. SDFM1_AC Register..................................................................................................... 471
2-285. CLB1_AC Register ....................................................................................................... 472
2-286. CLB2_AC Register ....................................................................................................... 473
2-287. CLB3_AC Register ....................................................................................................... 474
2-288. CLB4_AC Register ....................................................................................................... 475
2-289. CLA1PROMCRC_AC Register ......................................................................................... 476
2-290. SPIA_AC Register........................................................................................................ 477
2-291. SPIB_AC Register........................................................................................................ 478
2-292. PMBUS_A_AC Register ................................................................................................. 479

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2-293. LIN_A_AC Register....................................................................................................... 480
2-294. DCANA_AC Register..................................................................................................... 481
2-295. DCANB_AC Register..................................................................................................... 482
2-296. FSIATX_AC Register..................................................................................................... 483
2-297. FSIARX_AC Register .................................................................................................... 484
2-298. HRPWM_A_AC Register ................................................................................................ 485
2-299. PERIPH_AC_LOCK Register ........................................................................................... 486
2-300. PIECTRL Register........................................................................................................ 488
2-301. PIEACK Register.......................................................................................................... 489
2-302. PIEIER1 Register ......................................................................................................... 490
2-303. PIEIFR1 Register ......................................................................................................... 491
2-304. PIEIER2 Register ......................................................................................................... 492
2-305. PIEIFR2 Register ......................................................................................................... 493
2-306. PIEIER3 Register ......................................................................................................... 494
2-307. PIEIFR3 Register ......................................................................................................... 495
2-308. PIEIER4 Register ......................................................................................................... 496
2-309. PIEIFR4 Register ......................................................................................................... 497
2-310. PIEIER5 Register ......................................................................................................... 498
2-311. PIEIFR5 Register ......................................................................................................... 499
2-312. PIEIER6 Register ......................................................................................................... 500
2-313. PIEIFR6 Register ......................................................................................................... 501
2-314. PIEIER7 Register ......................................................................................................... 502
2-315. PIEIFR7 Register ......................................................................................................... 503
2-316. PIEIER8 Register ......................................................................................................... 504
2-317. PIEIFR8 Register ......................................................................................................... 505
2-318. PIEIER9 Register ......................................................................................................... 506
2-319. PIEIFR9 Register ......................................................................................................... 507
2-320. PIEIER10 Register........................................................................................................ 508
2-321. PIEIFR10 Register........................................................................................................ 509
2-322. PIEIER11 Register........................................................................................................ 510
2-323. PIEIFR11 Register........................................................................................................ 511
2-324. PIEIER12 Register........................................................................................................ 512
2-325. PIEIFR12 Register........................................................................................................ 513
2-326. ROMPREFETCH Register............................................................................................... 515
2-327. ROMWAITSTATE Register.............................................................................................. 517
2-328. SCSR Register............................................................................................................ 519
2-329. WDCNTR Register ....................................................................................................... 520
2-330. WDKEY Register.......................................................................................................... 521
2-331. WDCR Register........................................................................................................... 522
2-332. WDWCR Register ........................................................................................................ 524
2-333. XINT1CR Register........................................................................................................ 526
2-334. XINT2CR Register........................................................................................................ 527
2-335. XINT3CR Register........................................................................................................ 528
2-336. XINT4CR Register........................................................................................................ 529
2-337. XINT5CR Register........................................................................................................ 530
2-338. XINT1CTR Register ...................................................................................................... 531
2-339. XINT2CTR Register ...................................................................................................... 532
2-340. XINT3CTR Register ...................................................................................................... 533
3-1. Device Boot Flow ......................................................................................................... 540

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List of Figures
3-2. Emulation Boot Flow ..................................................................................................... 541
3-3. Standalone Boot Flow.................................................................................................... 542
3-4. Overview of SCI Bootloader Operation ................................................................................ 548
3-5. Overview of SCI Boot Function ......................................................................................... 549
3-6. SPI Loader................................................................................................................. 549
3-7. Data Transfer From EEPROM Flow.................................................................................... 551
3-8. EEPROM Device at Address 0x50 ..................................................................................... 551
3-9. Overview of I2C Boot Function ......................................................................................... 552
3-10. Random Read............................................................................................................. 553
3-11. Sequential Read .......................................................................................................... 554
3-12. Overview of Parallel GPIO Bootloader Operation.................................................................... 554
3-13. Parallel GPIO Bootloader Handshake Protocol....................................................................... 555
3-14. Parallel GPIO Mode Overview .......................................................................................... 555
3-15. Parallel GPIO Mode - Host Transfer Flow............................................................................. 556
3-16. 8-Bit Parallel GetWord Function ........................................................................................ 557
3-17. Overview of CAN-A Bootloader Operation ............................................................................ 558
4-1. CLA Block Diagram....................................................................................................... 569
4-2. _MVECTBGRNDACTIVE Register..................................................................................... 707
4-3. _MPSACTL Register ..................................................................................................... 708
4-4. _MPSA1 Register......................................................................................................... 709
4-5. _MPSA2 Register......................................................................................................... 710
4-6. SOFTINTEN Register .................................................................................................... 711
4-7. SOFTINTFRC Register .................................................................................................. 712
4-8. MVECT1 Register ........................................................................................................ 715
4-9. MVECT2 Register ........................................................................................................ 716
4-10. MVECT3 Register ........................................................................................................ 717
4-11. MVECT4 Register ........................................................................................................ 718
4-12. MVECT5 Register ........................................................................................................ 719
4-13. MVECT6 Register ........................................................................................................ 720
4-14. MVECT7 Register ........................................................................................................ 721
4-15. MVECT8 Register ........................................................................................................ 722
4-16. MCTL Register............................................................................................................ 723
4-17. _MVECTBGRNDACTIVE Register..................................................................................... 724
4-18. SOFTINTEN Register .................................................................................................... 725
4-19. _MSTSBGRND Register................................................................................................. 726
4-20. _MCTLBGRND Register................................................................................................. 727
4-21. _MVECTBGRND Register............................................................................................... 728
4-22. MIFR Register............................................................................................................. 729
4-23. MIOVF Register........................................................................................................... 733
4-24. MIFRC Register........................................................................................................... 736
4-25. MICLR Register........................................................................................................... 738
4-26. MICLROVF Register ..................................................................................................... 740
4-27. MIER Register............................................................................................................. 742
4-28. MIRUN Register........................................................................................................... 745
4-29. _MPC Register............................................................................................................ 747
4-30. _MAR0 Register .......................................................................................................... 748
4-31. _MAR1 Register .......................................................................................................... 749
4-32. _MSTF Register........................................................................................................... 750
4-33. _MR0 Register ............................................................................................................ 753