Texas Instruments TMS320F2807 Series User manual

1
SPRZ423H–October 2014–Revised February 2020
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TMS320F2807x MCUs Silicon Revisions C, B
Silicon Errata
SPRZ423H–October 2014–Revised February 2020
TMS320F2807x MCUs
Silicon Revisions C, B
1 Introduction
This document describes the silicon updates to the functional specifications for the TMS320F2807x
microcontrollers (MCUs).
The updates are applicable to the following:
• 176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack, PTP Suffix
• 100-Pin PowerPAD Thermally Enhanced Thin Quad Flatpack, PZP Suffix
2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28075). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX
for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PTP) and temperature range (for example, T).

PREFIX
TMS
TMX = experimental device
TMP = prototype device
TMS = qualified device
320
DEVICE FAMILY
320 = TMS320 MCU Family
F
TECHNOLOGY
F = Flash
28075
DEVICE
28076
28075
PTP
PACKAGE TYPE
176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP)
100-Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP)
TEMPERATURE RANGE
T
−40°C to 105°C (T )
−40°C to 125°C (T )
−40°C to 125°C (T )
(Q refers to AEC Q100 qualification for automotive applications.)
J
J
A
T
S
Q
=
=
=
YMLLLLS
YM
LLLL
S
$$
#
G4
Lot Trace Code
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code as applicable
Silicon Revision Code
Green (Low Halogen and RoHS-compliant)
=
=
=
=
=
=
=
$$#-YMLLLLS
G4
F28075PTPT
TMS320
Package
Pin 1
Device Markings www.ti.com
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3 Device Markings
Figure 1 provides an example of the 2807x device markings and defines each of the markings. The device
revision can be determined by the symbols marked on the top of the package as shown in Figure 1. Some
prototype devices may have markings different from those illustrated. Figure 2 shows an example of the
device nomenclature.
Figure 1. Example of Device Markings
(1) Silicon Revision ID
Table 1. Determining Silicon Revision From Lot Trace Code
SILICON REVISION CODE SILICON REVISION REVID(1)
Address: 0x5D00C COMMENTS
B B 0x0002 This silicon revision is available as TMX.
C C 0x0003 This silicon revision is available as TMS.
Figure 2. Example of Device Nomenclature

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4 Usage Notes and Known Design Exceptions to Functional Specifications
4.1 Usage Notes
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
Table 2 shows which silicon revision(s) are affected by each usage note.
Table 2. List of Usage Notes
TITLE SILICON REVISION(S)
AFFECTED
B C
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Yes Yes
Caution While Using Nested Interrupts Yes Yes
SYS/BIOS: Version Implemented in Device ROM is not Maintained Yes Yes
SDFM: Use Caution While Using SDFM Under Noisy Conditions Yes Yes
4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt
Mask Clear
Revision(s) Affected: B, C
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state
that can trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other
interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it
happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be
triggered after the nested interrupt reenables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is
shown below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
EINT; //Enable nesting in the CPU
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
asm(" NOP"); //Wait for PIEACK to exit the pipeline
EINT; //Enable nesting in the CPU
4.1.2 Caution While Using Nested Interrupts
Revision(s) Affected: B, C
If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order
to use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so
may cause undefined behavior of CPU execution.

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4.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
Revision(s) Affected: B, C
The SYS/BIOS version 6.37 in ROM cannot be updated to address bug fixes or enhancements. For
applications using this ROM version of SYS/BIOS, the user should review the release notes on the
SYS/BIOS Product Releases page to assess any application impact to known bugs.
To use the latest maintained SYS/BIOS version, download the SYS/BIOS library and include in the
application flash image instead of using the ROM version.
4.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
Revision(s) Affected: B, C
The SDFM clock input (SDx_Cy) directly clocks the SDFM module when there is no GPIO input
synchronization. Any glitches or ringing noise on the SDx_Cy input beyond VIH or VIL can corrupt the
SDFM module, leading to unpredictable results.
Workaround(s):
SDFM GPIO Asynchronous Mode:
Special attention should be taken during board design to ensure a clean and noise-free signal that meets
the SDFM timing requirements. Precautions such as series termination for ringing due to any impedance
mismatch of the clock driver, and spacing of traces from other high-frequency signals are recommended.
SDFM GPIO Qualification (3-sample) Mode:
It is highly recommended that the SDFM GPIO qualification mode be used in noisy conditions. This mode
provides additional protection by filtering both SDx_Cy and SDx_Dy inputs from system noise. Refer to the
"SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window)" table in the
TMS320F2807x Microcontrollers Data Manual when using this option.
When a noise event occurs while using the GPIO Qualification mode, there may still be data disturbance,
but it will be proportional to the duration of the noise event and typically filtered by the oversampling of the
SDFM module. Below is a relative listing of each SDFM mode's sensitivity to data variation in the
presence of severe system noise.
• Mode 0: This mode is the best performing mode. It is the recommended mode under noisy conditions.
• Mode 1 and Mode 3: The error in these modes can be twice as large as the error in Mode 0 since each
noise glitch can introduce error for multiple data bits.
• Mode 2: This option is unavailable when using GPIO qualification. This mode is not recommended for
either GPIO ASYNC or GPIO qualification.

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4.2 Known Design Exceptions to Functional Specifications
Table 3 shows which silicon revision(s) are affected by each advisory.
Table 3. List of Advisories
TITLE SILICON REVISION(S)
AFFECTED
B C
Analog Bandgap References Yes Yes
Analog Trim of Some TMX Devices Yes
ADC: ADC Post-Processing Block Limit Compare Yes Yes
ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes
ADC: DMA Read of Stale Result Yes Yes
ADC: Random Conversion Errors Yes
ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule Yes
ADC: 12-Bit Switch Resistance Yes
ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes
XRS may Toggle During Power Up Yes
USB: USB DMA Event Triggers are not Supported Yes Yes
VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ Yes
Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR Yes Yes
Flash: Minimum Programming Word Size Yes Yes
ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled Yes
eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes
eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes
PLL: May Not Lock On the First Lock Attempt Yes Yes
PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective Yes Yes
SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256 Yes Yes
SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First
Time Yes Yes
SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES
Signal Yes Yes
SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions Yes Yes
SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will
Trigger Spurious Comparator Events Yes Yes
SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger
Spurious Data Acknowledge Events Yes Yes
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes
FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions Yes Yes
Memory: Prefetching Beyond Valid Memory Yes Yes
INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift Yes Yes
Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity Yes Yes
I2C: SDA and SCL Open-Drain Output Buffer Issue Yes Yes
ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes Yes
ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using Shadow Load Mode for
RED/FED Yes Yes
SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes
CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions Yes Yes
CMPSS: Ramp Generator May Not Start Under Certain Conditions Yes Yes
GPIO: Open-Drain Configuration May Drive a Short High Pulse Yes Yes
During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer Yes Yes
Boot ROM: Calling SCI Bootloader from Application Yes Yes

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Table 3. List of Advisories (continued)
TITLE SILICON REVISION(S)
AFFECTED
B C
Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present Yes
Table 4. Table of Contents for Advisories
Title ...................................................................................................................................... Page
Advisory —Analog Bandgap References............................................................................................. 8
Advisory —Analog Trim of Some TMX Devices ..................................................................................... 9
Advisory —ADC: ADC Post-Processing Block Limit Compare................................................................... 10
Advisory —ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set ............................... 10
Advisory —ADC: DMA Read of Stale Result ....................................................................................... 11
Advisory —ADC: Random Conversion Errors...................................................................................... 11
Advisory —ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule ............................ 11
Advisory —ADC: 12-Bit Switch Resistance ........................................................................................ 12
Advisory —ADC: 12-Bit Input Capacitance When Switching Channel Groups ................................................ 12
Advisory —XRS may Toggle During Power Up .................................................................................... 13
Advisory —USB: USB DMA Event Triggers are not Supported.................................................................. 13
Advisory —VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ .................................... 13
Advisory —Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR ............................... 14
Advisory —Flash: Minimum Programming Word Size............................................................................. 14
Advisory —ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled...................................... 15
Advisory —eQEP: Position Counter Incorrectly Reset on Direction Change During Index .................................. 16
Advisory —eQEP: eQEP Inputs in GPIO Asynchronous Mode.................................................................. 16
Advisory —PLL: May Not Lock on the First Lock Attempt........................................................................ 17
Advisory —PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective .......................... 18
Advisory —SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256................ 19
Advisory —SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First Time 19
Advisory —SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES Signal 19
Advisory —SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions ....... 20
Advisory —SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger
Spurious Comparator Events................................................................................................. 20
Advisory —SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious
Data Acknowledge Events.................................................................................................... 21
Advisory —FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation............................. 22
Advisory —FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions ............................... 25
Advisory —Memory: Prefetching Beyond Valid Memory ......................................................................... 28
Advisory —INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift .................................... 28
Advisory —Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity................................... 29
Advisory —I2C: SDA and SCL Open-Drain Output Buffer Issue ................................................................ 30
Advisory — ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window........... 32
Advisory —ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using Shadow Load Mode for
RED/FED........................................................................................................................ 32
Advisory —SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang.......................... 33
Advisory —CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions .................................... 34
Advisory —CMPSS: Ramp Generator May Not Start Under Certain Conditions .............................................. 34
Advisory —GPIO: Open-Drain Configuration May Drive a Short High Pulse .................................................. 35
Advisory —During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer ............ 36
Advisory —Boot ROM: Calling SCI Bootloader from Application ................................................................ 37

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Table 4. Table of Contents for Advisories (continued)
Advisory —Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present ................................... 37

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Advisory Analog Bandgap References
Revision(s) Affected B, C
Details The Analog Subsystem includes internal bandgap reference circuits that are shared by
the embedded analog modules. Table 5 shows the bandgap usage by module.
Table 5. Bandgap Usage by Module
BANDGAP ADC BUFFERED DAC CMPSS
BGA ADCA DACA
DACB CMPSS1 CMPSS2
BGB ADCB DACC CMPSS3
CMPSS4
BGC ADCC CMPSS5
CMPSS6
BGD ADCD CMPSS7
CMPSS8
Each bandgap reference—BGA, BGB, BGC, or BGD—will power up when one or more
of the dependent modules are enabled. An active bandgap reference will power down if
all dependent modules are disabled.
For example, bandgap B (BGB) is powered down unless one or more of the following
register bits are set:
• AdcbRegs.ADCCTL1.bit.ADCPWDNZ
• DaccRegs.DACOUTEN.bit.DACOUTEN
• Cmpss3Regs.COMPCTL.bit.COMPDACE
• Cmpss4Regs.COMPCTL.bit.COMPDACE
The CMPSS and GPDAC power-up time specification in the TMS320F2807x
Microcontrollers Data Manual previously did not account for the bandgap power-up time.
This 10-µs value has been increased to 500 µs to account for the bandgap power-up
time.
Workaround(s) If your application was utilizing a power-up time of 10 µs for the CMPSS and GPDAC,
you do not need to increase it to 500 µs if the respective ADC on that bandgap was
turned on before the CMPSS and GPDAC, and the ADC power-up time of 500 µs was
adhered to.
For simplicity, it is recommended that 500 µs be used as the power-up time for both
CMPSS and GPDAC.

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Advisory Analog Trim of Some TMX Devices
Revision(s) Affected B
Details Some TMX samples may not have analog trims programmed. This could degrade the
performance of the ADC, buffered DAC, and internal oscillators. A value of all zeros in
these trim registers due to lack of trim will have the following impact.
TRIM REGISTER IMPACT OF UNTRIMMED REGISTER
ADC reference AnalogSubsysRegs.ANAREFTRIMA Degraded performance of the ADC for all
specifications.
AnalogSubsysRegs.ANAREFTRIMB
AnalogSubsysRegs.ANAREFTRIMD
ADC linearity AdcaRegs.ADCINLTRIM1-6 Degraded INL and DNL specifications of the ADC
in 16-bit mode. No workaround available.
AdcbRegs.ADCINLTRIM1-6
AdcdRegs.ADCINLTRIM1-6
ADC offset AdcaRegs.ADCOFFTRIM Degraded performance of the ADC offset error
specification.
AdcbRegs.ADCOFFTRIM
AdcdRegs.ADCOFFTRIM
Internal oscillator AnalogSubsysRegs.INTOSC1TRIM Degraded frequency accuracy and temperature
drift of the internal oscillators.
AnalogSubsysRegs.INTOSC2TRIM
Buffered DAC offset DacaRegs.DACTRIM Degraded offset error specification of the buffered
DAC. No workaround available.
DacbRegs.DACTRIM
DaccRegs.DACTRIM
Workaround(s) The following workarounds can be used for improved performance, though it still may not
meet data sheet specifications.
To determine if a device is TMX in software, check the status of the PARTIDL[QUAL]. If
this field is 0, the device is TMX. PARTIDL[QUAL] can be read via the function call
SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL). This check is implemented in
the Device_init() function, which will then call the Device_configureTMXAnalogTrim()
function if needed. The user can place any additional self-calibration or static calibration
code in the Device_configureTMXAnalogTrim() function.
If the ADC reference trim registers contain all zeros, write the static reference trim value
of 0x7BDD to the reference trim register for all ADCs.
Missing ADC offset trim can be generated by following the instructions in the “ADC
Zero Offset Calibration” section of the TMS320F2807x Microcontrollers Technical
Reference Manual.
If the internal oscillator trim contains all zeros, the user can adjust the lowest 10 bits of
the oscillator trim register between 1 (minimum) and 1023 (maximum) while observing
the system clock on the XCLOCKOUT pin.

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Advisory ADC: ADC Post-Processing Block Limit Compare
Revision(s) Affected B, C
Details When using a non-zero offset reference in the ADC post-processing block (PPB), the
resultant ADCPPBxRESULT can be signed. TRIPHI or TRIPLO limit compares do not
function correctly with this result if it is signed.
Workaround(s) When using the TRIPHI or TRIPLO limit compares, leave the offset reference as zero.
The offset reference (and zero compare) can be used as long as the limit compares are
disabled.
If the limit compares, the offset reference, and the zero-crossing compare are to be used
at the same time, then two PPBs can be used. Both PPBs should be configured to use
the same SOC. One PPB can implement the TRIPHI and/or TRIPLO limit compares
while the other can implement offset reference subtraction and zero-crossing detection.
Advisory ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set
Revision(s) Affected B, C
Details If ADCINTSELxNx[INTxCONT] = 0, then interrupts will stop when the ADCINTFLG is set
and no additional ADC interrupts will occur.
When an ADC interrupt occurs simultaneously with a software write of the
ADCINTFLGCLR register, the ADCINTFLG will unexpectedly remain set, blocking future
ADC interrupts.
Workaround(s) 1. Use Continue-to-Interrupt Mode to prevent the ADCINTFLG from blocking additional
ADC interrupts:
ADCINTSEL1N2[INT1CONT] = 1;
ADCINTSEL1N2[INT2CONT] = 1;
ADCINTSEL3N4[INT3CONT] = 1;
ADCINTSEL3N4[INT4CONT] = 1;
2. Ensure there is always sufficient time to service the ADC ISR and clear the
ADCINTFLG before the next ADC interrupt occurs to avoid this condition.
3. Check for an overflow condition in the ISR when clearing the ADCINTFLG. Check
ADCINTOVF immediately after writing to ADCINTFLGCLR; if it is set, then write
ADCINTFLGCLR a second time to ensure the ADCINTFLG is cleared. The
ADCINTOVF register will be set, indicating an ADC conversion interrupt was lost.
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1) //ADCINT overflow
{AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 again
// If the ADCINTOVF condition will be ignored by the application
// then clear the flag here by writing 1 to ADCINTOVFCLR.
// If there is a ADCINTOVF handling routine, then either insert
// that code and clear the ADCINTOVF flag here or do not clear
// the ADCINTOVF here so the external routine will detect the
// condition.
// AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; // clear OVF
}

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Advisory ADC: DMA Read of Stale Result
Revision(s) Affected B, C
Details The ADCINT flag can be set before the ADCRESULT value is latched (see the tLAT and
tINT(LATE) columns in the ADC Timings table of the TMS320F2807x Microcontrollers Data
Manual). The DMA can read the ADCRESULT value as soon as 3 cycles after the
ADCINT trigger is set. As a result, the DMA could read a prior ADCRESULT value when
the user expects the latest result if all of the following are true:
• The ADC is in late interrupt mode.
• The ADC operates in a mode where tINT(LATE) occurs 3 or more cycles before tLAT
(ADCCTL2 [PRESCALE] > 2 for 12-bit mode).
• The DMA is triggered from the ADCINT signal.
• The DMA immediately reads the ADCRESULT value associated with that ADCINT
signal without reading any other values first.
• The DMA was idle when it received the ADCINT trigger.
Only the DMA reads listed above could result in reads of stale data; the following non-
DMA methods will always read the expected data:
• The ADCINT flag triggers a CLA task.
• The ADCINT flag triggers a CPU ISR.
• The CPU polls the ADCINT flag.
Workaround(s) Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy
transaction. This will result in enough delay that the second channel will always read the
fresh ADC result.
Advisory ADC: Random Conversion Errors
Revision(s) Affected B
Details The ADC may have errors at a rate as high as 1 in 106.5 ADC conversions. When a
conversion error occurs, it will be a significant random jump in the digital output of the
ADC without a corresponding change in the ADC input voltage, otherwise known as a
“sparkle code”. The magnitude of this jump will typically be in the range of 20 LSBs to
200 LSBs; however, larger or smaller jumps may occur.
Workaround(s) For the revisions affected, the error rate will be lower than 1 error in 1014.5 ADC
conversions when all of the following configurations are used:
• The S+H duration is at least 320 ns
• ADCCLK is 40 MHz or less
• ADCCLK prescale is a whole number: /1.0, /2.0, /3.0, /4.0, /5.0, /6.0, /7.0, or /8.0
• The value of 0x7000 is written to memory locations 0x0000 743F, 0x0000 74BF,
0x0000 753F, and 0x0000 75BF (writing this value is only valid when the ADCCLK
prescale is a whole number).
Advisory ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule
Revision(s) Affected B
Details The ADCxEVT trigger to the ePWM digital compare submodule may not be detected by
the ePWM.
Workaround(s) The ADCxEVT can generate an ADCx_EVT interrupt to the PIE. The ISR can be used to
perform the desired task in software.

AC
ADCINx
ADC
11.5 pF
Switch
Rs
Ron
CpCh
VREFLO
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Advisory ADC: 12-Bit Switch Resistance
Revision(s) Affected B
Details The ADC input model should be used to select the sample-and-hold (S+H) duration for
each ADC input. For the revisions affected, the 12-bit input model under-estimates the
value of the sampling switch resistance (Ron). A Ron value of 2 kΩshould be used to
select the S+H duration for these revisions.
Workaround(s) For the revisions affected, the S+H duration should be chosen to account for the
additional switch resistance.
Advisory ADC: 12-Bit Input Capacitance When Switching Channel Groups
Revision(s) Affected B
Details The ADC input model should be used to select the sample-and-hold (S+H) duration for
each ADC input. For the revisions affected, if the currently converting channel is an
even-numbered channel and the previously converted channel was an odd-numbered
channel (or vice versa), then the 12-bit input model will not accurately predict ADC input
performance. Under these conditions, an additional capacitance should be added to the
model. This capacitance has a value of 11.5 pF and should be placed between the S+H
switch and Ron as shown in Figure 3.
Figure 3. Single-Ended Input Model
Workaround(s) For the revisions affected, when subsequent conversions switch between channel
groups, the S+H duration should be chosen to account for the additional capacitance.

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory XRS may Toggle During Power Up
Revision(s) Affected B
Details During device power up, the XRS pin may toggle high prematurely. After the VDDIO and
VDD supplies reach the recommended operation conditions, the XRS pin behavior will be
per the pin description. This is only an issue with the external state of the XRS pin.
Internally, the device will be held in reset by the POR logic until the supplies are within
an acceptable range and XRS is high.
Workaround(s) Disregard XRS activity on the board prior to supplies reaching recommended operating
conditions.
Advisory USB: USB DMA Event Triggers are not Supported
Revision(s) Affected B, C
Details The USB module generates inadvertent extra DMA requests, causing the FIFO to
overflow (on IN endpoints) or underflow (on OUT endpoints). This causes invalid IN
DATA packets (larger than the maximum packet size) and duplicate receive data.
Workaround(s) None
Advisory VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ
Revision(s) Affected B
Details During power up of the 3.3-V VDDIO, the internal Voltage Regulator (VREG) will be active
until the 1.2-V VDD supply reaches approximately 0.7 V. After this time, the VREGENZ
pin tied to VDDIO will disable the internal VREG. This will not impact device operation.
Workaround(s) None

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR
Revision(s) Affected B, C
Details When a single-bit ECC error is detected, the CPU executes the single-bit-error interrupt
service routine (ISR). When the ISR returns, the same instruction that caused the first
error is fetched again. If the ECC error threshold (ERR_THRESHOLD.THRESHOLD)
is 0, then the same error is detected and another ISR is executed. This continues in an
endless loop. This sequence of events only occurs if the error is caused by a program
fetch operation, not a data read.
Workaround(s) Set the error threshold bit-field (ERR_THRESHOLD.THRESHOLD) to a value greater
than or equal to 1. Note that the default value of the threshold bit-field is 0.
Advisory Flash: Minimum Programming Word Size
Revision(s) Affected B, C
Details The Main Array flash programming must be aligned to 64-bit address boundaries and
each 64-bit word may only be programmed once per write/erase cycle.
Applications using Fapi_issueProgrammingCommand() in Fapi_AutoEccGeneration or
Fapi_DataAndEcc modes are implicitly performing 64-bit programming since ECC is
programmed for each 64 bits. Applications using Fapi_DataOnly mode with fewer than
64 bits may be impacted by this advisory.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each
128-bit word may only be programmed once. The exceptions are:
1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP
should be programmed together, and may be programmed 1 bit at a time as required
by the DCSM operation.
2. The DCSM Zx-LINKPOINTER3 value in the DCSM OTP may be programmed 1 bit at
a time as required by the DCSM operation.
Workaround(s) All applications should follow the restrictions outlined in this advisory. Contact TI for
devices already in production which violate this advisory.

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled
Revision(s) Affected B
Details The VCU-II can power up in a state which incorrectly sets the VCU VSTATUS[DIVE]
error bit and, subsequently PIEIFR12[INTx6], when the CPU is released from reset.
When the VCU interrupt enable PIEIER12[INTx6] is enabled for the first time by the
application, a spurious interrupt can occur due to the erroneous pending interrupt.
Workaround(s) Before enabling VCU interrupt 12.6, execute the following instructions to avoid the
spurious interrupt.
// Clear VCU divide by zero status
asm(" VCLRDIVE");
// Clear PIE interrupt for VCU
PieCtrlRegs.PIEIFR12.bit.INTx6 = 0;
Beginning with revision C silicon, the Boot ROM will perform the above workaround
before branching to the application.

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory eQEP: Position Counter Incorrectly Reset on Direction Change During Index
Revision(s) Affected B, C
Details While using the PCRM = 0 configuration, if the direction change occurs when the index
input is active, the position counter (QPOSCNT) could be reset erroneously, resulting in
an unexpected change in the counter value. This could result in a change of up to
±4 counts from the expected value of the position counter and lead to unexpected
subsequent setting of the error flags.
While using the PCRM = 0 configuration [that is, Position Counter Reset on Index Event
(QEPCTL[PCRM] = 00)], if the index event occurs during the forward movement, then
the position counter is reset to 0 on the next eQEP clock. If the index event occurs
during the reverse movement, then the position counter is reset to the value in the
QPOSMAX register on the next eQEP clock. The eQEP peripheral records the
occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index
event marker (QEPSTS[FIDF]) in QEPSTS registers. It also remembers the quadrature
edge on the first index marker so that same relative quadrature transition is used for
index event reset operation.
If the direction change occurs while the index pulse is active, the module would still
continue to look for the relative quadrature transition for performing the position counter
reset. This results in an unexpected change in the position counter value.
The next index event without a simultaneous direction change will reset the counter
properly and work as expected.
Workaround(s) Do not use the PCRM = 0 configuration if the direction change could occur while the
index is active and the resultant change of the position counter value could affect the
application.
Other options for performing position counter reset, if appropriate for the application
[such as Index Event Initialization (IEI)], do not have this issue.
Advisory eQEP: eQEP Inputs in GPIO Asynchronous Mode
Revision(s) Affected B, C
Details If any of the eQEP input pins are configured for GPIO asynchronous input mode via the
GPxQSELn registers, the eQEP module may not operate properly because the eQEP
peripheral assumes the presence of external synchronization to SYSCLKOUT on inputs
to the module. For example, QPOSCNT may not reset or latch properly, and pulses on
the input pins may be missed.
For proper operation of the eQEP module, input GPIO pins should be configured via the
GPxQSELn registers for synchronous input mode (with or without qualification), which is
the default state of the GPxQSEL registers at reset. All existing eQEP peripheral
examples supplied by TI also configure the GPIO inputs for synchronous input mode.
The asynchronous mode should not be used for eQEP module input pins.
Workaround(s) Configure GPIO inputs configured as eQEP pins for non-asynchronous mode (any
GPxQSELn register option except “11b = Asynchronous”).

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory PLL: May Not Lock on the First Lock Attempt
Revision(s) Affected B, C
Details The PLL may not start properly at device power up or wake up from Hibernate. The
PLLSTS[LOCKS] bit is set, but the PLL does not produce a clock.
Once the PLL has properly started, the PLL can be disabled and reenabled with no
issues and will stay locked. However, the PLL lock problem could reoccur on a
subsequent power-up or Hibernate cycle.
If the SYSPLL has not properly started and is selected as the CPU clock source, the
CPU will stop executing instructions. The occurrence rate of this transient issue is low
and after an initial occurrence, this issue may not be subsequently observed in the
system again. Implementation of the workaround reduces the rate of occurrence.
This advisory applies to both PLLs, with a different workaround for each.
Workaround(s) SYSPLL Workaround:
Repeated lock attempts will reduce the likelihood of seeing the condition on the final
attempt. TI recommends a minimum of five lock sequences in succession when the PLL
is configured the first time after a power up. A lock sequence means disabling the PLL,
starting the PLL locking, and waiting for the LOCKS bit to set. After the final sequence,
the clock source is switched to use the PLL output as normal.
The Watchdog timer can be used to detect that the condition has occurred because it is
not clocked by the PLL output. The Watchdog should be enabled before selecting the
PLL as the clock source and configured to reset the device. If the PLL is not producing a
clock, the Watchdog will reset the device and the user initialization software will therefore
repeat the PLL initialization.
Many applications do not have a different initialization sequence for a Watchdog-initiated
reset; for these applications, no further action is required. For applications that do use a
different device initialization sequence when a Watchdog reset is detected, a flag can be
used to identify the Watchdog reset as a PLL cause. The SYSDBGCTL[BIT_0] bit (which
is bit 0 at 0x0005D12C) can be set active during the PLL lock sequence and used to
distinguish a Watchdog PLL retry attempt versus a different Watchdog reset source.
The SYSPLLSTS[SLIPS] should also be checked immediately after setting the PLL as
the SYSCLK source with SYSPLLCTL1[PLLCLKEN]. If SLIPS indicates a PLL slip, then
the PLL should be disabled and locked again until there are no slips detected.
See the C2000Ware InitSysPll() function for an example implementation of this
workaround, as well as the DriverLib function SysCtl_setClock().
The workaround can also be applied at the System level by a supervisor resetting the
device if it is not responding.

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TMS320F2807x MCUs Silicon Revisions C, B
AUXPLL Workaround:
CPU Timer 2 can be used to detect that the AUXPLL is active before it is used as a
clock source for USB. If the AUXPLL is not active, repeat the lock attempt until
successful.
The AUXPLLSTS[SLIPS] should also be checked immediately after setting the PLL as
the AUXPLLCLK source with AUXPLLCTL1[PLLCLKEN]. If SLIPS indicates a PLL slip,
then the PLL should be disabled and locked again until there are no slips detected.
See the C2000Ware InitAuxPll() function for an example implementation of this
workaround, as well as the DriverLib function SysCtl_setAuxClock().
NOTE: The USB Boot Mode does not implement the previous workarounds.
Applications using USB Boot will need to implement any retry attempts at
the system level.
Advisory PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective
Revision(s) Affected B, C
Details When the PLL is powered down (that is, SYPLLCTL1.PLLEN = 0) or bypassed (that is,
SYSPLLCTL1.PLLCLKEN = 0), there is a necessary period of clock synchronization
before the PLL bypass completes. During this time, if PLLSYSCLKDIV (or other clock
divider) is set to a smaller value, the resulting system clock could be unexpectedly more
than the rated device frequency.
Implementing the workaround below will allow the PLL bypass operation to complete
before any other code is executed, ensuring expected device frequencies and proper
system operation.
Workaround(s) Add a software delay of 120 SYSCLK cycles using a NOP instruction while performing
either a PLL power down or a PLL bypass operation.
Example:
SYSPLLCTL1.PLLCLKEN = 0; // Bypassing the PLL
asm(" RPT #120 || NOP"); // Delay of 120 SYSCLK Cycles
SYSPLLCTL1.PLLEN = 0; // Powering down the PLL
asm(" RPT #120 || NOP"); // Delay of 120 SYSCLK Cycles
The latest released C2000Ware, which has this workaround implemented, can be used
as reference.

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and
OSR = 256
Revision(s) Affected B, C
Details If the differential input of the Sigma-Delta Filter Module (SDFM) is greater than or equal
to +FSR (full-scale differential voltage input range), then the output of the SDFM clips
with a stream of ones. When this stream of ones is fed to a data filter that is configured
as a sinc3 filter with an OSR = 256, the output of the filter does not saturate at the
maximum value (16777215 in 32-bit mode or 32767 in 16-bit mode); but, instead roll
over to the minimum value (–16777216 in 32-bit mode or –32768 in 16-bit mode).
Workaround(s) Maintain the differential input of the SDFM in the specified linear input range as specified
in the modulator data sheet.
Advisory SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and
Enabled for the First Time
Revision(s) Affected B, C
Details When the SDFM data filter is configured and enabled for the first time, it is possible to
get one spurious data acknowledge event (AFx) before the data filter settles to give
correct digital data. Subsequent data acknowledge events (AFx)/DMA events occur
correctly as per data filter configuration.
Workaround(s) Do the following:
1. Configure and enable the SDFM data filter.
2. Delay for at least latency of data filter + 5 SD-Cx clock cycles.
3. Enable SDFM data acknowledge interrupts/DMA events.
Advisory SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using
PWM FILRES Signal
Revision(s) Affected B, C
Details When the SDFM data filters are synchronized using the PWM FILRES signal, it is
possible to get a spurious data acknowledge event (AFx) before the data filter settles to
give correct digital data. Subsequent data acknowledge events (AFx) occur correctly as
per data filter configuration before the next PWM FILRES signal.
Workaround(s) Do the following:
1. Choose any PWMx to work in the same time base as the PWM that generates the
FILRES pulse.
2. PWMx should also interrupt the CPU/CLA at least 1.2 µs after the PWM FILRES
pulse gets applied in order to clear the SDIFLG register that may be set because of
the spurious data acknowledge event.
3. SDFM_CPUISR or SDFM_CLATask:
i. Collect the required number of samples, N, after the FILRES pulse.
ii. If the number of samples is less than or equal to N, clear the SDIFLG register;
otherwise, do not clear the SDIFLG register to prevent further SDFM interrupts.

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TMS320F2807x MCUs Silicon Revisions C, B
Advisory SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-
Value Conditions
Revision(s) Affected B, C
Details When interrupts are enabled in the SDFM comparator module, it may trigger spurious
over-value (SDIFLG.IEHx, x = 1 to 4) or under-value (SDIFLG.IELx, x = 1 to 4)
conditions. These are depicted as IELx and IEHx interrupt outputs in the “Block Diagram
of One Filter Module” figure in the TMS320F2807x Microcontrollers Technical Reference
Manual.
Workaround(s) These erroneous interrupts can be eliminated by implementing the following workaround:
• Comparator OSR (COSR) value should be greater than or equal to 5.
• After changing COSR, wait for at least latency of comparator filter and 5 SD-Cx
cycles before enabling comparator interrupts SDCPARMx.IEH and SDCPARMx.IEL.
Advisory SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR
Settings Will Trigger Spurious Comparator Events
Revision(s) Affected B, C
Details When SDFM comparator settings—such as filter type, lower/upper threshold, or
comparator OSR (COSR) settings—are dynamically changed during run time, spurious
comparator events will be triggered. The spurious comparator event will trigger a
corresponding CPU interrupt, CLA task, ePWM X-BAR events, and GPIO output X-BAR
events if configured appropriately.
Workaround(s) When comparator settings need to be changed dynamically, follow the procedure below
to ensure spurious comparator events do not generate a CPU interrupt or CLA task:
1. Disable the SDFM comparator interrupt.
2. Change comparator settings such as lower/upper threshold, filter type, or COSR.
3. COSR value should be greater than or equal to 5.
4. Delay for at least a latency of comparator filter + 5 SD-Cx clock cycles.
5. Enable the SDFM comparator interrupt.
When comparator settings need to be changed dynamically, follow the procedure below
to ensure spurious comparator events do not trigger X-BAR events (ePWM X-BAR and
GPIO output X-BAR events):
1. Disable the SDFM X-BAR trip events in the corresponding X-BAR registers (ePWM
X-BAR or GPIO X-BAR event).
2. Change comparator settings such as lower/upper threshold, filter type, or COSR.
3. COSR value should be greater than or equal to 5.
4. Delay for at least a latency of comparator filter + 5 SD-Cx clock cycles.
5. Enable the SDFM X-BAR trip events in the corresponding X-BAR registers (ePWM X-
BAR or GPIO X-BAR event).