
bq40z80EVM Circuit Module Schematic
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14 SLUUBZ5–November 2018
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bq40z80EVM Li-Ion Battery Pack Manager Evaluation Module
4 bq40z80EVM Circuit Module Schematic
This section contains information on modifying the EVM and using various features on the reference
design. The jumpers on the board allow different pin configurations. The pin configuration in the registers
must match the jumper configuration on the bq40z80EVM . The Pin Configuration register can be set in
the Data Memory section of bqStudio. If a register is set to an undefined setting, the output is configured
as high-Z.
Table 4. bq40z80 EVM-RevB Jumper and Pin Configuration Register Settings
General Description Pin Configuration Register Setting Jumper
Connections Comments
Pack connector with
SYS_PRES J1 Connect PACK+ and PACK– to the appropriate pins on
the battery pack
Header for cell
connections J12
Pin 1: 7P, Pin2: 6P, Pin3: 5P, Pin4: 4P, Pin5: 3P, Pin6:
2P, Pin7: 1P, Pin8: 1N(GND). If using less than 7 cells,
tie the unused cell pins (6P, 5P, etc) to the highest cell in
the stack
Pin
12
V7SENSE [MFP12_SEL2:MFP12_SEL0]=000
(EVM DEFAULT) J20[1,2], J7[1,2] Connects Pin 12 as V7SENSE to the middle of the
voltage divider
TS3 [MFP12_SEL2:MFP12_SEL0]=001 J20[2,3] Connects Pin 12 as TS3 to a 10k NTC
ADCIN1 [MFP12_SEL2:MFP12_SEL0]=010 J20[1,2], J7[2,3] Connects Pin 12 to Pin 1 of J11. Connect a voltage
between 0 V and 1 V to have the ADC read the voltage
at this pin
GPIO [MFP12_SEL2:MFP12_SEL0]=011
(DEVICE DEFAULT) J20[1,2], J7[2,3] Connects Pin 12 to Pin 1 of J11. Use this pin as a GPIO
Pin
13
/DISP [MFP13_SEL2:MFP13_SEL0]=000
(EVM DEFAULT) J21[1,2], J14[1,2] Connects Pin 13 (/DISP) to TP5 and S3
TS4 [MFP13_SEL2:MFP13_SEL0]=001 J21[2,3] Connects Pin 12 as TS4 to a 10k NTC
ADCIN2 [MFP13_SEL2:MFP13_SEL0]=010 J21[1,2], J14[2,3] Connects Pin 13 to Pin 5 of J11. Connect a voltage
between 0 V and 1 V to have the ADC read the voltage
at this pin
GPIO [MFP13_SEL2:MFP13_SEL0]=011
(DEVICE DEFAULT) J21[1,2], J14[2,3] Connects Pin 13 to Pin 5 of J11. Use this pin as a GPIO
Pin
15
VC7EN [MFP15_SEL1:MFP15_SEL0]=00
(EVM DEFAULT) J6[1,2] Connects Pin 15 (VC7EN) to the gate of Q6 to enable
the voltage divider so a scaled voltage of the top of stack
is applied to VC7SENSE
/DISP [MFP15_SEL1:MFP15_SEL0]=01 J6[2,3], J8[1,2] Connects Pin 15 (/DISP) to TP5 and S3
GPIO [MFP15_SEL1:MFP15_SEL0]=10
(DEVICE DEFAULT) J6[2, 3], J8[2, 3] Connects Pin 15 (GPIO) to Pin 2 of J11
Pin
16
CB7EN [MFP16_SEL1:MFP16_SEL0]=00
(EVM DEFAULT) J10[1,2] Connects Pin 17 (CB7EN) to the gate of Q11 for external
cell balancing for the 7th cell
PDSG [MFP16_SEL1:MFP16_SEL0]=01 J10[2, 3], J9[1,2] Connects Pin 16 (PDSG) to the gate of Q7 to enable pre-
discharge through Q5
GPIO [MFP16_SEL1:MFP16_SEL0]=10
(DEVICE DEFAULT) J10[2,3], J9[2,3] Connects Pin 62 to Pin 4 of J11. Use this pin as a GPIO
Pin
17
/PRES [MFP17_SEL2:MFP17_SEL0]=000
(EVM DEFAULT) J5[1,2] Connects Pin 17 (/PRES) to Pin 3 of J2
SHUTDN [MFP17_SEL2:MFP17_SEL0]=001 J5[1,2] Connects Pin 17 (/SHUTDN) to S3 pushbutton
/DISP [MFP17_SEL2:MFP17_SEL0]=010 J5[2,3], J3[1,2] Connects Pin 17 (/DISP) to TP5 and S2
PDSG [MFP17_SEL2:MFP17_SEL0]=011 J5[2,3], J3[2, 3],
J4[1,2] Connects Pin 17 (PDSG) to the gate of Q7 to enable pre-
discharge through Q5
GPIO [MFP17_SEL2:MFP17_SEL0]=100
(DEVICE DEFAULT) J5[2,3], J3[2,3],
J4[2,3] Connects Pin 17 (GPIO) to Pin 3 of J11
Pin
20
LEDCNTLA [MFP20_SEL2:MFP20_SEL0]=000
(EVM DEFAULT) J15[2,3] Connects pin 20 to LEDs to be used as LEDCNTLA.
Must be used with LEDCNTLB and LEDCNTLC
PDSG [MFP20_SEL2:MFP20_SEL0]=010 J15[1,2], J13[1,2] Connects pin 20 (PDSG) to the gate of Q7 to enable pre-
discharge through Q5. In this mode, Pins 21 and Pin 22
are used as GPIOs.
GPIO [MFP20_SEL2:MFP20_SEL0]=001
(DEVICE DEFAULT) J15[1,2], J13[2,3] Connects Pin 20 to Pin 6 of J11. Use this pin as a GPIO