Texas instruments Ads9817evm-pdk User manual

EVM User's Guide: ADS9817EVM-PDK

ADS9817EVM-PDK Evaluation Module

ABSTRACT

This user's guide describes the characteristics, operation, and use of the ADS9817EVM-PDK evaluation module

(EVM) performance demonstration kit (PDK). This kit is an evaluation platform for the ADS9817, which is an

8-channel, 18-bit, 2-MSPS per channel, single-ended input, successive approximation register (SAR) analog-

to-digital converter (ADC) with a complementary metal oxide semiconductor (CMOS) digital interface. The

EVM-PDK also includes an adapter printed circuit board (PCB) that facilitates connection to a standard FPGA

mezzanine card (FMC) connecter used in many field-programmable gate array (FPGA) kits. The EVM-PDK

eases the evaluation of the ADS9817 device with hardware, software, and computer connectivity through

the universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic

diagrams, and a bill of materials (BOM). Throughout this document, the terms demonstration kit, evaluation

board, evaluation module, EVM, and EVM-PDK are synonymous with the ADS9817EVM-PDK.

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Table of Contents

1 Overview .................................................................................................................................................................................3

1.1 ADS9817EVM-PDK Features............................................................................................................................................ 3

2 Analog Interface......................................................................................................................................................................5

2.1 ADS9817 Device Connections...........................................................................................................................................5

2.2 Input SMA Connections..................................................................................................................................................... 6

3 Digital Interface.......................................................................................................................................................................7

4 Power Supplies....................................................................................................................................................................... 8

5 EVM Operation........................................................................................................................................................................ 9

5.1 ADS9817EVM Software Installation...................................................................................................................................9

5.2 USB Driver Installation..................................................................................................................................................... 10

5.3 Connecting the Hardware and Starting the Software.......................................................................................................12

5.4 Initial Required Setup on the Config Tab..........................................................................................................................13

5.5 Initial Required Setup on the Capture Tab....................................................................................................................... 14

5.6 Using the INL/DNL Tool....................................................................................................................................................15

6 Bill of Materials, Schematics, and Layout.......................................................................................................................... 16

6.1 Bill of Materials (BOM)..................................................................................................................................................... 16

6.2 Schematics.......................................................................................................................................................................18

6.3 Layout.............................................................................................................................................................................. 22

List of Figures

Figure 1-1. System Using FMC to VITA57 and FPGA Kit............................................................................................................3

Figure 1-2. System Using GUI and TSWDC155EVM..................................................................................................................4

Figure 1-3. ADS9817EVM Block Diagram...................................................................................................................................4

Figure 2-1. Connections to ADS9817.......................................................................................................................................... 5

Figure 2-2. Input SMA Connections Digital Interface...................................................................................................................6

Figure 3-1. Digital I/O...................................................................................................................................................................7

Figure 4-1. Power Entry and Regulators..................................................................................................................................... 8

Figure 5-1. Initial Software Installation.........................................................................................................................................9

Figure 5-2. Installation Process................................................................................................................................................. 10

Figure 5-3. Open Device Manager............................................................................................................................................ 10

Figure 5-4. Update Driver With Device Manager....................................................................................................................... 11

Figure 5-5. Connecting the Hardware........................................................................................................................................12

Figure 5-6. Start the Software GUI............................................................................................................................................ 12

Figure 5-7. Initial Required Setup on the Config Tab.................................................................................................................13

Figure 5-8. Initial Required Setup on the Capture Tab.............................................................................................................. 14

Figure 5-9. Using the INL/DNL Tool...........................................................................................................................................15

Figure 6-1. ADS9817 Device Connections................................................................................................................................ 18

Figure 6-2. SMA Input Signal Connections................................................................................................................................19

Figure 6-3. Digital Connector.....................................................................................................................................................20

Figure 6-4. Power Connections and Regulators........................................................................................................................21

Figure 6-5. ADS9817 PCB Layout Top......................................................................................................................................22

Figure 6-6. ADS9817 PCB Layout Bottom................................................................................................................................ 23

List of Tables

Table 1-1. Related Documentation.............................................................................................................................................. 3

Table 6-1. ADS9817EVM-PDK Bill of Materials.........................................................................................................................16

Trademarks

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

All trademarks are the property of their respective owners.

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1 Overview

The ADS9817EVM-PDK is a platform for evaluating the performance of the ADS9817 SAR ADC, which is a

±2.5-V, ±5-V, ±10-V, and ±12-V, single-ended input, 18-bit, 2-MSPS/Ch device. The evaluation kit includes the

ADS9817EVM board and an FMC connecter adapter board used to interface the ADC with many FPGA kits. The

TSWDC155EVM (sold separately) is a digital controller board that can be used with this evaluation kit and the

EVM software GUI to communicate with the device, graph measured results, and compute common figures of

merit (such as SNR and THD).

The following related documents are available for download through the Texas Instruments web site at

www.ti.com.

Table 1-1. Related Documentation

Device Literature Number

TSWDC155EVM SLAU870

TPS61070 SLVS510

TPS7A20 SBVS338

LM66100 SLVSEZ8

1.1 ADS9817EVM-PDK Features

The ADS9817EVM-PDK includes the following features:

• Hardware and software required for diagnostic testing and accurate performance evaluation of the ADS9817

ADC

• The FMC connecter adapter board, as shown in Figure 1-1, facilitates connection to common FPGA kits

• The TSWDC155EVM controller (sold separately) requires a separate 5-V, 2-A power source; the

ADS9817EVM requires a separate 5.5-V, 1-A power source

• The TSWDC155EVM controller (sold separately) provides a convenient communication interface (see Figure

1-2) to the ADS9817 ADC over USB 3.0 (or higher) for power delivery and for digital inputs and outputs

• Easy-to-use evaluation software (no cost) for Microsoft® Windows® 10, 64-bit operating systems requires the

TSWDC155EVM (sold separately) for operation

• The software suite (no cost) includes graphical tools for data capture, histogram analysis, spectral analysis,

SNR, and THD

•Figure 1-3 depicts the connections and basic subsystems of the EVM

Included in kit

ADS9817EVM FMCtoVITA57

Not provided

by Texas

Instruments

Your custom

so



ware

FPGA Kit

5.2V to 5.5V

DC power

Signal

Source

Signal

Source

Figure 1-1. System Using FMC to VITA57 and FPGA Kit

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Included in kit

ADS9817EVM

TSWDC155EVM

ADS9817

GUI

Signal

Source

Sold Separately

from Texas

Instruments

5.2V to 5.5V

DC power

SMI18-5-V-P5

5V DC wall supply

Signal

Source

Figure 1-2. System Using GUI and TSWDC155EVM

Power

FMC connector

Power

SMASMA

ADS9817

AIN1M AIN1P

AIN8M

AIN8P

AIN7M

AIN7P

SMASMA

AIN7M AIN7P

SMASMA

AIN7M AIN7P

SMASMA

AIN7M AIN7P

SMASMA

AIN7M AIN7P

SMASMA

AIN2M AIN2P

Figure 1-3. ADS9817EVM Block Diagram

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2 Analog Interface

As an analog interface, the evaluation board directly connects the inputs of the ADS9817 to input signals using

subminiature version A (SMA) connectors. The ADS9817 includes an integrated voltage reference available on

pin 52 of the device and can be monitored using the REFIO test point. The inputs also have an optional filter.

This section also covers the decoupling capacitors and digital signal connections.

2.1 ADS9817 Device Connections

The digital communications lines for the ADC (shown in Figure 2-1) are CMOS interface and are connected with

optional termination resistors. A digital serial peripheral interface (SPI) port is used to configure registers in the

device. The SDO output line includes a termination. Figure 2-1 also shows the analog inputs and the decoupling

and filter capacitors.

AIN1M

55 AIN1P

54

AIN2M

2 AIN2P

1

AIN3M

4 AIN3P

3

AIN4M

6 AIN4P

5

AIN5M

10 AIN5P

9

AIN6M

12 AIN6P

11

AIN7M

14 AIN7P

13

AIN8M

17 AIN8P

16

SMPL_CLK 44

SMPL_SYNC 45

CS 25

PWDN 32

RESET 31

D0 34

D1 35

D2 36

D3 37

DCLKIN 43

DCLKOUT 33

FCLKOUT 40

SCLK 26

SDI 27

SDO 28

SPI_EN 24

VBIAS

20

NC

38

NC

39

NC

50

NC

51

ADS9817IRSHT

U1A

AVDD_1V8

21

AVDD_1V8

49

AVDD_5V

15

AVDD_5V

56

DVDD_1V8

22

DVDD_1V8

47

DVDD_1V8

48

IOVDD

30

IOVDD

41

AGND 7

DGND 23

DGND 46

IOGND 29

IOGND 42

Thermal_Pad 57

REFM 8

REFM 18

REFOUT_2V5 19

REFIO 52

REFM 53

ADS9817IRSHT

U1B

10V

1µF

C19

10V

0.1µF

C20

10V

0.1µF

C21

GND GND GND

5V

10V

1µF

C15

10V

0.1µF

C16

GND GND

10V

0.1µF

C23

GND

1V8_VDD

10V

0.1µF

C24

10V

0.1µF

C25

GND GND

1V8_IOVDD

GND

NT1

Net-Tie

GND

10V

1µF

C22

GND

AIN1P

AIN1M

AIN2P

AIN2M

AIN3P

AIN3M

AIN4P

AIN4M

AIN5P

AIN5M

AIN6P

AIN6M

AIN7P

AIN7M

AIN8P

AIN8M

VBIAS

REFOUT_2V5

REFIO

TP2

TP1

RESETz

SMPL_CLK

SMPL_SYNC

DCLKOUT

FCLKOUT

D0

D1

D2

D3

SPI_EN

CSz

SCLK

SDI

SDO

PWDNz

DCLKOUT

FCLKOUT

DATA_D0

DATA_D1

DATA_D2

DATA_D3

SPI_EN

SCLK

CSz

SDI

SDO

PWDNz

RESETz

SMPL_CLK

SMPL_SYNC

33

R10

33

R11

33

R12

33

R13

33

R14

33

R15

33

R22

Figure 2-1. Connections to ADS9817

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2.2 Input SMA Connections

Each input is connected to two SMA connectors. The positive input connector (for example, AIN1P) is connected

to a ±5-V signal. The negative input connector (for example, AIN1M) is normally connected to GND with a

jumper connection (for example, J19). Alternatively, the negative input connector can be used to measure the

local sensors ground. The negative input has a range of ±0.3 V. Figure 2-2 shows the input connections for a

digital interface.

GND

AIN1P

AIN1M

0

R4

50V

10pF

C9

DNP

0

R8

GND

10k

R6

DNP

1

2

J19

1

2

3

4

5

J1

GND

1

2

3

4

5

J2

Figure 2-2. Input SMA Connections Digital Interface

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3 Digital Interface

The ADS9817 uses an SPI interface to configure the registers (SCLK, SDI, SDO, CS, and SPI_EN). The

ADS9817 uses a CMOS interface for capturing conversion data for each ADC channel (D0, D1, D2, and D3).

The SPI and CMOS signals connect to the FMC connector. Figure 3-1 provides the FMC connector signal

definition. These signals are also available on tented via test points for scope measurements. Top overlay text

indicates the location of these test points.

SDI

SCLK

CSz

SDO

D3

D2

D1

D0

FCLKOUT

DCLKOUT

FX3_I2C_SCL

FX3_I2C_SDA

SPI_EN

RESETz

PWDNz

SPRW_SUP_3P3

SPRW_SUP_2P5

SPRW_SUP_1P8

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

J27A

ASP-134486-01

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

J27B

ASP-134486-01

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

J27C

ASP-134486-01

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

J27D

ASP-134486-01

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E40

J27E

ASP-134486-01

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F40

J27F

ASP-134486-01

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

G31

G32

G33

G34

G35

G36

G37

G38

G39

G40

J27G

ASP-134486-01

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

H31

H32

H33

H34

H35

H36

H37

H38

H39

H40

J27H

ASP-134486-01

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J31

J32

J33

J34

J35

J36

J37

J38

J39

J40

J27I

ASP-134486-01

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K40

J27J

ASP-134486-01

SMPL_CLK

SMPL_SYNC

GND GND GND GND GND

GNDGNDGNDGNDGND

Figure 3-1. Digital I/O

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4 Power Supplies

The TSWDC155EVM can provide power using the 3.3-V supply, but is not enabled by default on the

TSWDC155EVM. Typical use requires external power on J17. The TSWDC155EVM provides the ADS9817EVM

with a 3.3-V supply. The ADS9817EVM has a TPS61070 boost converter that boosts the 3.3-V supply to 5.4

V. This voltage is applied to low-dropout regulators (LDOs) to derive the AVDD and the DVDD supply. The

TPS7A2050 provides the 5-V AVDD supply and the TPS7A2018 provides the 1.8-V DVDD supply. The required

power connection is made through jumper J18 and can be set to allow external power to be applied on screw

terminal J17. In this case U2, an LM66100 device, provides reverse polarity protection if the connection is

miswired. Figure 4-1 shows a schematic for various protection circuits.

1

2

J17

GND

OUT 5

GND 2

IN

1

EN

3

NC

4

TPS7A2050PDBVR

U3

5V

GND

1µF

16V

C1

1µF

16V

C2

GND GND

IN

1

GND

2

CE

3 N/C 4

ST 5

OUT 6

LM66100DCKR

U2

GND

1V8_VDD

GND

1µF

16V

C3

1µF

16V

C4

GND GND

1V8_IOVDD

GND

1µF

16V

C7

1µF

16V

C8

GND GND

2.2k

R1

Green

12

D2

APT2012LZGCK

GND

AVDD

VDD

IOVDD

EN

3

IN

1

NC

4

OUT 5

GND 2

TPS7A2018PDBVR

U4

EN

3

IN

1

NC

4

OUT 5

GND 2

TPS7A2018PDBVR

U6

SW 1

GND

2

EN

3

FB 4

VOUT 5

VBAT

6

TPS61070DDCR

U5

10uH

L1

GND

16V

10uF

C5

GND

1.96M

R2

200k

R3

GND

25V

22µF

C6

GND

SPRW_SUP_3P3

LDO_IN

6V

D1

SMBJ6.0CA

GND

1

2

3

J18

Figure 4-1. Power Entry and Regulators

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5 EVM Operation

5.1 ADS9817EVM Software Installation

This section discusses the installation and operation of the ADS9817EVM software graphical user interface

(GUI). This software requires the TSWDC155EVM (sold separately) controller to operate. The first steps to

installing the software (as shown in Figure 5-1) is to download the latest version of the EVM GUI installer from

the Tools and Software folder of the ADS9817EVM, and run the GUI installer to install the EVM GUI software

on your computer. Accept all the license agreements and choose the destination location, project directory, and

start menu. Typically, the default values work, but these values can be customized as needed based on your

requirements.

Figure 5-1. Initial Software Installation

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Next, the installer prompts you to create a desktop icon and summarize the installation plan. Pressing Install

begins copying software onto your computer. This process takes a few minutes. At completion, you can launch a

readme text file and the application. Figure 5-2 shows these steps.

C:\Program Files\Texas Instruments\ads92xx_1v0\bin

Figure 5-2. Installation Process

5.2 USB Driver Installation

This section describes the steps for installing the USB driver.

1. For the TSWDC155, connect J8 to the workstation using a USB-C to USB-A cable

2. Open the Windows® Device Manager, as shown in Figure 5-3, and right-click on the WestBridge folder in the

Device Manager window and select the Update Driver button (see Figure 5-4)

3. In the next window that appears, select Browse my computer for driver software.

4. Then select Let me pick from a list of available drivers on my computer in the next pop-up window

5. Click on Have Disk in the pop-up window and navigate to C:\Program Files\Texas

Instruments\ADS98xx\bin\proj_lib\Sparrow\Bootloader

Figure 5-3. Open Device Manager

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Figure 5-4. Update Driver With Device Manager

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5.3 Connecting the Hardware and Starting the Software

1. Connect the EVM and set the jumpers as shown in Figure 5-5 after installing the software.

2. Connect a 5-V wall-wart connector or other power source for the TSWDC155EVM (sold separately). The

TSWDC155EVM user guide provides information on this power source.

3. Physically connect J1 of the TSWDC155EVM to J27 of the ADS9817EVM. This component is the digital

communications and power signal connection.

4. Connect the USB on the TSWDC155EVM to the computer.

5. Set jumper J18 to the FMC_PWR position to allow for an external power connection. Connect an external

5.2-V to 5.5-V supply on screw terminal connection J17.

6. Start the software GUI as described in Figure 5-6.

7. Press the Initialize USB, Power Up, Program FPGA, and Initialize ads92xx buttons on the Config tab to

power up and configure the EVM (see Figure 5-8 for details).

8. Connect a single-ended, ±5.0-V signal generator.

9. Press the EN SYNC button on the Capture tab. Select the number of samples to be at least 32k, and choose

the Hanning window type for best frequency domain results. Press the Start Capture button to collect and

analyze the data; see Figure 5-8.

TSWDC155

(DC155A)

J5, J6, J29, J33

J8: USB-C to USB-A cable

J13: 5V, 3A, 15W power adapter

( or Bench supply)

J17: 5.3V -5.5V, 1A,

Bench supply J18 in EXT_PWR

posi



on

ADS9218EVM

(MED1613E2)

Jumpers shor



ng

nega



ve input to

GND as needed:

J19 … J26

Figure 5-5. Connecting the Hardware

Select the GUI from

the start menu

Figure 5-6. Start the Software GUI

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5.4 Initial Required Setup on the Config Tab

After the EVM GUI is started, press the Initialize USB, Power Up, Program FPGA, and Initialize ADS98xx

buttons to setup the initial configurations. As shown in Figure 5-7, press these buttons in order from top to

bottom. Wait after each button press for the status to indicate that the step is complete. For the Power Up and

Program FPGA buttons, some status LEDs on the hardware illuminate. The power-up step takes the longest

time (approximately 30 seconds). After all four buttons are pressed, the power on the ADS9817EVM is on and

the ADS9817 device registers are configured.

Press the bu



ons circled below.

Wait a



er each bu



on press for

the status to indicate that the

step is complete.

Figure 5-7. Initial Required Setup on the Config Tab

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5.5 Initial Required Setup on the Capture Tab

In Figure 5-8, the device and EVM are powered up and configured. In this step, the necessary updates to the

Capture settings are made to capture the time domain data and to get a good frequency domain result. First, the

EN SYNC button is pressed to synchronize the communication channel. Next, update the number of samples to

at least 32k to get good frequency domain results (for example, accurate FFT display, SNR data, and THD data).

Finally, select the Hanning type window to eliminate spectral leakage in the FFT result.

When these changes are made, press the Start Capture button to collect time domain and frequency domain

data. Select the appropriate tab to view data for channel 1 or channel 2.

1. Select “capture tab for



me domain and FFT

analysis

2. Press “EN SYNC”

3. Choose at least 32k

samples for good FFT results.

4. Press start capture to

collect data

5. Measured SNR,

SINAD, and THD shown

here.

Figure 5-8. Initial Required Setup on the Capture Tab

EVM Operation www.ti.com

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5.6 Using the INL/DNL Tool

The INL/DNL tool measures the linearity of the of the ADS9817EVM by applying a full-scale, low-distortion

sinusoidal input signal. The accuracy improves if the number of hits per code is increased at the cost of extra

test time. Select the channel to measure and the hits per code, then press the GET INL/DNL button (as shown in

Figure 5-9) to run this tool.

1. Select “INL/DNL”

2. Select the hits-percode for

linearity analysis. More hits

produces more accurate results

at the cost of test time.

128 = 120 seconds

3. Select channel to

analyze, and press “GET

INL/DNL”

Figure 5-9. Using the INL/DNL Tool

www.ti.com EVM Operation

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ADS9817EVM-PDK Evaluation Module 15

6 Bill of Materials, Schematics, and Layout

This section contains the ADS9817EVM-PDK bill of materials (BOM), printed-circuit board (PCB) layout, and

schematics.

6.1 Bill of Materials (BOM)

Table 6-1 lists the ADS9817EVM-PDK BOM.

Table 6-1. ADS9817EVM-PDK Bill of Materials

Designator Quantity Value Description PackageRefer

ence

PartNumber Manufacturer

!PCB1 1 Printed Circuit Board MED1604 Any

AVDD, IOVDD,

VDD

3 Test Point, Compact, SMT Testpoint_Keys

tone_Compact

5016 Keystone

Electronics

C1, C2, C3, C4,

C7, C8

6 1uF CAP, CERM, 1 uF, 16 V, +/- 10%,

X7R, 0603

0603 C1608X7R1C105K080

AC

TDK

C5 1 10uF CAP, CERM, 10 uF, 16 V, +/- 10%,

X7R, 1206

1206 GRM31CR71C106KAC

7L

MuRata

C6 1 22uF CAP, CERM, 22 µF, 25 V,+/- 10%,

X7R, AEC-Q200 Grade 1, 1210

1210 TMK325B7226KMHP Taiyo Yuden

C15, C19, C22 3 1uF CAP, CERM, 1 µF, 10 V,+/- 10%,

X7R, 0603

0603 0603ZC105KAT4A AVX

C16, C20, C21,

C23, C24, C25

6 0.1uF CAP, CERM, 0.1 µF, 10 V,+/- 10%,

X7R, 0402

0402 C0402C104K8RACTU Kemet

D1 1 6V Diode, TVS, Bi, 6 V, SMB SMB SMBJ6.0CA Littelfuse

D2 1 Green LED, Green, SMD LED_0805 APT2012LZGCK Kingbright

H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x

1/4, Nylon, Philips panhead

Screw NY PMS 440 0025 PH B&F Fastener

Supply

H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone

H9, H10, H11,

H12

4 Bumpon, Hemisphere, 0.44 X

0.20, Clear

Transparent

Bumpon

SJ-5303 (CLEAR) 3M

J1, J2, J3, J4,

J5, J6, J7, J8,

J9, J10, J11,

J12, J13, J14,

J15, J16

16 SMA Connector Jack, Female

Socket 50Ohm Through Hole

Solder

CONN_SMA_P

TH

60312002114503 Wurth Electronics

J17 1 Terminal Block, 3.5mm Pitch, 2x1,

TH

7.0x8.2x6.5mm ED555/2DS On-Shore

Technology

J18 1 Header, 100mil, 3x1, Gold, TH Header,

100mil, 3x1,

TH

HTSW-103-07-G-S Samtec

J19, J20, J21,

J22, J23, J24,

J25, J26

8 Header, 100mil, 2x1, Gold, TH Header,

100mil, 2x1,

TH

HTSW-102-07-G-S Samtec

J27 1 Socket, 1.27mm, 40x10, Black,

SMT

Connector,

1.27mm,

40x10, SMT

ASP-134486-01 Samtec

L1 1 10uH Inductor, Wirewound, Ceramic, 10

uH, 0.48 A, 0.36 ohm, SMD

2.5x1.8x1.8mm CBC2518T100M Taiyo Yuden

Bill of Materials, Schematics, and Layout www.ti.com

16 ADS9817EVM-PDK Evaluation Module SBAU416 – NOVEMBER 2022

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Table 6-1. ADS9817EVM-PDK Bill of Materials (continued)

Designator Quantity Value Description PackageRefer

ence

PartNumber Manufacturer

LBL1 1 Thermal Transfer Printable Labels,

0.650" W x 0.200" H - 10,000 per

roll

PCB Label

0.650 x 0.200

inch

THT-14-423-10 Brady

R1 1 2.2k RES, 2.2 k, 5%, 0.063 W, 0402 0402 CRCW04022K20JNED Vishay-Dale

R2 1 1.96Meg RES, 1.96 M, 1%, 0.063 W, 0402 0402 CRCW04021M96FKED Vishay-Dale

R3 1 200k RES, 200 k, 1%, 0.063 W, 0402 0402 CRCW0402200KFKED Vishay-Dale

R4, R5, R8, R9,

R16, R17, R20,

R21, R23, R24,

R27, R28, R29,

R30, R33, R34

16 0 RES, 0, 5%, 0.1 W, AEC-Q200

Grade 0, 0402

0402 ERJ-2GE0R00X Panasonic

R10, R11, R12,

R13, R14, R15,

R22

7 33 RES, 33, 5%, 0.063 W, 0402 0402 CRCW040233R0JNED Vishay-Dale

U1 1 18-Bit, 8-MSPS, Dual,

Simultaneous Sampling ADC with

Integrated Analog Front-End

QFN56 ADS9817IRSHT Texas Instruments

U2 1 +/-6V, Low IQ Ideal Diode

with Input Polarity Protection,

DCK0006A (SOT-SC70-6)

DCK0006A LM66100DCKR Texas Instruments

U3 1 300-mA, ultra-low-noise, low-IQ,

low-dropout (LDO) linear regulator

with high PSRR 5-SOT-23 -40 to

125

SOT23-5 TPS7A2050PDBVR Texas Instruments

U4, U6 2 Linear Voltage Regulator IC

Positive Fixed 1 Output 300mA

SOT-23-5

SOT23-5 TPS7A2018PDBVR Texas Instruments

U5 1 Adjustable, 600-mA Switch,

90% Efficient PFM/PWM Boost

Converter in ThinSOT-23,

DDC0006A (SOT-23-T-6)

DDC0006A TPS61070DDCR Texas Instruments

C9, C10, C11,

C12, C13, C14,

C17, C18

0 10pF CAP, CERM, 10 pF, 50 V,+/- 1%,

C0G/NP0, 0402

0402 GRM1555C1H100FA01

D

MuRata

FID1, FID2,

FID3, FID4,

FID5, FID6

0 Fiducial mark. There is nothing to

buy or mount.

N/A N/A N/A

R6, R7, R18,

R19, R25, R26,

R31, R32

0 10k RES, 10 k, 5%, 0.063 W, 0402 0402 CRCW040210K0JNED Vishay-Dale

www.ti.com Bill of Materials, Schematics, and Layout

SBAU416 – NOVEMBER 2022

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ADS9817EVM-PDK Evaluation Module 17

6.2 Schematics

Figure 6-1 through Figure 6-4 show the various connections to the ADS9817 device. The digital signals connect

to J27, and the analog signals connect to SMA connectors and input filtering. Figure 6-1 also shows the

decoupling for the device.

AIN1M

55 AIN1P

54

AIN2M

2 AIN2P

1

AIN3M

4 AIN3P

3

AIN4M

6 AIN4P

5

AIN5M

10 AIN5P

9

AIN6M

12 AIN6P

11

AIN7M

14 AIN7P

13

AIN8M

17 AIN8P

16

SMPL_CLK 44

SMPL_SYNC 45

CS 25

PWDN 32

RESET 31

D0 34

D1 35

D2 36

D3 37

DCLKIN 43

DCLKOUT 33

FCLKOUT 40

SCLK 26

SDI 27

SDO 28

SPI_EN 24

VBIAS

20

NC

38

NC

39

NC

50

NC

51

ADS9817IRSHT

U1A

AVDD_1V8

21

AVDD_1V8

49

AVDD_5V

15

AVDD_5V

56

DVDD_1V8

22

DVDD_1V8

47

DVDD_1V8

48

IOVDD

30

IOVDD

41

AGND 7

DGND 23

DGND 46

IOGND 29

IOGND 42

Thermal_Pad 57

REFM 8

REFM 18

REFOUT_2V5 19

REFIO 52

REFM 53

ADS9817IRSHT

U1B

10V

1µF

C19

10V

0.1µF

C20

10V

0.1µF

C21

GND GND GND

5V

10V

1µF

C15

10V

0.1µF

C16

GND GND

10V

0.1µF

C23

GND

1V8_VDD

10V

0.1µF

C24

10V

0.1µF

C25

GND GND

1V8_IOVDD

GND

NT1

Net-Tie

GND

10V

1µF

C22

GND

AIN1P

AIN1M

AIN2P

AIN2M

AIN3P

AIN3M

AIN4P

AIN4M

AIN5P

AIN5M

AIN6P

AIN6M

AIN7P

AIN7M

AIN8P

AIN8M

VBIAS

REFOUT_2V5

REFIO

TP2

TP1

RESETz

SMPL_CLK

SMPL_SYNC

DCLKOUT

FCLKOUT

D0

D1

D2

D3

SPI_EN

CSz

SCLK

SDI

SDO

PWDNz

DCLKOUT

FCLKOUT

DATA_D0

DATA_D1

DATA_D2

DATA_D3

SPI_EN

SCLK

CSz

SDI

SDO

PWDNz

RESETz

SMPL_CLK

SMPL_SYNC

33

R10

33

R11

33

R12

33

R13

33

R14

33

R15

33

R22

Figure 6-1. ADS9817 Device Connections

Bill of Materials, Schematics, and Layout www.ti.com

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GND

AIN1P

AIN1M

0

R4

50V

10pF

C9

DNP

0

R8

GND

10k

R6

DNP

AIN2P

AIN2M

0

R16

50V

10pF

C11

DNP

0

R20

10k

R18

DNP

AIN3P

AIN3M

0

R23

50V

10pF

C13

DNP

0

R27

10k

R25

DNP

AIN4P

AIN4M

0

R29

50V

10pF

C17

DNP

0

R33

10k

R31

DNP

AIN5P

AIN5M

0

R5

50V

10pF

C10

DNP

0

R9

10k

R7

DNP

AIN6P

AIN6M

0

R17

50V

10pF

C12

DNP

0

R21

10k

R19

DNP

AIN7P

AIN7M

0

R24

50V

10pF

C14

DNP

0

R28

10k

R26

DNP

AIN8P

AIN8M

0

R30

50V

10pF

C18

DNP

0

R34

10k

R32

DNP

GND

1

2

J19

1

2

J23

1

2

J20

1

2

J24

1

2

J21

1

2

J25

1

2

J22

1

2

J26

1

2

3

4

5

J1

GND

1

2

3

4

5

J2

GND

1

2

3

4

5

J9

GND

1

2

3

4

5

J10

GND

1

2

3

4

5

J3

GND

1

2

3

4

5

J4

GND

1

2

3

4

5

J11

GND

1

2

3

4

5

J12

GND

1

2

3

4

5

J5

GND

1

2

3

4

5

J6

GND

1

2

3

4

5

J7

GND

1

2

3

4

5

J8

GND

1

2

3

4

5

J13

GND

1

2

3

4

5

J14

GND

1

2

3

4

5

J15

GND

1

2

3

4

5

J16

Figure 6-2. SMA Input Signal Connections

www.ti.com Bill of Materials, Schematics, and Layout

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ADS9817EVM-PDK Evaluation Module 19

SDI

SCLK

CSz

SDO

D3

D2

D1

D0

FCLKOUT

DCLKOUT

FX3_I2C_SCL

FX3_I2C_SDA

SPI_EN

RESETz

PWDNz

SPRW_SUP_3P3

SPRW_SUP_2P5

SPRW_SUP_1P8

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

J27A

ASP-134486-01

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

J27B

ASP-134486-01

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

J27C

ASP-134486-01

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

J27D

ASP-134486-01

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E40

J27E

ASP-134486-01

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F40

J27F

ASP-134486-01

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

G31

G32

G33

G34

G35

G36

G37

G38

G39

G40

J27G

ASP-134486-01

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

H31

H32

H33

H34

H35

H36

H37

H38

H39

H40

J27H

ASP-134486-01

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J31

J32

J33

J34

J35

J36

J37

J38

J39

J40

J27I

ASP-134486-01

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K40

J27J

ASP-134486-01

SMPL_CLK

SMPL_SYNC

GND GND GND GND GND

GNDGNDGNDGNDGND

Figure 6-3. Digital Connector

Bill of Materials, Schematics, and Layout www.ti.com

20 ADS9817EVM-PDK Evaluation Module SBAU416 – NOVEMBER 2022

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