Texas Instruments ADS1285EVM-PDK User manual

User’s Guide
ADS1285EVM-PDK Evaluation Module
Cole Macias
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS1285EVM-PDK. This evaluation
module (EVM) is an evaluation board for the ADS1285, a high-performance, 32-bit, multichannel, delta-sigma
(ΔΣ) analog-to-digital converter (ADC). The EVM allows evaluation of all aspects of the ADS1285. This
manual covers the operation of the ADS1285EVM-PDK. Throughout this document, the terms evaluation board,
evaluation module, and EVM are synonymous with the ADS1285EVM-PDK. Complete circuit descriptions,
schematic diagrams, and bills of material are included in this document.
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Table of Contents
1 EVM Overview......................................................................................................................................................................... 4
1.1 ADS1285EVM-PDK Kit...................................................................................................................................................... 4
2 ADS1285EVM-PDK Quick-Start Guide.................................................................................................................................. 4
3 EVM Analog Interface.............................................................................................................................................................6
3.1 ADC Analog Input Signal Path........................................................................................................................................... 6
3.2 ADC Input Clock (CLK) Options.........................................................................................................................................8
4 Digital Interface.......................................................................................................................................................................9
4.1 Connection to the PHI........................................................................................................................................................ 9
4.2 Digital Header.................................................................................................................................................................. 10
5 Power Supplies..................................................................................................................................................................... 10
6 Digital-to-Analog Converter.................................................................................................................................................12
7 ADS1285EVM-PDK Initial Setup.......................................................................................................................................... 13
7.1 Default Jumper Settings...................................................................................................................................................13
7.2 EVM Graphical User Interface (GUI) Software Installation.............................................................................................. 14
8 ADS1285EVM-PDK Software Reference............................................................................................................................. 16
8.1 EVM GUI Global Settings for ADC Control...................................................................................................................... 16
8.2 Register Map Configuration Tool......................................................................................................................................17
8.3 Time Domain Display Tool................................................................................................................................................18
8.4 Spectral Analysis Tool...................................................................................................................................................... 19
8.5 Histogram Tool................................................................................................................................................................. 20
8.6 DAC Configuration Tool....................................................................................................................................................20
9 ADS1285EVM-PDK Bill of Materials, PCB Layout, and Schematics................................................................................ 22
9.1 Bill of Materials.................................................................................................................................................................22
9.2 PCB Layout...................................................................................................................................................................... 27
9.3 Schematics.......................................................................................................................................................................28
10 References.......................................................................................................................................................................... 34
11 Revision History..................................................................................................................................................................34
List of Figures
Figure 2-1. ADS1285EVM-PDK Hardware Setup and LED Indicators........................................................................................ 4
Figure 2-2. EVM GUI Global Input Parameters........................................................................................................................... 5
Figure 3-1. Input Terminal Blocks and Headers (Schematic)...................................................................................................... 7
Figure 3-2. CLK Source (Schematic)...........................................................................................................................................8
Figure 5-1. ADS1285EVM-PDK AVDD1, AVDD2, and AVSS+5V Supply Generation (Schematic).......................................... 10
Figure 5-2. ADS1285EVM-PDK Unipolar and Bidirectional Supplies Selection (Schematic).................................................... 11
Figure 5-3. Voltage Reference (Schematic)...............................................................................................................................12
Figure 7-1. ADS1285EVM-PDK Jumper Default Settings......................................................................................................... 13
Figure 7-2. ADS1285 Software Installation Prompt................................................................................................................... 14
Figure 7-3. Device Driver Installation Wizard Prompts.............................................................................................................. 15
Figure 7-4. LabVIEW Run-Time Engine Installation.................................................................................................................. 15
Figure 8-1. EVM GUI Global Input Parameters......................................................................................................................... 16
Figure 8-2. Register Map Configuration.....................................................................................................................................17
Figure 8-3. Time Domain Display Tool Options......................................................................................................................... 18
Figure 8-4. Spectral Analysis Tool............................................................................................................................................. 19
Figure 8-5. Histogram Analysis Tool.......................................................................................................................................... 20
Figure 8-6. DAC Configuration Tool Page................................................................................................................................. 21
Figure 9-1. Top Silkscreen......................................................................................................................................................... 27
Figure 9-2. Top Layer.................................................................................................................................................................27
Figure 9-3. Ground Layer 1....................................................................................................................................................... 27
Figure 9-4. Power Layer............................................................................................................................................................ 27
Figure 9-5. Bottom Layer........................................................................................................................................................... 27
Figure 9-6. Bottom Silkscreen................................................................................................................................................... 27
Figure 9-7. ADS1285EVM-PDK Block Diagram........................................................................................................................ 28
Figure 9-8. ADS1285EVM-PDK ADC Schematic...................................................................................................................... 29
Figure 9-9. ADS1285EVM-PDK Analog Inputs and Common-Mode Buffer Schematic.............................................................30
Figure 9-10. ADS1285EVM-PDK Clock and Interface Schematic.............................................................................................31
Figure 9-11. ADS1285EVM-PDK Power-Supply Schematic......................................................................................................32
Figure 9-12. ADS1285EVM-PDK Reference Voltage Schematic.............................................................................................. 33
Figure 9-13. ADS1285EVM DAC Schematic.............................................................................................................................33
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List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 4
Table 3-1. Analog Input Terminal Blocks (J12, J13).....................................................................................................................7
Table 4-1. PHI Connector Pin Functions......................................................................................................................................9
Table 4-2. Digital Header Pins................................................................................................................................................... 10
Table 5-1. Programmable LDO Configurations.......................................................................................................................... 11
Table 7-1. Default Shunt Settings.............................................................................................................................................. 13
Table 7-2. Nominal Voltages Resulting From a Default Configuration.......................................................................................14
Table 9-1. ADS1285EVM-PDK BOM......................................................................................................................................... 22
Trademarks
LabVIEW® is a registered trademark of National Instruments.
All trademarks are the property of their respective owners.
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1 EVM Overview
The evaluation kit includes the ADS1285EVM-PDK board and the precision host interface (PHI) controller
board. The PHI board enables the accompanying computer software to communicate with the ADC over the
universal serial bus (USB) for data capture and analysis because the ADS1285EVM-PDK does not contains a
microprocessor on the board.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS1285EVM-PDK
• Supplies power to all active circuitry on the ADS1285EVM-PDK board
The following related documents are available for download through the Texas Instruments web site at
www.ti.com.
Table 1-1. Related Documentation
Device Literature Number
ADS1285 SBASAK6
1.1 ADS1285EVM-PDK Kit
The ADS1285 evaluation module kit includes the following features:
• Contains all support circuitry needed for the ADS1285
• USB powered: No external power supply is required
• Voltage reference options: External or onboard
• Clock options: External clock source or 8.192-MHz onboard crystal oscillator with dividers for 4.096-MHz
• Voltage supply options: Unipolar or bipolar support with adjustable AVDD1 low-dropout regulator (LDO) and
externally sourced –2.5-V LDO
• Signals contained within signal bank for ease of probing
• Built-in analysis tools including scope, FFT, histogram, and DAC configuration using the graphical user
interface (GUI)
2 ADS1285EVM-PDK Quick-Start Guide
The following instructions are a step-by-step guide to connecting the ADS1285EVM-PDK to the computer and
evaluating the performance of the ADS1285:
1. Review the default jumper settings in Section 7 and GUI software installation in Section 7.2.
2. Connect the ADS1285EVM-PDK to the PHI. Install the two screws as indicated in Figure 2-1.
3. Attach the micro USB to the PHI board and your PC. Three LEDs illuminate on the PHI board to indicate
connectivity to the PC.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with
the PC. Figure 2-1 shows the resulting LED indicators.
Figure 2-1. ADS1285EVM-PDK Hardware Setup and LED Indicators
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4. Launch the ADS1285EVM-PDK GUI software and power will be supplied to the EVM.
a. The default installation path is C:\Program Files (x86)\Texas Instruments\ADS1285 EVM.
5. As shown in Figure 2-2, use the Configuration section of the GUI for a specific clock input, desired data
rate, and number of samples. Then, use the Capture button to collect data. Section 8.1 details the EVM GUI
global input parameters and the various pages within the GUI.
Figure 2-2. EVM GUI Global Input Parameters
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3 EVM Analog Interface
The ADS1285EVM-PDK is designed for easy interfacing with analog sources. This section details the front-end
circuit, including jumper configuration for different input test signals and board connectors for signal sources.
3.1 ADC Analog Input Signal Path
Analog inputs to the EVM can be connected to either terminal block associated with each ADC channel. The
screw terminal blocks (J12, and J13) can interface directly with the leads of an external sensor input. Figure
3-1 depicts the signal chain used for the two input channels on the EVM and Table 3-1 lists the supported input
options.
An input must not be applied such that the voltage on the input pins of the ADS1285 exceeds the absolute
maximum ratings. For more details, see the ADS1285 data sheet.
R45 and R46 provide common-mode voltage paths for the channel 1 inputs. See Section 5 for more information.
In addition, R43 and C29 (in combination with R47 and C31) provide the common-mode, low-pass filters for
the positive and negative inputs, respectively. Furthermore, R44 and R40 in combination with C30 provides the
differential low-pass filter used in antialiasing. The series impedance is kept relatively low to maintain adequate
total harmonic distortion (THD) performance. Similar differential and common-mode, low-pass filter footprints are
present on all inputs.
Specifically for channel 2, the default configuration is set up to use the DAC1282 on the input. As a result,
the common-mode filters for this configuration are not populated, and R50, R54, and C33 are optimized for
the output of the DAC. There are two options for connecting the DAC to the channel 2 of the ADS1285: using
the direct output of the DAC1282 or the integrated switches of the DAC1282. By default, the direct output of
the DAC1282 is used by populating R55 and R59. As a result, using the integrated switches is achieved by
depopulating R55 and R59, populating R56 and R58, and configuring the DAC using the GUI as described in
Section 6. For best THD performance (approximately a 1-dB difference), use the direct output. For maximum
flexibility, use the integrated switches.
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Analog inputs
DAC_SWOUTP
DAC_SWOUTN
Connects to 'DC127_DAC' page
This input is reserved
for the DAC1282
+VINP1
-VINN1
+VINP2
-VINN2
GND
VOCM
+VINP1
-VINN1
Vocm
Vocm
Connects to 'DC127_ADC' page
AIN1P
AIN1N
AIN2P
AIN2N
Connects to 'DC127_ADC' page
+VINP2
-VINN2
GND
Vocm
C0G/NP0
1000pF
C29
C0G/NP0
1000pF
C31
C0G/NP0
1000pF
C32
C0G/NP0
1000pF
C34
1
2
J14
0
R56
0
R58
22.6k
R45
22.6k
R46
22.6k
R51
22.6k
R52
1
2
3
J12
GND
1
2
3
J13
GND
NP0
1nF
C30
NP0
1nF
C33
20
R50
20
R54
0
R55
0
R59
VOUTN_SWINN
VOUTP_SWINP
20
R48
20
R47
20
R43
20
R44
20
R49
20
R53
Place differential RC filter
stages close to ADC input pins
Recommended input protection:
TPD4E1B06DCKR
Figure 3-1. Input Terminal Blocks and Headers (Schematic)
Table 3-1. Analog Input Terminal Blocks (J12, J13)
Terminal Block Pin Function ADS1285 Input Pin(s)
J12
1 Channel 1 positive input +VINP1
(Eventually leading to AIN1P)
2 GND AGND and DGND
3 Channel 1 negative input –VINN1
(Eventually leading to AIN1N)
J13
1 Channel 2 positive input +VINP2
(Eventually leading to AIN2P)
2 GND AGND and DGND
3 Channel 2 negative input –VINN2
(Eventually leading to AIN2N)
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3.2 ADC Input Clock (CLK) Options
Using the onboard oscillator, clock dividers, and external connectors, the ADS1285EVM-PDK has device
configuration flexibility. The ADC operates from CLK, which generates the modulator clock (fMOD), provided
in one of two ways:
• A crystal oscillator and the accompanying clock dividers can provide a selectable frequency for the entire
range of the ADC.
– The onboard crystal oscillator (Y1) provides the nominal 8.192-MHz clock frequency (default)
– The dividers (U6) step down the frequency to 4.096 MHz
– J8 allows the user to select between these frequencies and connect them directly to CLK by using a shunt
• An external main clock can be provided to a subminiature version A (SMA) connector (J5) or to pins 4 or 2 of
J7 when a shunt does not select the frequency from the crystal oscillator.
– In this case, a shunt must not cover J7 so that CLK is connected to any of the crystal oscillator signals
– Be sure to review the valid CLKIN input frequency in the data sheet
Note
All clock sources are sourced back to the PHI connector (J6) so that the GUI SCLK communication is
synchronous with CLK.
Figure 3-2 shows a schematic for the clock source.
1) FPGA provides CLK output
2) External oscillator drives CLK (default)
CLK Options:
Q4 D
1
CLK
2
GND 3 VCC
5
U6
SN74AUP1G80DCKT
GND
GND
1
2
J8
GND
GND
DVDD
On-board clock
GND
Connect jumper across to
select ADC clock frequency.
DNI if using FPGA clock.
Supply range: 1.71V - 3.63V
8 MHz
4 MHz
1
2
3
4
5
J5
GND
External clock
DAC_4MHZ
Gnd 2
Output 3
Tri-state
1
Vdd
4
Y1
ECS-2520MVLC-081.92-BN-TR
DVDD
0
R31
0.1uF
C21
0.1uF
C23
100k
R30
49.9
R29
1 2
3 4
J7
CLK DIS
Figure 3-2. CLK Source (Schematic)
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4 Digital Interface
As noted in Section 1, the EVM interfaces with the PHI and communicates with the computer over the USB.
There are two devices on the EVM with which the PHI communicates: the ADS1285 ADC (over SPI) and the
EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to configure and
initialize the ADS1285EVM-PDK GUI. When the hardware is initialized, the EEPROM is no longer used.
4.1 Connection to the PHI
The ADS1285EVM-PDK board communicates with the PHI through a shrouded, 60-pin connector, J6. There are
two round standoffs next to J6 with Phillips-head screws. To connect the PHI to the EVM, remove the screws,
attach the PHI to the EVM, and replace the screws into the standoffs. The screws secure the EVM to the PHI
and ensures the connection between the boards.
Table 4-1 lists the different PHI connection and their functions.
Table 4-1. PHI Connector Pin Functions
PHI Connector Pin Name PHI Connector Pin Function
5.5V J6[1] Power-supply source for the analog section of the EVM
GND J6[3] Ground
~RESET J6[6] ADC reset pin, active low
~PWDN J6[8] ADC power-down pin, active low
SYNC J6[12] ADC synchronization, active high
DIN_PHI J6[12] SPI: DIN from the ADC, POCI, or serial interface data in (pre-RTM
GUI revision compatibility)
GPIO1 J6[14] General-purpose I/O 1 pin from the ADC
GPIO0 J6[16] General-purpose I/O 0 pin from the ADC
DIN_PHI J6[18] SPI: DIN from the ADC, POCI, or serial interface data in (RTM GUI
revision compatibility)
~CS_ADC J6[22] SPI: CS, chip-select, or serial interface select, active low for the ADC
SCLK_PHI J6[24] SPI: Serial interface clock, or SCLK
CAPCLK_OUT J6[26] Output path for the PHI signal to synchronize captures with any delay
from the EVM
CAPCLK_IN J6[28] Input path for the PHI signal to synchronize captures with any delay
from the EVM
~DRDY J6[30] SPI: Data-ready signal for the ADS1285; active-low DRDY
ADC_CLK (input) J6[32] Input for the PHI to sense CLK
ADC_CLK (output) J6[34] Possible output for the PHI to provide CLK (not supported on the
ADS1285EVM-PDK)
DOUT J6[38] SPI: Serial data output for the ADS1285, or PICO
~RST/PWDN_DAC J6[46] Reset or power-down input pin for the DAC1282
SYNC_DAC J6[48] Synchronize input pin for the DAC1282
WP J6[49] Write protection for the EEPROM
DVDD J6[50] Power-supply source for the digital section of the EVM
SW/TD_DAC J6[52] Switch control input or bitstream input pin for the DAC1282
~CS_DAC J6[54] SPI: Serial port chip select, or CS, for the DAC1282
SDA J6[56] I2C serial data for the EEPROM used to identify the EVM
SCL J6[58] I2C serial clock for the EEPROM used to identify the EVM
ID_PWR J6[59] Power-supply source for the EEPROM used to identify the EVM
GND J6[60] Ground
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4.2 Digital Header
In addition to the PHI, the EVM has a header connected to the digital lines that can be used to connect a
logic analyzer or oscilloscope. This placement allows for easy access to the digital communications. Header J9
is connected to the digital lines between the ADS1285 and the PHI connector. Table 4-2 describes the digital
header pins.
Table 4-2. Digital Header Pins
Signal Name Digital Header Pin
~RESET J9[1]
~PWDN J9[3]
SYNC J9[5]
DIN_PHI J9[7]
GPIO1 J9[9]
GPIO0 J9[11]
~CS_ADC J9[13]
SCLK_PHI J9[15]
~DRDY J9[17]
ADC_CLK J9[19]
DOUT J9[21]
~RST/PWDN_DAC J9[23]
SYNC_DAC J9[25]
SW/TD_DAC J9[27]
~CS_DAC J9[29]
5 Power Supplies
The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the computer that
is routed to the 5.5-V net on the ADS1285EVM-PDK on the board.
The EEPROM on the ADS1285EVM-PDK uses a 3.3-V power supply, ID_PWR, generated directly by the PHI.
The 3.3-V supply to the digital section of the ADC (3V3_IOVDD) is provided directly by a separate LDO on the
PHI.
Figure 5-1 and Table 5-1 describe the supply generation and programmable configurations, respectively.
AVDD2
1µF
C15
5.5V
GND
GND
GND
AVDD1 supply for ADS1285
AVDD2 supply for ADS1285
AVDD supply for DAC1282
AVDD2 is referenced to the ADC's AGND
10uF
C11
GND
AVDD1
1µF
C13
5.5V
10uF
C9
AVSS
AVSS
AVSS
AVSS AVSS+5V
1µF
C16
5.5V
10uF
C14
AVSS
AVSS
AVSS
AVSS
Do NOT modify!
The DAC1282 requires a 5V analog supply
Default: 5V
Default: 3V
10uF
C8
10uF
C10
10uF
C12
NOTE: If you configure AVDD1 for 3.3V, replace REF6241 with a REF6225!
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4701QRGWRQ1
U2
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4701QRGWRQ1
U3
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4701QRGWRQ1
U4
0
R8
0
R9
0
R10
0
R11
0
R12
0
R13
0
R14
0
R15
0
R16
0
R17
0
R18
0
R19
0
R20
0
R21
0
R22
0
R23
0
R24
0
R25
13
NC 2
D1
PLVA653A,215
TP1
AVSS+5V
Figure 5-1. ADS1285EVM-PDK AVDD1, AVDD2, and AVSS+5V Supply Generation (Schematic)
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Table 5-1. Programmable LDO Configurations
VOUT (V)(2) 3P2V 1P6V 0P8V 0P4V 0P2V 0P1V
2.5 — — Installed(1) — Installed Installed
3.0 — Installed — — — —
3.3 — Installed — — Installed Installed
4.5 — Installed Installed Installed Installed Installed
5.0 Installed — — Installed — —
(1) Installed = Solder a 0-Ω jumper to GND/AVSS.
(2) VOUT = 1.4 V + Σ (all grounded pins).
The PGA positive analog supply of the ADC, AVDD1, is powered by the TPS7A4701 or TPS7A4700 (U2)
onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a
cleaner 5-V output. The TPS47A470x is a configurable LDO so R8 to R13 can be used to change the voltage.
AVDD2 is the modulator analog supply that is also used by the ADC. As with AVDD1, AVDD2 is generated by
the TPS7A470x (U3) onboard the EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the
PHI to generate a cleaner 5-V output. The TPS7A470x is a configurable LDO so R14 to R19 can be used to
change the voltage but a lower AVDD2 will result in lower THD performance in unipolar mode.
AVSS+5V is used for the analog supply of the DAC1282. This pin also uses a TPS7A470x (U4) onboard the
EVM, which is a low-noise linear regulator that uses the 5.5-V supply on the PHI to generate a cleaner 5-V
output. The DAC1282 requires a 5-V supply so R20 to R25 must not be modified.
The user has the option to configure the EVM for unipolar supplies (AVSS = 0 V) by placing a jumper to cover
pins 1 and 2 of J4 (UNIPOL), or to configure the EVM for bidirectional supplies (AVSS = –2.5 V) by placing the
jumper to cover pins 2 and 3 of J4 (BIPOL). The TPS7A3001 (U5) is an LDO with a VIN range from –3 V to –36
V that provides a clean –2.5-V output for the AVSS voltage. However, an external voltage is needed to supply
the AVSS voltage, which can be supplied using J3. Because AVDD1 is referenced to AVSS, the output AVDD1
must be modified using R8 to R13 so that the AVDD1 to AVSS voltage does not go above the recommended
operating conditions. Figure 5-2 shows the supply selection and –2.5-V generation circuit.
GND
GND
AVSS
-2.5V
BIPOLUNIPOL
TPS7A3001DRBR
OUT 1
FB 2
NC
3GND 4
EN
5
NR/SS
6
DNC
7
IN
8
PAD 9
U5 -2.5V
GND
11.3k
R27
10.0k
R28
GND
10uF
C17
GND 10uF
C19
GND
1
2
3
J4
AVSS supply
Header for connecting an
external negative supply
source, when configuring
AVSS to -2.5V
1
2
J3
Header to select AVSS potential
(UNIPOL = GND, BIPOL = -2.5V)
GND
-IN
-2.5V
-IN
GND
AVSS
10nF
C18
10nF
C20
0
R26
Figure 5-2. ADS1285EVM-PDK Unipolar and Bidirectional Supplies Selection (Schematic)
AVDD1 is used as the supply for the REF6241, which is a high-precision voltage reference with an integrated
high-bandwidth buffer in reference to AVSS. The voltage reference can be used to supply the positive reference,
VREFP, for the ADC and DAC using R38 as a pass transistor. Alternatively, R38 and R42 can be depopulated so
the positive and negative reference externally using pins 1 and 2 of J10, respectively.
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Figure 5-3 shows a schematic of the voltage reference.
1µF
C28
1µF
C25
AVSS
AVSS
AVSS
NOTE: This reference voltage is shared between
the ADS1285 and DAC1282
On-board references
Route REFP/REFN as differential
pair, and only connect REFN to
AVSS near the reference source(s).
AVSS
VREFP
VREFN
Header for measuring reference voltage or
connecting to an external reference source
AVSS
+ -
10.0k
R41
1
2
J11
Connects to 'DC127_ADC' and 'DC127_DAC' pages
REF6250 supply range: 5.3 - 5.5V
REF6241 supply range: 4.35 - 5.5V
REF6225 supply range: 3 - 5.5V
0.22
R39
0.01uF
C26
0.22
R37
VIN
1
EN
2
SS
3
FILT
4
OUT_S 5
OUT_F 6
GND_F 7
GND_S 8
REF6241IDGKR
U8
REF62xx EN
AVDD1
Reference options
22µF
C27
0
R38
0
R42
130k
R40
1
2
J10
Figure 5-3. Voltage Reference (Schematic)
The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed close
to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where possible,
between bypass capacitors and their loads to minimize inductance along the load current path.
As mentioned previously in Section 1, power to the EVM is supplied by the PHI through connector J5. For
information about PHI pins and the power connections, see Table 4-1.
With modifications, the user can use external supplies for any voltage supplies. Using the ADC PWR header
(J26), DAC PWR header (J1), and the unipolar or bipolar select (J4); the shunts can be depopulated for direct
access to the AVDD1, AVDD2, AVSS+5V, DVDD, and AVSS pins.
6 Digital-to-Analog Converter
The ADS1282EVM-PDK contains a DAC1282, which is a fully integrated digital-to-analog converter (DAC) that
provides a low-distortion, digital-synthesized voltage output designed for testing seismic equipment and the
ADS128x family of devices; see the DAC1282 data sheet for more information. The DAC1282 can be used in
combination with the GUI to directly supply an input voltage for testing and performance purposes. For more
information on configuring the inputs to use the DAC1282, see Section 3.1.
If using the DAC in Sine mode, the output frequency is programmable from 0.5 Hz to 250 Hz and the magnitude
is scaled by both analog and digital control. The analog gain is adjustable in 6-dB steps and the digital gain in
0.5-dB steps. The analog gain settings match those of the ADS1282 for testing at all gains with high resolution.
Controlling the settings of the DAC1282 can be done on the DAC Configuration page of the GUI as explained in
Section 8.6.
The DAC1282 uses AVSS+5V and DVDD for the power supplies and shares the same reference as the
ADS1285. This configuration minimizes potential errors from using separate references between the devices.
However, most of the DAC1282 documentation is in reference to a 5-V supply where the ADS1285EVM-PDK
uses a 4.096-V reference by default. As a result, the DAC output amplitude is scaled in reference to the 4.096-V
reference through the following equation:
Vout_peak =VFSR_peak ∙10
GDAC_Dig dB
20 (1)
where:
• Vout_peak = Output amplitude of the DAC in Sine mode
• VFSR_peak = Positive peak of the full-scale range calculation, which depends on voltage reference
• GDAC_Dig(dB) = Digital gain of the DAC determined by the SINEG register
This equation and scaling is automatically calculated in the ADS1285EVM-PDK GUI; see Section 8.6.
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7 ADS1285EVM-PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for properly
operating the ADS1285EVM-PDK.
7.1 Default Jumper Settings
After unpacking, the EVM is already configured with the default jumper settings. Figure 7-1 shows the locations
for the default jumpers and Table 7-1 shows the functions of the default shunts.
Figure 7-1. ADS1285EVM-PDK Jumper Default Settings
Table 7-1. Default Shunt Settings
Header Designator Position Function
J11 [1-2] Enables the REF62x supply to VREFP
J4 [1-2] Connects AVSS to GND for unipolar ADC supply mode
J7 [3-4] Connects CLK to an 8.192-MHz source from the crystal oscillator
J10 Not installed Header to supply the external reference voltage to VREFN and VREFP
J1 [1-2] DAC PWR: Connects the output of the U4 LDO (AVSS+5V) to the DAC analog supply
pin (AVDD)
J1 [3-4] DAC PWR: Connects the PHI digital supply (DVDD) to the DAC digital supply pin
(DVDD)
J15 [1-2] ADC PWR: Connects the output of the U2 LDO (AVDD1) to the ADC analog supply 1
(AVDD1)
J15 [3-4] ADC PWR: Connects the output of the U3 LDO (AVDD2) to the ADC analog supply 2
(AVDD2)
J15 [5-6] ADC PWR: Connects the PHI digital supply (DVDD) to the ADC digital supply (IOVDD)
J3 Not installed Header to supply the external input to U5 for the –2.5-V supply
J8 Not Installed Enables 8.192-MHz crystal oscillator
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Table 7-2 lists the nominal voltages that result from the default configuration.
Table 7-2. Nominal Voltages Resulting From a Default Configuration
Supply Name Voltage (Referenced to GND)
AVSS GND (0 V)
AVSS+5V 5 V
DVDD (IOVDD) 3.3 V
AVDD1 5 V
AVDD2 5 V
5.5V 5.5 V
REFP 4.096 V
–2.5V NA, external supply needed to generate –2.5 V
7.2 EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the ADS1285EVM-
PDK and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Depending on the antivirus settings, an error message may appear
or the installer. The .exe file can be deleted.
Accept the license agreements and follow the on-screen instructions shown in Figure 7-2 to complete the
installation.
Figure 7-2. ADS1285 Software Installation Prompt
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As part of the ADS1285EVM-PDK GUI installation, a prompt with a device driver installation (as shown in Figure
7-3) appears on the screen. Click Next to proceed.
Figure 7-3. Device Driver Installation Wizard Prompts
Note
A notice may appear on the screen stating that Windows cannot verify the publisher of this driver
software. Select Install this driver software anyway.
The ADS1285EVM-PDK requires the LabVIEW® run-time engine and may prompt for the installation of this
software, as shown in Figure 7-4, if not already installed.
Figure 7-4. LabVIEW Run-Time Engine Installation
Verify that C:\Program Files (x86)\Texas Instruments\ADS1285EVM-PDK is available after these installations.
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8 ADS1285EVM-PDK Software Reference
8.1 EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC digital
interface, the EVM GUI does give users high-level control over many other functions of the ADS1285, including:
internal clock dividers, oversampling ratio (OSR), and number of samples to be captured. Figure 8-1 identifies
the input parameters of the GUI (as well as their default values) through which the various functions of the
ADS1285 can be exercised.
Figure 8-1. EVM GUI Global Input Parameters
There are four pages available in the ADS1285EVM-PDK GUI. The information area displays the results of each
of the pages. Each of these pages display a different control or measurement of the device. The Register Map
Config page reads and writes the registers of the device. The Time Domain Display page collects a set of data
from the device and displays the result. The Spectral Analysis page can compute the FFT of the collected data,
and the Histogram Analysis page shows a histogram of the collected data and displays basic statistics of the
result.
The Single Commands section allows for direct control of the device for three basic functions. First, the Reset
button sends a signal to the RESET pin to reset the device. The Standby button puts the device into a low-
power state where all channels are disabled, and the reference and other non-essential circuitry are powered
down. The Wakeup button exits standby mode.
The Interface Configuration section also sets the data rate by setting the internal clock dividers and OSR
in the ADC. Finally, this section can set the power modes in the registers. The ADS1285 has three power
modes (low-power, mid-power, and high-power) that are configured in the CONFIG0 register (bits 7-6). This
configuration is used in conjunction with the jumper settings of JP8 for the CLK pin, as outlined in Section 3.2.
The Clock and Sampling Rate section allows the user to specify a target SCLK frequency (in Hz) and the
GUI tries to match this frequency as closely as possible by changing the PHI PLL settings, but the achievable
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frequency may differ from the target value entered. This section also displays the sampling rate of the ADC as
controlled by the internal clock dividers and the OSR.
The GUI is switched between hardware mode and simulation mode by checking and unchecking the Connected
to Hardware box in the top right area of the screen at any time.
8.2 Register Map Configuration Tool
The register map configuration tool allows the user to view and modify the registers of the ADS1285. This tool
can be selected, as indicated in Figure 8-2, by clicking on the Register Map Config radio button at the Pages
section of the left pane. On power-up, the values on this page correspond to the Host Configuration Settings that
enable ADC sampling at the maximum sampling rate specified for the ADC. The register values can be edited
by double-clicking the corresponding value field. If interface mode settings are affected by the change in register
values, this change reflects on the left pane immediately.
Figure 8-2. Register Map Configuration
Section 8.3 through Section 8.5 describe the data collection and analysis features of the ADS1285EVM-PDK
GUI.
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8.3 Time Domain Display Tool
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is useful
for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
The user can trigger a capture of the data of the selected number of samples from the ADS1285EVM-PDK,
as per the current interface mode settings indicated in Figure 8-3 by using the Capture button. The sample
indices are on the x-axis and there are two y-axes showing the corresponding output codes as well as the
equivalent analog voltages based on the specified reference voltage. Switching pages to any of the Analysis
tools described in the subsequent sections causes calculations to be performed on the same set of data.
Figure 8-3. Time Domain Display Tool Options
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8.4 Spectral Analysis Tool
The spectral analysis tool, shown in Figure 8-4, is intended to evaluate the dynamic performance (SNR, THD,
SFDR, SINAD, and ENOB) of the ADS1285 ADC through single-tone sinusoidal signal FFT analysis using the
7-term Blackman-Harris window setting.
Figure 8-4. Spectral Analysis Tool
The FFT tool includes windowing options that are required to mitigate the effects of non-coherent sampling (this
discussion is beyond the scope of this document). The 7-Term Blackman-Harris window is the default option
and has sufficient dynamic range to resolve the frequency components of up to a 24-bit ADC. The None option
corresponds to not using a window (or using a rectangular window) and is not recommended.
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8.5 Histogram Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which is an
indicator of the number of bits of ADC resolution losses resulting from noise generated by the various sources
connected to the ADC when measuring a DC signal. The cumulative effect of noise coupling to the ADC output
from sources such as the input drive circuits, the reference drive circuit, the ADC power supply, and the ADC
is reflected in the standard deviation of the ADC output code histogram that is obtained by performing multiple
conversions of a DC input applied to a given channel.
As shown in Figure 8-5, the histogram corresponding to a DC input is displayed on clicking the Capture button.
Figure 8-5. Histogram Analysis Tool
8.6 DAC Configuration Tool
The DAC configuration tool page (Figure 8-6) controls the onboard DAC1282, a test DAC specifically designed
to work with the ADS128x family of devices. As previously discussed in Section 6, the DAC output frequency is
programmable from 0.5 Hz to 250 Hz and the magnitude is scaled by both analog and digital control. The analog
gain is adjustable in 6-dB steps and the digital gain in 0.5-dB steps. The analog gain settings match those of the
ADS1282 for testing at all gains with high resolution. More information about each setting can be found in the
DAC1282 data sheet.
In general, the most important outcomes of changing the DAC are to understand the mode, output amplitude,
and output frequency (if applicable). In the middle, the Operation box shows the Mode drop-down, which can be:
Sine, DC, digital pulse, and pulse.
For Sine, the amplitude is determined by a combination of the analog gain and digital gain settings. In addition,
the DAC page uses the Vref (V) drop-down menu to calculate the values in the gray boxes, although the DAC
does not need to know the reference voltage to function. As a result, review the Sine AMP (Vp) calculation,
in combination with the ADC gain on the register map page, to understand the output code and voltage of the
ADC. The frequency is determined by typing a desired frequency into the Desired Frequency (Hz) text box. The
GUI automatically displays the closest Freq, M, and N values to achieve the desired output frequency that are
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