Texas Instruments bq2415x User manual

User's Guide
SLUU366A–March 2010–Revised April 2010
bq2415x RGY EVM (HPA255)
This user's guide describes the features, setup, and operation of the bq2415x RGY evaluation board.
Included are the bill of materials, board layout, and schematic.
Contents
1 Introduction .................................................................................................................. 2
1.1 EVM Features ...................................................................................................... 2
1.2 General Description ................................................................................................ 2
1.3 I/O Description ...................................................................................................... 2
1.4 Controls and Key Parameters Setting ........................................................................... 2
1.5 Recommended Operating Conditions ........................................................................... 3
2 Test Summary ............................................................................................................... 4
2.1 Definitions ........................................................................................................... 4
2.2 Equipment ........................................................................................................... 4
2.3 Equipment Setup ................................................................................................... 5
2.4 Procedure ........................................................................................................... 6
3 PCB Layout Guideline ...................................................................................................... 8
4 Board Layout, Schematic, and Bill of Materials ......................................................................... 9
4.1 Board Layout ....................................................................................................... 9
4.2 Schematic ......................................................................................................... 12
4.3 Bill of Materials .................................................................................................... 13
List of Figures
1 Connections of the HPA172 Kit........................................................................................... 5
2 Original Test Setup for HPA255 (bq2415x EVM)....................................................................... 5
3 Main Window of the bq2415x Evaluation Software..................................................................... 6
4 Test Setup for HPA255 .................................................................................................... 7
5 Top Layer .................................................................................................................... 9
6 Bottom Layer............................................................................................................... 10
7 Top Assembly.............................................................................................................. 10
8 Top Silk ..................................................................................................................... 11
List of Tables
1 Input/Output Jack Descriptions............................................................................................ 2
2 Control and Key Parameters Settings for JMP1 Through JMP5 ..................................................... 2
3 Factory Jumper Settings ................................................................................................... 3
4 Recommended Operating Conditions.................................................................................... 3
5 JMP1 Through JMP5 Installation Settings............................................................................... 5
I2C is a trademark of Koninklijke Philips Electronics NV.
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SLUU366A–March 2010–Revised April 2010 bq2415x RGY EVM (HPA255)
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Introduction www.ti.com
1 Introduction
1.1 EVM Features
• Evaluation module for bq2415x
• High-efficiency, fully integrated NMOS-NMOS synchronous buck charger with 3-MHz frequency
• Integrated power FETs for up to 1.25-A charge rate
• Programmable battery voltage, charge current, and input current via I2C™ interface
• Input operating range 4 V–6 V
• Boost mode operation for USB OTG
• LED indication for status signals
• Test points for key signals available for testing purposes. Easy probe hook-up.
• Jumpers available. Easy to change connections.
1.2 General Description
The bq2415x evaluation module is a complete charger module for evaluating compact, flexible,
high-efficiency, USB-friendly switch-mode charge management solution for single-cell Li-ion and
Li-polymer batteries used in a wide range of portable applications.
The bq2415x integrates a synchronous PWM controller, power MOSFETs, input current sensing,
high-accuracy current and voltage regulation, and charge termination, into a small WCSP package.
The charge parameters can be programmed through an I2C interface.
For details, see the bq2415x data sheet (SLUS942).
1.3 I/O Description
Table 1. Input/Output Jack Descriptions
Jack Description
J1–DC+ AC adapter or USB, positive output
J1–DC– AC adapter or USB, negative output
J2–BAT+ Charger positive output, connect to CSOUT pin
J2–AUXPWR/CD Connect to AUXPWR/CD pin
J2–BAT– Battery negative terminal, connect to DC-
J3–SCL I2C clock, connect to SCL pin
J3–SDA I2C data, connect to SDA pin
J3–DC– AC adapter or USB, negative output
J4–STAT Status output, can be connected to STAT pin by JMP1 set to EXT (2-3)
J4–OTG/SLRST/TS/ISEL Connect to OTG/SLRST/TS/ISEL pin
J4–DC– AC adapter or USB, negative output
1.4 Controls and Key Parameters Setting
Table 2. Control and Key Parameters Settings for JMP1 Through JMP5
Jack Description Factory Setting
JMP1 LED 1-2: Connect STAT pin to LED on EVM Jumper On LED (1-2)
EXT 2-3: Connect STAT pin to J4-1
JMP2 HI 1-2: OTG/SLRST/TS/ISEL high (input or battery voltage) See table below
LO 2-3: OTG/SLRST/TS/ISEL low (ground)
JMP3 J2-BAT+ connect to J2-AUXPWR/CD See table below
JMP4 AUXPWR/CD pin connect to high or low or float See table below
JMP5 OTG/SLRST/TS/ISEL pin 10k resistor to ground or float Jumper On
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www.ti.com Introduction
Table 3. Factory Jumper Settings
Spin JMP1 JMP2 JMP3 JMP4 JMP5
HPA255-001 (bq24150) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-002 (bq24151) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-003 (bq24152) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-004 (bq24153) (-LED-) ON (-LO-) ON OFF (-LO-) ON ON
HPA255-005 (bq24155) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-006 (bq24156) (-LED-) ON (-HI-) ON OFF (-LO-) ON ON
HPA255-007 (bq24159) (-LED-) ON OFF OFF (-LO-) ON ON
1.5 Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Min Typ Max Unit Notes
Supply voltage, VIN Input voltage from ac adapter input 4 5 6 V
Battery voltage, VBAT Voltage applied at VBAT terminal of J8 0 3–4.2 4.44 V
Supply current, IAC Maximum input current from ac adapter 0 0.1–0.5 1.5 A
input
Charge current, Ichrg Battery charge current 0.55 0.7 1.25 A
Operating junction temperature range, TJ0 125 °C
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Test Summary www.ti.com
2 Test Summary
2.1 Definitions
This procedure details how to configure the HPA255 evaluation board. On the test procedure the following
naming conventions are followed. Refer to the HPA255 schematic for details.
VXXX : External voltage supply name (VADP, VBT, VSBT)
LOADW : External load name (LOADR, LOADI)
V(TPyyy) : Voltage at internal test point TPyyy. For example, V(TP12) means the voltage at
TP12.
V(Jxx) : Voltage at jack terminal Jxx.
V(TP(XXX)) : Voltage at test point “XXX”. For example, V(ACDET) means the voltage at the test
point which is marked as “ACDET”.
V(XXX, YYY) : Voltage across point XXX and YYY.
I(JXX(YYY)) : Current going out from the YYY terminal of jack XX.
Jxx(BBB) : Terminal or pin BBB of jack xx
Jxx ON : Internal jumper Jxx terminals are shorted
Jxx OFF : Internal jumper Jxx terminals are open
Jxx (-YY-) ON : Internal jumper Jxx adjacent terminals marked as “YY” are shorted
Measure: →A,B Check specified parameters A, B. If measured values are not within specified limits
the unit under test has failed.
Observe →A,B Observe if A, B occur. If they do not occur, the unit under test has failed.
Assembly drawings have location for jumpers, test points and individual components
2.2 Equipment
2.2.1 POWER SUPPLIES
Power Supply 1 (PS1): a power supply capable of supplying 5 V at 2 A is required.
2.2.2 LOAD 1
A 10-V (or above), 2-A (or above) electronic load that can operate at constant current mode.
2.2.3 LOAD 2
A HP 6060B 3-60V/0-60A, 300-W system dc electronic load.
Or: equivalent.
2.2.4 METERS
Four Fluke 75, (equivalent or better)
Or: Two equivalent voltage meters and two equivalent current meters. The current meters must be able to
measure a 2-A current.
2.2.5 COMPUTER
A computer with at least one USB port and a USB cable. The bq2415x evaluation software must be
properly installed.
2.2.6 HPA172 COMMUNICATION KIT
A HPA172 USB to I2C communication kit.
4bq2415x RGY EVM (HPA255) SLUU366A–March 2010–Revised April 2010
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To Computer
USB port
10-pin
Ribbon Cable
To EVM
U S B In te r fa c e
A d a p t e r
I/ O
U S B
T ex a s In s t ru m e n ts
©2006
bq24150/1/2/3/5/6/9 EVM
DC+
J 1
DC -
BAT+
S C L
BAT -
APPLICATION
CIRCUIT
U1
J3
J5
J4
J2
D1 JMP1 JMP2
JMP3
AUXPWR
CD
S D A
DC-
DC- S TA T O TG S L RS T T S IS E L
JMP5
JMP4
V
Iin I
Power
supply #1
V
Load
#2
Ichrg
USB
Cable HPA172 Ribbon Cable
I
www.ti.com Test Summary
2.2.7 SOFTWARE
Double click on the “SETUP.EXE” file. Follow the installation steps.
2.3 Equipment Setup
(A) Set the Power Supply 1 for 5 V ±100 mVdc, 2 ±0.1-A current limit and then turn off supply.
(B) Connect the output of Power Supply 1 in series with a current meter (multimeter) to J1 (DC+, DC–).
(C) Connect a voltage meter across J1 (DC+, DC-).
(D) Connect the Load 2 in series with a current meter (multimeter) to J2 (BAT+, BAT–). Make sure a
voltage meter is connected across J2 (BAT+, BAT–). Turn on the Load 2. Use the constant voltage
mode. Set the output voltage to 2.5 V.
(E) Turn off Load 2.
(F) Connect J5 to HPA172 kit by 10-pin ribbon cable. Connect the USB port of the HPA172 kit to the USB
port of the computer. The connections are shown in Figure 1.
Figure 1. Connections of the HPA172 Kit
(G) Install jumpers per following table.
Table 5. JMP1 Through JMP5 Installation Settings
Spin JMP1 JMP2 JMP3 JMP4 JMP5
HPA255-001 (bq24150) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-002 (bq24151) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-003 (bq24152) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-004 (bq24153) (-LED-) ON (-LO-) ON OFF (-LO-) ON ON
HPA255-005 (bq24155) (-LED-) ON (-LO-) ON ON OFF ON
HPA255-006 (bq24156) (-LED-) ON (-HI-) ON OFF (-LO-) ON ON
HPA255-007 (bq24159) (-LED-) ON OFF OFF (-LO-) ON ON
After completing the preceding steps, the test setup for HPA255 appears as is shown in Figure 2.
Figure 2. Original Test Setup for HPA255 (bq2415x EVM)
(H) Turn on the computer. Open the bq2415x evaluation software. The main window of the software is
shown in Figure 3.
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Figure 3. Main Window of the bq2415x Evaluation Software
2.4 Procedure
2.4.1 Charge Voltage and Current Regulation
1. Ensure that Section 2.3 steps are followed. Turn on PS1.
2. Software setup: Click Immediate Update Disabled button. It changes to Immediate Update Enabled.
Check Auto Reset Enable, set Rate to 5 seconds. Check Periodic Updates, set Rate to 1 second.
Ensure that Operation Mode is Charger Mode. Uncheck Charge Current Termination. Check STAT
Pin. Select Battery Regulation Voltage to 4.20V.
Measure →V(J2(VBAT+, VBAT–)) = 4.2 ±100 mV
Observe →D1 is on.
3. Enable Load 2.
Measure →V(J2(VBAT+, VBAT–)) = 2.5 ±100 mV
Measure →Ichrg = 160 mA ±40 mA
Measure →Iin = 93 mA ±5 mA
4. Select Charge Current to 1.25 A, select Input Current Limit to 500 mA.
Measure →Ichrg = 750 mA ±100 mA
Measure →Iin = 475 mA ±25 mA
5. Check Disable Charger. Turn off PS1, turn off Load 2, and disconnect
2.4.2 Boost Function (For –001, –002, –003, –004, –007 ONLY)
1. Adjust PS1 output to 3.7 V and disable the output. Connect the PS1 in series with a current meter
(multimeter) to J2 (BAT+, BAT-). Ensure that a voltage meter is connected across J2 (BAT+, BAT-).
2. Set the Load 1 current to 200 mA ±20 mA but disable the output. Connect the output of the Load 1 in
series with a current meter (multimeter) to J1 (DC+, DC-). Ensure that a voltage meter is connected
across J1 (DC+, DC-). The setup is now like that shown in Figure 4 for HPA255.
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bq24150/1/2/3/5/6/9 EVM
DC+
J 1
DC -
BAT+
S C L
BAT -
APPLICATION
CIRCUIT
U1
J3
J5
J4
J2
D1 JMP1 JMP2
JMP3
AUXPWR
CD
S D A
DC- DC-
S TA T
OTG S L RS T T S IS E L
JMP5
JMP4
V
I
Power
supply #1
Load
#1
Io
I
I in
USB
Cable HPA172 Ribbon Cable
V
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Figure 4. Test Setup for HPA255
3. Turn on PS1 output.
4. Software setup: Change Operation Mode to Boost Mode.
Measure →V(J1(DC+, DC–)) = 5 V ±0.2 V
5. Enable Load 1.
Measure →V(J1(DC+, DC-)) = 5 V ±0.2 V
Measure →Iin = 330 mA ±40 mA
Measure →Io = 200 mA ±20 mA
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PCB Layout Guideline www.ti.com
3 PCB Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from input to PGND, must be
placed as close as possible to the integrated circuit (IC).
2. The output inductor must be placed close to the IC and the output capacitor connected between the
inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin
through the LC filter and back to the PGND pin. To prevent high-frequency oscillation problems, proper
layout to minimize high-frequency current path loop is critical.
3. The sense resistor must be adjacent to the junction of the inductor and output capacitor. Route the
sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or
on top of each other on adjacent layers. (Do not route the sense leads through a high-current path.)
4. Place all decoupling capacitors close to their respective IC pin and as close as possible to PGND. (Do
not place components such that routing interrupts power stage currents.) All small control signals must
be routed away from the high-current paths.
5. The printed-circuit board must have a ground plane (return) connected directly to the return of all
components through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND,
one via per capacitor for small-signal components). A star ground design approach is typically used to
keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling
and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, no ground-bounce issue occurs, and having the components
segregated minimizes coupling between signals.
6. The high-current charge paths into VBUS, PMID, and from the SW pins must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND pins must be
connected to the ground plane to return current through the internal low-side FET.
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www.ti.com Board Layout, Schematic, and Bill of Materials
4 Board Layout, Schematic, and Bill of Materials
4.1 Board Layout
Figure 5. Top Layer
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Board Layout, Schematic, and Bill of Materials www.ti.com
Figure 6. Bottom Layer
Figure 7. Top Assembly
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