Texas Instruments LMK61E2EVM User manual

LMK61E2EVM
User's Guide
Literature Number: SNAU188
October 2015

Contents
1 Overview ............................................................................................................................ 5
2 Features ............................................................................................................................. 5
3 Configuring the EVM ............................................................................................................ 6
4 Configuring the Power Supply .............................................................................................. 6
5 Configuring the Control Pins................................................................................................. 8
6 Configuring the Clock Output .............................................................................................. 10
7 Using the USB Interface Connection..................................................................................... 11
8 EVM Quick Start Guide........................................................................................................ 11
9 Recommended Test Instruments.......................................................................................... 11
10 Example Performance Measurements................................................................................... 12
11 EVM Layout ....................................................................................................................... 15
12 EVM Schematic.................................................................................................................. 18
13 EVM Bill of Materials........................................................................................................... 21
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List of Figures
1 LMK61E2EVM Photo........................................................................................................ 4
2 LMK61E2EVM Board Layout............................................................................................... 6
3 Power Terminals and Jumpers............................................................................................. 7
4 Control Pin Interfaces (Default jumper settings shown) ............................................................... 8
5 LMK61E2EVM Termination Schematic.................................................................................. 10
6 156.25 MHz LVPECL Differential Phase Noise ........................................................................ 12
7 156.25 MHz LVDS Differential Phase Noise ........................................................................... 13
8 161.1328125 MHz HCSL Differential Phase Noise.................................................................... 14
9 Top Overlay................................................................................................................. 15
10 Top Solder Mask ........................................................................................................... 15
11 Layer 1 (Top Side) ......................................................................................................... 15
12 Layer 4 (Bottom Side, View From Bottom) ............................................................................. 16
13 Bottom Solder Mask ....................................................................................................... 16
14 Bottom Overlay ............................................................................................................. 16
15 Drill Drawing ................................................................................................................ 17
List of Tables
1 Ordering Information ........................................................................................................ 4
2 Power Configurations ....................................................................................................... 7
3 Control Pin Interfaces ....................................................................................................... 9
4 Output Termination Schemes............................................................................................. 10
5 Recommended Device Configurations .................................................................................. 11
6 Typical Output RMS Jitter Summary..................................................................................... 12
3
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User's Guide
SNAU188–October 2015
LMK61E2EVM User's Guide
Figure 1. LMK61E2EVM Photo
Table 1. Ordering Information
EVM ID DEVICE ID DEVICE PACKAGE
LMK61E2EVM LMK61E2-SIA 5 mm x 7 mm 8-pin QFM (SIA)
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www.ti.com Overview
1 Overview
The LMK61E2EVM evaluation module provides a complete evaluation platform to evaluate the clock
performance and flexibility of the Texas Instruments LMK61E2 Ultra-Low Jitter Crystal Oscillator, with
integrated tunable 50 MHz crystal, low noise PLL, differential output, and integrated EEPROM.
The LMK61E2EVM can be used as a flexible clock source for compliance testing, performance evaluation,
and initial system prototyping. The onboard edge-launch SMA ports provides access to the LMK61E2’s
configurable clock output for interfacing to test equipment and reference boards using commercially
available coaxial cables, adapters, or baluns (not included). This connectivity enables integrated system
level testing between TI’s LMK61E2 and third-party FPGA/ASIC/SoC reference boards. A software
graphical user interface (GUI) platform can be installed on a Host PC to access the LMK61E2’s device
registers and EEPROM via the on-board USB-to-I2C interface.
2 Features
• Integrated low noise 50 MHz tunable crystal
– Fine frequency margining in ppm steps via I2C
• Coarse frequency margining in percentage steps via I2C
• Configurable output format of either LVPECL, LVDS, or HCSL
• Programmable Output Enable polarity
• EEPROM allows for custom configuration for power up defaults
• Footprint compatible with industry standard 5 mm x 7 mm XO package
– 2 additional pins allow for optional I2C programing
• GUI platform for full access to device registers and EEPROM
• On-board USB-to-I2C programming interface
• External Power supply inputs or powered over USB
• LEDs indicators: Device Power and USB / I2C activity
• Configurable output format of either LVPECL, LVDS, or HCSL
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Configuring the EVM www.ti.com
3 Configuring the EVM
The LMK61E2 is a highly-configurable crystal oscillator with simple power supply requirements and
flexible clock output formats. To support a wide range of evaluation use cases, the EVM was designed for
maximum flexibility so various configurations options that are not required in all typical system applications
have been included.
This section describes the jumpers and connectors on the EVM, as well as how to connect, set-up, and
use the LMK61E2EVM. When operating the LMK61E2EVM, the power supply and clock outputs can be
connected to the SMA ports shown in Figure 2. Additionally, the USB port can be used to power the entire
LMK61E2EVM without the need for external power supplies. These SMA ports are labeled in the top
silkscreen layer.
Figure 2. LMK61E2EVM Board Layout
4 Configuring the Power Supply
The LMK61E2 features a single VDD supply pin that operates from 3.3V (+ 5%). This supply can be
powered directly from an external supply or through an on-board LDO regulator. Although the LMK61E2
has integrated LDO regulators for excellent power-supply-ripple-rejection (PSRR), the EVM’s on-board
regulator (U2) can allow a higher supply voltage (like 5 V) to power the EVM. The direct external supply or
on-board regulator can be independently routed for the VDD supply pin by configuring the power terminals
and jumpers shown in Figure 3. J1 (USB mini connector) is the default power supply for the EVM,
featuring a low noise regulator for voltage step down. Power SMA Port EXTIN (P1) provides an alternative
connector style to apply power using coax cables. Using EXTIN while connected to USB power is not
required but can be useful when testing with externally regulated supplies.
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www.ti.com Configuring the Power Supply
Figure 3. Power Terminals and Jumpers
Table 2 summarizes the EVM power configurations to connect and route power to the onboard LDOs and
LMK61E2. Refer to the EVM schematic for more details.
Table 2. Power Configurations
MODE EXTIN VOLTAGE J2 SETTING (1) J3 SETTING (1)
USB Powered (2) USB PWR
External Power + LDO 4.3 V to 5.5 V EXT PWR REG
External Power 3.3 V Remove Jumper EXT PWR
(1) Markings left of J2 indicate the orientation of jumper settings EXT PWR (pins 1 and 2 of jumper) and USB PWR / REG (pins 2
and 3 of jumper)
(2) USB cable must be connected to J1 for operation
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Configuring the Control Pins www.ti.com
5 Configuring the Control Pins
The LMK61E2 has several control pins dedicated for control of I2C communications, device I2C address,
and output enable control. These control pins can be configured through the jumpers shown in .
Figure 4. Control Pin Interfaces (Default jumper settings shown)
Jumpers J9 and J10 can be used to configure the corresponding control pin to either high or low state by
strapping the center pin to “VDD” position (tie pins 1-2) or “GND” position (tie pins 2-3), respectively.
Connections from the “VDD” position to the device supply or from the “GND” position to the ground plane
are connected by 4.7 kΩresistors.
Jumpers J5 and J6 can be configured in a static configuration through a high or low state by strapping the
center pin to “VDD” position or to the “GND” position. Similarly, these connections are made through a 4.7
kΩresistor to the respective supply and ground planes. The third position, “U2A”, allows for control of the
respective control pins over software via the onboard microcontroller. Biasing is established externally and
is default set to a high state.
The LMK61E2 control pins serve several functions unique to device pins. For a description of each pin’s
functionality and the device configuration based on their power up state, refer to Table 3.
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www.ti.com Configuring the Control Pins
Table 3. Control Pin Interfaces
COMPONENT NAME (TYPE) DESCRIPTION DESCRIPTION
J5 OE (passive or software control) Output Enable Pin Output Enable Pin
OE state controls the device output operation. Polarity can be
adjusted in the LMK61E2’s register settings.
OE STATE OPERATING MODE (based on
default)
GND Output Disabled
VDD (JP Default) Output Enabled
J6 ADD (passive or software I2C Slave Address LSB Select
control) pin
ADD is sampled on POR to configure the lower 2 bits of the 7-bit
slave address. The upper 5 bits of the slave address are initialized
from EEPROM (SLAVEADR[7:3] = 10110b). By configuring ADD, the
composite slave address can be selected as follows:
ADD STATE 7-BIT SLAVE ADDRESS
(excludes W/R bit)
GND 1011000b / 0x58
High Z (no connect) 1011001b / 0x59
VDD (JP Default) 1011011b / 0x5B
J9 J10 SCL SDA I2C Serial Interface Pins
(I2C inputs) An I2C master device can interface with the LMK61E2 over the I2C
clock line (SCL) and data line (SDA). The open drain topology of the
SCL and SDA pins require an external pull up resistor. J9 and J10
should always be set in the VDD position to ensure proper I2C
communication. The SCL and SDA lines are connected with the
onboard microcontroller, which is controlled by the GUI.
J1 USB (not shown in Figure 4) USB port (Mini-B type) USB port (Mini-B type)
Using the GUI platform, USB controller (U4) provides the USB-to-I2C
interface to manage the LMK61E2 device registers and EEPROM.
When USB communication is established with a Host PC running the
GUI, LED D5 should be lit solid green.
The USB port powers LDO regulator U1 to supply 3.3 V power for
the MCU and its peripheral circuitry.
J4 (not populated) U2A Optional Test Point Access to I2C and Control pins
Pin 1: SDA Pin 2: SCL
Pin 4: N/C Pin 3: N/C
Pin 5: GND Pin 6: N/C
Pin 7: OE Pin 8: ADD
Pin 9: N/C Pin 10: N/C
9
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OUT_P
0.1µF
C25
0.1µF
C24
0
R25
0
R28
OUT_N
R_OUT_P
R_OUT_N
1
2 3 4 5
P2
OUTP
1
2 3 4 5
P3
OUTN
0
R27
100
R31
0
R30
150
R26
150
R29
Configuring the Clock Output www.ti.com
6 Configuring the Clock Output
The LMK61E2’s differential output is routed via 50 ohm single ended traces to SMA ports (OUTN and
OUTP) through AC coupling capacitors. The output also has a series resistor (0 ohm populated by default,
R25 ad R28) and emitter resistors (150 ohm populated by default for LVPECL, R26 and R29). Common
output format terminations are shown in Table 4. The output termination schematic is shown in Figure 5.
Table 4. Output Termination Schemes
OUTPUT FORMAT COUPLING COMPONENT VALUE
LVPECL AC R25, R28 0 Ω
(default EVM R26, R29 150 Ω
configuration) C24, C25 0.01 uF
R27, R30, R31 DNP
DC(1) R25, R28, C24, C25 0 Ω
R26, R27, R29, R30, R31 DNP
LVDS(2) AC R25, R27, R28, R30 0 Ω
R31 100 Ω
C24, C25 0.01 uF
R26, R29 DNP
DC R25, R27, R28, R30, C24, C25 0 Ω
R31 100 Ω
HCSL AC R25, R28 0 Ω(22 Ωoptional)
R26, R29 50 Ω
C24, C25 0 Ω
R27, R30, R31 DNP
DC R25, R28 0 Ω(22 Ωoptional)
R26, R29 50 Ω
C24, C25 0.01 uF
R27, R30, R31 DNP
(1) 50 ohm to Vcc-2 V termination is required on receiver.
(2) 100 ohm differential termination (R31) is provided on the LMK61E2EVM. Removing the differential termination on the EVM is
possible if the differential termination is available on the receiver.
Figure 5. LMK61E2EVM Termination Schematic
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www.ti.com Using the USB Interface Connection
7 Using the USB Interface Connection
The on-board MSP430F5529 USB microcontroller (U4) provides an I2C host interface to the LMK61E2
slave device. The device registers can be controlled via USB using the GUI platform running on a Host
PC.
8 EVM Quick Start Guide
The following guide allows the user to quickly configure the LMK61E2 to evaluate performance and device
flexibility
• 1. Set the Control Pin jumpers to the default configuration as noted in Table 1Table 3.
• 2. Confirm the EVM Default power configuration is set per Table 2 to power the LMK61E2 in USB
POWER mode using the on-board LDO regulators and power supplied over USB.
• 3. Observe any active output clock on OUTN and OUTP SMA ports.
– 3.1. Default EVM configuration is AC coupled LVPECL as noted in Table 4.
– 3.2. Use 50-ohm coax cables to connect the test equipment to the output SMA ports. If making a
single-ended measurement, terminate the unused SMA port with a 50-ohm load.
– 3.3. Power LEDs, D3 & D5 should be illuminated when the EVM is connected to power
– 3.4. I2C activity can be seen on LED D4 (active with activity).
• 4. Refer to Table 5 for recommended device configurations configurable via the GUI.
Table 5. Recommended Device Configurations(1)
PARAMETER 156.25 MHz(2) 100 MHz 161.1328125 MHz
PLL Reference Doubler Enabled
N Divider 50 48 51
Fractional Numerator 22500
Fractional Denominator 40000
VCO frequency 5000 MHz 4800 MHz 5162.25 MHz
Output Divider 32 16 32
Loop Filter Charge Pump Gain 6.4 mA 2.8 mA
Loop Filter Order 2nd Order 3rd Order
C1 5 pF 105 pF
C2 10 nF
C3 0 pF 35 pF
R2 800 Ω1.1 kΩ
R3 18 Ω1.3 kΩ
Modulator Order Integer Mode 1st Order
Dithering Disable Weak
Charge Pump Bleed None 8.5 kΩ1 ns
(1) Termination schemes should match device settings. See Table 4.
(2) Device default
9 Recommended Test Instruments
For making accurate measurements on ultra-low noise/jitter, high-speed clock signals, the following
instruments are recommended:
• Source Signal Analyzer: Keysight/Agilent E5052 for phase noise/jitter measurements
• Oscilloscope: Agilent DSA90000A series (or equivalent) for AC measurements and time-domain jitter
analysis with jitter software package
• Balun: M/A-COM H-183-4 (30-3000 MHz) 180° coupler, or equivalent
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Example Performance Measurements www.ti.com
10 Example Performance Measurements
RMS Jitter and phase noise measurements were taken on the differential output clock was measured
using a balun to a Keysight/Agilent E5052B. Some phase noise plots are provided below.
Table 6. Typical Output RMS Jitter Summary
Output Frequency Output Format(1) RMS Jitter (fs),12k-20M band, Reference Plot
spurs off
156.25 MHz LVPECL 90 Figure 6
LVDS 100 Figure 7
HCSL 100
161.1328125 MHz LVPECL 150
LVDS 150
HCSL 150 Figure 8
(1) All measurements are AC coupled with recommended board terminations as in Table 4.
Figure 6. 156.25 MHz LVPECL Differential Phase Noise
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Figure 7. 156.25 MHz LVDS Differential Phase Noise
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Example Performance Measurements www.ti.com
Figure 8. 161.1328125 MHz HCSL Differential Phase Noise
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11 EVM Layout
Figure 9. Top Overlay
Figure 10. Top Solder Mask
Figure 11. Layer 1 (Top Side)
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EVM Layout www.ti.com
Figure 12. Layer 4 (Bottom Side, View From Bottom)
Figure 13. Bottom Solder Mask
Figure 14. Bottom Overlay
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www.ti.com EVM Layout
Figure 15. Drill Drawing
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LMK61XX Evaluation Module (EVM)
LOGO
PCB
Texas Instruments
FID2
FID1
SV601195
A
PCB Number:
PCB Rev:
PCB Label
LBL1
Size: 0.65" x 0.20 "
Label Table
Variant Label Text
001 LMK61E2 EVM
HARDWARE AND MARKINGS
Label Assembly Note
ZZ1
This Assembly Note is for PCB labels only
ASSEMBLY NOTES
DIMENSIONS:
-- Rectangular shape with height minimized (SMA spacing + board stand offs)
-- Final PCB thickness 62 mil +/- 10% ****
STACKUP:
-- Layer 1: Device layer, Power/GPIO Jumper/Switches, RF microstrip from DUT
to SMA, USB connector, Silkscreens + Labeling
===== FR4: 8 mil
-- Layer 2: Ground Plane
===== FR4: 38 mil
-- Layer 3: Split Power planes for USB circuitry and DUT circuitry
===== FR4: 8
-- Layer 4: USB circuitry
Controlled Impedance Traces
-- TOP: 13 mil traces to be 50 ohm Zo +/- 5% reference to L2
LAYOUT NOTE:
PLace 4 standoffs at corners of board.
H3
TCBS-6-01
H4
TCBS-6-01
H2
TCBS-6-01
H1
TCBS-6-01
LOGO
PCB
Pb-Free Symbol
LOGO
PCB
FCC disclaimer
Assembly Note
ZZ2
These assemblies are ESD sensitive, ESD precautions shall be observed.
Assembly Note
ZZ3
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
Assembly Note
ZZ4
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
Assembly Note
ZZ5
Default Shunt settings: SH1_2-3 means short Pins 2-3of J2 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
Assembly Note
ZZ6
Default Shunt settings: SH2_2-3 means short Pins 2-3 of J3 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
Assembly Note
ZZ7
Default Shunt settings: SH3_2-3 means short Pins 2-3 of J5 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
Assembly Note
ZZ8
Default Shunt settings: SH4_2-3 means short Pins 2-3 of J6 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
Assembly Note
ZZ9
Default Shunt settings: SH5_2-3 means short Pins 2-3 of J9 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
Assembly Note
ZZ10
Default Shunt settings: SH6_2-3 means short Pins 2-3 of J10 jumper. For 3-way jumpers, Pin 4 is the 1-pin header.
EVM Schematic www.ti.com
12 EVM Schematic
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Green
1
2
D5
MSP_LED
270
R14
1
23
Q1
BSS138
VBUS
D_N
D_P
0.1µF
C1
33 0402R1
33 0402R3
1.2Meg
R7
220pF
C11
1
2
3
4
S1
BSL
1.5k
0402
R4
PUR
VUSB
220pF
C17
7.5V
D1
1SMB5922BT3G
22µF
0805
C5 10µF
C2
10µF
C3
U2A_3V3
P6.4/CB4/A4 1
P6.5/CB5/A5 2
P6.6/CB6/A6 3
P6.7/CB7/A7 4
P7.0/CB8/A12
5
P7.1/CB9/A13
6
P7.2/CB10/A14
7
P7.3/CB11/A15
8
P5.0/A8/VREF+/VEREF+
9
P5.1/A9/VREF-/VEREF-
10
AVCC1
11
P5.4/XIN
12
P5.5/XOUT
13
AVSS1 14
P8.0 15
P8.1 16
P8.2 17
DVCC1
18 DVSS1 19
VCORE
20
P1.0/TA0CLK/ACLK
21
P1.1/TA0.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/TA0.3
25
P1.5/TA0.4
26
P1.6/TA1CLK/CBOUT
27
P1.7/TA1.0
28
P2.0/TA1.1 29
P2.1/TA1.2 30
P2.2/TA2CLK/SMCLK 31
P2.3/TA2.0 32
P2.4/TA2.1 33
P2.5/TA2.2 34
P2.6/RTCCLK/DMAE0 35
P2.7/UCB0STE/UCA0CLK 36
P3.0/UCB0SIMO/UCB0SDA
37
P3.1/UCB0SOMI/UCB0SCL
38
P3.2/UCB0CLK/UCA0STE
39
P3.3/UCA0TXD/UCA0SIMO
40
P3.4/UCA0RXD/UCA0SOMI
41
P3.5/TB0.5
42
P3.6/TB0.6
43
P3.7/TB0OUTH/SVMOUT
44
P4.0/PM_UCB1STE/PM_UCA1CLK 45
P4.1/PM_UCB1SIMO/PM_UCB1SDA 46
P4.2/PM_UCB1SOMI/PM_UCB1SCL 47
P4.3/PM_UCB1CLK/PM_UCA1STE 48
DVSS2 49 DVCC2
50
P4.4/PM_UCA1TXD/PM_UCA1SIMO 51
P4.5/PM_UCA1RXD/PM_UCA1SOMI 52
P4.6/PM_NONE 53
P4.7/PM_NONE 54
P5.6/TB0.0
55
P5.7/TB0.1
56
P7.4/TB0.2
57
P7.5/TB0.3
58
P7.6/TB0.4
59
P7.7/TB0CLK/MCLK
60
VSSU 61
PU.0/DP 62
PUR 63
PU.1/DM 64
VBUS
65
VUSB
66
V18
67
AVSS2 68
P5.2/XT2IN
69
P5.3/XT2OUT
70
TEST/SBWTCK 71
PJ.0/TDO 72
PJ.1/TDI/TCLK 73
PJ.2/TMS 74
PJ.3/TCK 75
RST/NMI/SBWTDIO 76
P6.0/CB0/A0 77
P6.1/CB1/A1 78
P6.2/CB2/A2 79
P6.3/CB3/A3 80
U4
MSP430F5529IPN
0.1µF
C21
0.1µF
C20
0.1µF
C19
U2A_3V3
PUR
U2A_3V3
0.47µF
C18
VBUS
VUSB USER NOTE:
Features not supported by On-board or External USB2ANY circuiry
- Switched +3.3V_EXT supply
- Switched +5V_EXT supply
- ADCs 0-4
- DACs 0-1
- PWMs 0-3
- SPI interface (I2C/SMBus only)
I2CPU
V18
EXT5V_EN
EXT5V_FAULT
EXT3.3V_EN
EXT3.3V_FAULT
0.1µF
C15
100k
R16
2200pF
C16
33k
R15
U2A_3V3
D_N
D_P
1
2
24MHz
Y1
ECS-240-20-5PX-TR
33k
R5
VCORE
SDA
SCL
0 R10
0R11
U2A_GPIO4
U2A_GPIO5
0 R12
0 R13
USER NOTE:
De-populate the 0-ohm resistors connected to "U2A_GPIOx" and "U2A_3V3"
nets before attaching the External USB2ANY module to the USB2ANY Header.
LAYOUT NOTE:
Place 0-ohm footprints close to USB2ANY Header pins to minimize trace stubs
when 0-ohm resistors are de-populated (to disconnect the on-board MSP430).
3.3 V, 150 mA REGULATOR FOR USB2ANYUSB MINI-B CONNECTOR
ON-BOARD USB2ANY/MSP430
VBUS_FILT
33k
R2
0.1µF
C9
VIN
1
GND 2
EN
3
N/C
4
VOUT 5
U2
LP5907MFX-3.3/NOPB
33k
R6
0.1µF
C12
20V
D2
B220A-13-F 10µF
C6
1µF
C7
0.1µF
C8
GND GND GND GND
EXTIN
SH1_2_3
VDD
EXTIN
SH2_2_3
VDD_REG
VBUS_FILT
3.3 V, 250 mA REGULATOR FOR LMK61XX
Green
1
2
D3
VDD
I=5mA
SDA SCL
U2A_GPIO2 U2A_GPIO3
U2A_GPIO4 U2A_GPIO5
U2A_GPIO6 U2A_GPIO7
J7 connects to J5 of USB2ANY module via Ribbon cable
USB2ANY HEADER (VERTICAL)
SCL
SDA
2
3
4
1
5
J1
1734035-2
60 ohm
FB1
1 2
3 4
5 6
7 8
9 10
J4
DNP
TP2
TP3
1
2 3 4 5
P1
EXTIN
SH4_2_3
1.5k
R17
1.5k
R19
VDD
GND
OE
SH3_2_3
1.5k
R18
1.5k
R20
VDD
GND
ADD
OE / ADD JUMPERS
1µF
C10
1µF
C4
1
2
3
J5
OE
1
2
3
J6
ADD
1
2
3
J2
REG SUP
1 2 3
J3
IC SUP
1 1
LABEL SW: BSL
LABEL PINS:
1 = SDA
2 = SCL
5 = GND
6 = 3.3V
8 = OE
10 = ADD
LABEL PINS:
1 = GND
2 = <JP NAME>
3 = VDD
4 = U2A
LABEL PINS:
1 = GND
2 = <JP NAME>
3 = VDD
4 = U2A
LAYOUT NOTE:
Place C10 and C4 on the same side as U
and as close to the package as possible. Use
wide and short traces.
LAYOUT NOTE:
Place LED on L1, other components can be on L4
VDD
510
R8
Orange
1
2
D4
I2C
270
R9
U2A_3V3
U2A_GPIO5U2A_GPIO4
30pF
C13
30pF
C14
USB_N
USB_P
IO1 1 IO2 2
GND
3
IO3
4IO4 5
VCC 6
U3
TPD4E004DRYR
IN
6OUT 1
GND 3
EN
4
NC 5
DAP
7
NC 2
U1
LP5900SD-3.3/NOPB
www.ti.com EVM Schematic
19
SNAU188–October 2015 LMK61E2EVM User's Guide
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OUT_P
0.1µF
C25
0.1µF
C24
0
R25
0
R28
LAYOUT NOTE:
Place shunt resistors
near the output pins.
OUT_N
R_OUT_P
R_OUT_N
LAYOUT NOTE:
Place close to SMA
ports.
LAYOUT NOTE:
Individual vias to
GND on shunt
resistors.
OE
1
ADD 2
GND 3
SCL
8
OUTP 4
OUTN 5
VCC
6
SDA
7
U5
LMK06001SIA
GND
SDA
SCL
VDD
OE
ADD
1
2 3 4 5
P2
OUTP
1
2 3 4 5
P3
OUTN
SH5_2_3
1
2
3
J9
FS0
4.7k
R21
VDD
4.7k
R23
GND
SH6_2_3
1
2
3
J10
FS1
4.7k
R22
VDD
4.7k
R24
GND
0.01µF
C22
GND
LABEL PINS:
1 = VDD
2 = <JP NAME>
3 = GND
LABEL PINS:
1 = VDD
2 = <JP NAME>
3 = GND
LMK61XX
4.7µF
C23
GND
0
R27
DNP
100
R31
0
R30
DNP
150
R26
150
R29
EVM Schematic www.ti.com
20 LMK61E2EVM User's Guide SNAU188–October 2015
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Copyright © 2015, Texas Instruments Incorporated