Texas Instruments LMK61E2EVM User manual

LMK61E2EVM
User's Guide
Literature Number: SNAU188
October 2015

Contents
1 Overview ............................................................................................................................ 5
2 Features ............................................................................................................................. 5
3 Configuring the EVM ............................................................................................................ 6
4 Configuring the Power Supply .............................................................................................. 6
5 Configuring the Control Pins................................................................................................. 8
6 Configuring the Clock Output .............................................................................................. 10
7 Using the USB Interface Connection..................................................................................... 11
8 EVM Quick Start Guide........................................................................................................ 11
9 Recommended Test Instruments.......................................................................................... 11
10 Example Performance Measurements................................................................................... 12
11 EVM Layout ....................................................................................................................... 15
12 EVM Schematic.................................................................................................................. 18
13 EVM Bill of Materials........................................................................................................... 21
2Table of Contents SNAU188–October 2015
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List of Figures
1 LMK61E2EVM Photo........................................................................................................ 4
2 LMK61E2EVM Board Layout............................................................................................... 6
3 Power Terminals and Jumpers............................................................................................. 7
4 Control Pin Interfaces (Default jumper settings shown) ............................................................... 8
5 LMK61E2EVM Termination Schematic.................................................................................. 10
6 156.25 MHz LVPECL Differential Phase Noise ........................................................................ 12
7 156.25 MHz LVDS Differential Phase Noise ........................................................................... 13
8 161.1328125 MHz HCSL Differential Phase Noise.................................................................... 14
9 Top Overlay................................................................................................................. 15
10 Top Solder Mask ........................................................................................................... 15
11 Layer 1 (Top Side) ......................................................................................................... 15
12 Layer 4 (Bottom Side, View From Bottom) ............................................................................. 16
13 Bottom Solder Mask ....................................................................................................... 16
14 Bottom Overlay ............................................................................................................. 16
15 Drill Drawing ................................................................................................................ 17
List of Tables
1 Ordering Information ........................................................................................................ 4
2 Power Configurations ....................................................................................................... 7
3 Control Pin Interfaces ....................................................................................................... 9
4 Output Termination Schemes............................................................................................. 10
5 Recommended Device Configurations .................................................................................. 11
6 Typical Output RMS Jitter Summary..................................................................................... 12
3
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User's Guide
SNAU188–October 2015
LMK61E2EVM User's Guide
Figure 1. LMK61E2EVM Photo
Table 1. Ordering Information
EVM ID DEVICE ID DEVICE PACKAGE
LMK61E2EVM LMK61E2-SIA 5 mm x 7 mm 8-pin QFM (SIA)
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www.ti.com Overview
1 Overview
The LMK61E2EVM evaluation module provides a complete evaluation platform to evaluate the clock
performance and flexibility of the Texas Instruments LMK61E2 Ultra-Low Jitter Crystal Oscillator, with
integrated tunable 50 MHz crystal, low noise PLL, differential output, and integrated EEPROM.
The LMK61E2EVM can be used as a flexible clock source for compliance testing, performance evaluation,
and initial system prototyping. The onboard edge-launch SMA ports provides access to the LMK61E2’s
configurable clock output for interfacing to test equipment and reference boards using commercially
available coaxial cables, adapters, or baluns (not included). This connectivity enables integrated system
level testing between TI’s LMK61E2 and third-party FPGA/ASIC/SoC reference boards. A software
graphical user interface (GUI) platform can be installed on a Host PC to access the LMK61E2’s device
registers and EEPROM via the on-board USB-to-I2C interface.
2 Features
• Integrated low noise 50 MHz tunable crystal
– Fine frequency margining in ppm steps via I2C
• Coarse frequency margining in percentage steps via I2C
• Configurable output format of either LVPECL, LVDS, or HCSL
• Programmable Output Enable polarity
• EEPROM allows for custom configuration for power up defaults
• Footprint compatible with industry standard 5 mm x 7 mm XO package
– 2 additional pins allow for optional I2C programing
• GUI platform for full access to device registers and EEPROM
• On-board USB-to-I2C programming interface
• External Power supply inputs or powered over USB
• LEDs indicators: Device Power and USB / I2C activity
• Configurable output format of either LVPECL, LVDS, or HCSL
5
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Configuring the EVM www.ti.com
3 Configuring the EVM
The LMK61E2 is a highly-configurable crystal oscillator with simple power supply requirements and
flexible clock output formats. To support a wide range of evaluation use cases, the EVM was designed for
maximum flexibility so various configurations options that are not required in all typical system applications
have been included.
This section describes the jumpers and connectors on the EVM, as well as how to connect, set-up, and
use the LMK61E2EVM. When operating the LMK61E2EVM, the power supply and clock outputs can be
connected to the SMA ports shown in Figure 2. Additionally, the USB port can be used to power the entire
LMK61E2EVM without the need for external power supplies. These SMA ports are labeled in the top
silkscreen layer.
Figure 2. LMK61E2EVM Board Layout
4 Configuring the Power Supply
The LMK61E2 features a single VDD supply pin that operates from 3.3V (+ 5%). This supply can be
powered directly from an external supply or through an on-board LDO regulator. Although the LMK61E2
has integrated LDO regulators for excellent power-supply-ripple-rejection (PSRR), the EVM’s on-board
regulator (U2) can allow a higher supply voltage (like 5 V) to power the EVM. The direct external supply or
on-board regulator can be independently routed for the VDD supply pin by configuring the power terminals
and jumpers shown in Figure 3. J1 (USB mini connector) is the default power supply for the EVM,
featuring a low noise regulator for voltage step down. Power SMA Port EXTIN (P1) provides an alternative
connector style to apply power using coax cables. Using EXTIN while connected to USB power is not
required but can be useful when testing with externally regulated supplies.
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www.ti.com Configuring the Power Supply
Figure 3. Power Terminals and Jumpers
Table 2 summarizes the EVM power configurations to connect and route power to the onboard LDOs and
LMK61E2. Refer to the EVM schematic for more details.
Table 2. Power Configurations
MODE EXTIN VOLTAGE J2 SETTING (1) J3 SETTING (1)
USB Powered (2) USB PWR
External Power + LDO 4.3 V to 5.5 V EXT PWR REG
External Power 3.3 V Remove Jumper EXT PWR
(1) Markings left of J2 indicate the orientation of jumper settings EXT PWR (pins 1 and 2 of jumper) and USB PWR / REG (pins 2
and 3 of jumper)
(2) USB cable must be connected to J1 for operation
7
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Configuring the Control Pins www.ti.com
5 Configuring the Control Pins
The LMK61E2 has several control pins dedicated for control of I2C communications, device I2C address,
and output enable control. These control pins can be configured through the jumpers shown in .
Figure 4. Control Pin Interfaces (Default jumper settings shown)
Jumpers J9 and J10 can be used to configure the corresponding control pin to either high or low state by
strapping the center pin to “VDD” position (tie pins 1-2) or “GND” position (tie pins 2-3), respectively.
Connections from the “VDD” position to the device supply or from the “GND” position to the ground plane
are connected by 4.7 kΩresistors.
Jumpers J5 and J6 can be configured in a static configuration through a high or low state by strapping the
center pin to “VDD” position or to the “GND” position. Similarly, these connections are made through a 4.7
kΩresistor to the respective supply and ground planes. The third position, “U2A”, allows for control of the
respective control pins over software via the onboard microcontroller. Biasing is established externally and
is default set to a high state.
The LMK61E2 control pins serve several functions unique to device pins. For a description of each pin’s
functionality and the device configuration based on their power up state, refer to Table 3.
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www.ti.com Configuring the Control Pins
Table 3. Control Pin Interfaces
COMPONENT NAME (TYPE) DESCRIPTION DESCRIPTION
J5 OE (passive or software control) Output Enable Pin Output Enable Pin
OE state controls the device output operation. Polarity can be
adjusted in the LMK61E2’s register settings.
OE STATE OPERATING MODE (based on
default)
GND Output Disabled
VDD (JP Default) Output Enabled
J6 ADD (passive or software I2C Slave Address LSB Select
control) pin
ADD is sampled on POR to configure the lower 2 bits of the 7-bit
slave address. The upper 5 bits of the slave address are initialized
from EEPROM (SLAVEADR[7:3] = 10110b). By configuring ADD, the
composite slave address can be selected as follows:
ADD STATE 7-BIT SLAVE ADDRESS
(excludes W/R bit)
GND 1011000b / 0x58
High Z (no connect) 1011001b / 0x59
VDD (JP Default) 1011011b / 0x5B
J9 J10 SCL SDA I2C Serial Interface Pins
(I2C inputs) An I2C master device can interface with the LMK61E2 over the I2C
clock line (SCL) and data line (SDA). The open drain topology of the
SCL and SDA pins require an external pull up resistor. J9 and J10
should always be set in the VDD position to ensure proper I2C
communication. The SCL and SDA lines are connected with the
onboard microcontroller, which is controlled by the GUI.
J1 USB (not shown in Figure 4) USB port (Mini-B type) USB port (Mini-B type)
Using the GUI platform, USB controller (U4) provides the USB-to-I2C
interface to manage the LMK61E2 device registers and EEPROM.
When USB communication is established with a Host PC running the
GUI, LED D5 should be lit solid green.
The USB port powers LDO regulator U1 to supply 3.3 V power for
the MCU and its peripheral circuitry.
J4 (not populated) U2A Optional Test Point Access to I2C and Control pins
Pin 1: SDA Pin 2: SCL
Pin 4: N/C Pin 3: N/C
Pin 5: GND Pin 6: N/C
Pin 7: OE Pin 8: ADD
Pin 9: N/C Pin 10: N/C
9
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OUT_P
0.1µF
C25
0.1µF
C24
0
R25
0
R28
OUT_N
R_OUT_P
R_OUT_N
1
2 3 4 5
P2
OUTP
1
2 3 4 5
P3
OUTN
0
R27
100
R31
0
R30
150
R26
150
R29
Configuring the Clock Output www.ti.com
6 Configuring the Clock Output
The LMK61E2’s differential output is routed via 50 ohm single ended traces to SMA ports (OUTN and
OUTP) through AC coupling capacitors. The output also has a series resistor (0 ohm populated by default,
R25 ad R28) and emitter resistors (150 ohm populated by default for LVPECL, R26 and R29). Common
output format terminations are shown in Table 4. The output termination schematic is shown in Figure 5.
Table 4. Output Termination Schemes
OUTPUT FORMAT COUPLING COMPONENT VALUE
LVPECL AC R25, R28 0 Ω
(default EVM R26, R29 150 Ω
configuration) C24, C25 0.01 uF
R27, R30, R31 DNP
DC(1) R25, R28, C24, C25 0 Ω
R26, R27, R29, R30, R31 DNP
LVDS(2) AC R25, R27, R28, R30 0 Ω
R31 100 Ω
C24, C25 0.01 uF
R26, R29 DNP
DC R25, R27, R28, R30, C24, C25 0 Ω
R31 100 Ω
HCSL AC R25, R28 0 Ω(22 Ωoptional)
R26, R29 50 Ω
C24, C25 0 Ω
R27, R30, R31 DNP
DC R25, R28 0 Ω(22 Ωoptional)
R26, R29 50 Ω
C24, C25 0.01 uF
R27, R30, R31 DNP
(1) 50 ohm to Vcc-2 V termination is required on receiver.
(2) 100 ohm differential termination (R31) is provided on the LMK61E2EVM. Removing the differential termination on the EVM is
possible if the differential termination is available on the receiver.
Figure 5. LMK61E2EVM Termination Schematic
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