Texas Instruments LMK048 Series User manual

LMK048xx Evaluation Board
User's Guide
August 2011
SNAU076B
Revised August 2014
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Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
Evaluation Board Operating Instructions
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Table of Contents
TABLE OF CONTENTS ..............................................................................................................................................................3
GENERAL DESCRIPTION ..........................................................................................................................................................5
EVALUATION BOARD KIT CONTENTS ...................................................................................................................................................5
AVAILABLE LMK048XX EVALUATION BOARDS......................................................................................................................................5
AVAILABLE LMK04800 FAMILY DEVICES ............................................................................................................................................5
QUICK START ..........................................................................................................................................................................6
DEFAULT CODELOADER MODES FOR EVALUATION BOARDS.....................................................................................................................7
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04808B ............................................................................................8
1. START CODELOADER 4APPLICATION...............................................................................................................................................8
2. SELECT DEVICE............................................................................................................................................................................8
3. PROGRAM/LOAD DEVICE..............................................................................................................................................................8
4. RESTORING A DEFAULT MODE .......................................................................................................................................................9
5. VISUAL CONFIRMATION OF FREQUENCY LOCK .................................................................................................................................10
6. ENABLE CLOCK OUTPUTS ............................................................................................................................................................10
PLL LOOP FILTERS AND LOOP PARAMETERS .........................................................................................................................12
PLL 1LOOP FILTER .......................................................................................................................................................................12
122.88 MHz VCXO PLL .........................................................................................................................................................12
PLL2 LOOP FILTER ........................................................................................................................................................................13
Integrated VCO PLL .............................................................................................................................................................13
EVALUATION BOARD INPUTS AND OUTPUTS........................................................................................................................14
RECOMMENDED TEST EQUIPMENT ......................................................................................................................................22
PROGRAMMING 0-DELAY MODE IN CODELOADER ...............................................................................................................23
OVERVIEW...................................................................................................................................................................................23
DUAL LOOP 0-DELAY MODE EXAMPLES ............................................................................................................................................23
Programming Steps.............................................................................................................................................................23
Details .................................................................................................................................................................................23
SINGLE LOOP 0-DELAY MODE EXAMPLES ..........................................................................................................................................25
Programming Steps.............................................................................................................................................................25
Details .................................................................................................................................................................................25
APPENDIX A: CODELOADER USAGE.......................................................................................................................................27
PORT SETUP TAB ..........................................................................................................................................................................27
CLOCK OUTPUTS TAB.....................................................................................................................................................................28
PLL1 TAB....................................................................................................................................................................................30
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency........................................................................................31
PLL2 TAB....................................................................................................................................................................................32
BITS/PINS TAB .............................................................................................................................................................................33
REGISTERS TAB.............................................................................................................................................................................38
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS..................................................................................................39
PLL1..........................................................................................................................................................................................39
122.88 MHz VCXO Phase Noise ...........................................................................................................................................39
Clock Output Measurement Technique...............................................................................................................................40
Buffered OSCout Phase Noise..............................................................................................................................................40
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CLOCK OUTPUTS (CLKOUT) ............................................................................................................................................................41
LMK04808B CLKout Phase Noise.........................................................................................................................................41
LMK04808B OSCout Phase Noise ........................................................................................................................................43
LMK04806B CLKout Phase Noise.........................................................................................................................................44
LMK04806B OSCout Phase Noise ........................................................................................................................................46
LMK04803B CLKout Phase Noise.........................................................................................................................................47
LMK04803B OSCout Phase Noise ........................................................................................................................................49
APPENDIX C: SCHEMATICS ....................................................................................................................................................50
POWER SUPPLIES ..........................................................................................................................................................................50
LMK048XXBDEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS...........................................................................................................51
REFERENCE INPUTS (CLKIN0&CLKIN1), EXTERNAL VCXO (OSCIN)&VCO CIRCUITS,AND OSCOUT1OUTPUT...........................................52
CLOCK OUTPUTS (OSCOUT0, CLKOUT0TO CLKOUT3)........................................................................................................................53
CLOCK OUTPUTS (CLKOUT4TO CLKOUT7)........................................................................................................................................54
CLOCK OUTPUTS (CLKOUT8TO CLKOUT11)......................................................................................................................................55
UWIRE HEADER,LOGIC I/O PORTS AND STATUS LEDS.........................................................................................................................56
USB INTERFACE............................................................................................................................................................................57
APPENDIX D: BILL OF MATERIALS .........................................................................................................................................58
APPENDIX E: PCB LAYERS STACKUP .....................................................................................................................................68
APPENDIX F: PCB LAYOUT.....................................................................................................................................................69
LAYER #1 –TOP ...........................................................................................................................................................................69
LAYER #2 –RF GROUND PLANE (INVERTED)......................................................................................................................................70
LAYER #3 –VCC PLANES ................................................................................................................................................................71
LAYER #4 –GROUND PLANE (INVERTED)...........................................................................................................................................72
LAYER #5–VCC PLANES 2.............................................................................................................................................................73
LAYER #6 –BOTTOM.....................................................................................................................................................................74
LAYERS #1 AND 6–TOP AND BOTTOM (COMPOSITE)..........................................................................................................................75
APPENDIX G: EVM SOFTWARE AND COMMUNICATION: INTERFACING UWIRE.....................................................................76
APPENDIX H: TROUBLESHOOTING INFORMATION................................................................................................................78
1) CONFIRM COMMUNICATIONS ................................................................................................................................................78
2) CONFIRM PLL1 OPERATION/LOCKING .....................................................................................................................................78
3) CONFIRM PLL2 OPERATION/LOCKING .....................................................................................................................................79
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General Description
The LMK048xx Evaluation Board simplifies evaluation of the LMK048xxB Low-Noise Clock Jitter
Cleaner with Dual Loop PLLs. Texas Instruments Incorporated’s CodeLoader software can be used to
program the internal registers of the LMK048xxB device through the USB2ANY-uWire interface. The
CodeLoader software will run on a Windows 7 or Windows XP PC and can be downloaded from
http://www.ti.com/tool/codeloader/.
Evaluation Board Kit Contents
The evaluation board kit includes:
•(1) LMK048xx Evaluation Board from Table 1
•(1) LMK04800 Family Quick Start Guide
oEvaluation board instructions can be downloaded from www.ti.com.
•(1) LPT Cable or USB2ANY-uWire (HPA665-001) + adapter (Please see “EVM Software and
Communication” for more information)
Available LMK048xx Evaluation Boards
The LMK048xx Evaluation Board supports any of the four devices offered in the LMK04800 Family. All
evaluation boards use the same PCB layout and bill-of-materials, except for the corresponding
LMK0480xxB device affixed to the board. A commercial-quality VCXO is also mounted to the board to
provide a known reference point for evaluating device performance and functionality.
Table 1: Available Evaluation Board Configurations
Evaluation Board ID
Device
PLL1 VCXO
LMK04803BEVAL
LMK04803B
122.88 MHz Crystek VCXO
Model CVHD-950-122.880
LMK04805BEVAL
LMK04805B
LMK04806BEVAL
LMK04806B
LMK04808BEVAL
LMK04808B
Available LMK04800 Family Devices
Table 2: LMK048xxB Devices
Device Reference
Inputs
Buffered/
Divided
OSCin
Outputs
Programmable
LVDS/LVPECL/
LVCMOS
Outputs
VCO Frequency
LMK04803B
2 2 12
1840 to 2030 MHz
LMK04805B
2148 to 2370 MHz
LMK04806B
2370 to 2600 MHz
LMK04808B
2750 to 3072 MHz
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Quick Start
Full evaluation board instructions are downloadable from the LMK048xxB device product folder at
www.ti.com.
1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard LP3878-ADJ
LDO regulator will output a low-noise 3.3 V supply to operate the device.
2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 122.88 MHz for
default. The reference frequency depends on the device programming.
3. Please see Appendix G for quick start on interfacing the board
4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at least once
to load all registers. Alternatively click menu “Keyboard Controls” “Load Device”.
CodeLoader can be downloaded from http://www.ti.com/tool/codeloader.
5. Measurements may be made on an active output clock port via its SMA connector.
Figure
1: Quick Start Diagram
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Default CodeLoader Modes for Evaluation Boards
CodeLoader saves the state of the selected LMK048xxB device when exiting the software. To ensure a
common starting point, the following modes listed in Table 3 may be restored by clicking “Mode” and
selecting the appropriate device configuration, as shown in Figure 2 in the case of the LMK04808B
device. Similar default modes are available for each LMK048xxB device in CodeLoader. Choose a mode
with CLKin0 for differential clock signal or CLKin1 for a single ended signal.
Figure 2: Selecting a Default Mode for the LMK04808 Device
After restoring a default mode, press Ctrl+L to program the device. The default modes also disable
certain outputs, so make sure to enable the output under test to make measurements.
Table 3: Default CodeLoader Modes for LMK04808
Default CodeLoader Mode Device Mode
CLKin
Frequency
OSCin
Frequency
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
122.88 MHz CLKin1, Dual Loop 0-
delay, 122.88 MHz VCXO
Dual PLL, Internal VCO,
0-Delay with Internal
Feedback
122.88 MHz 122.88 MHz
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO,
PLL2 Crystal Oscillator
Enabled
122.88 MHz 20.48 MHz
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
122.88 MHz CLKin1, Dual Loop 0-
delay, 122.88 MHz VCXO
Dual PLL, Internal VCO,
0-Delay with Internal
Feedback
122.88 MHz 122.88 MHz
122.88 MHz CLKin1, 122.88 MHz
VCXO
Dual PLL, Internal VCO,
PLL2 Crystal Oscillator
Enabled
122.88 MHz 20.48 MHz
The next section outlines step-by-step procedures for using the evaluation board with the LMK04808B.
For boards with another part number, make sure to select the corresponding part number under the
“Device” menu.
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Example: Using CodeLoader to Program the LMK04808B
The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements
with the LMK04808B device as an example. For more information on CodeLoader refer to Appendix A:
CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. Start CodeLoader 4 Application
Click “Start” “Programs” “CodeLoader 4” “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” “Clock Conditioners” “LMK04808B”
Once started CodeLoader 4 will load the last used
device. To load a new device click “Select Device”
from the menu bar, then select the subgroup and
finally device to load. For this example, the
LMK04808B is chosen. Selecting the device does
cause the device to be programmed.
Figure 3 – Selecting the LMK04808B device
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3. Program/Load Device
Assuming the Port Setup settings are correct, press the
“Ctrl+L” shortcut or click “Keyboard Controls” “Load
Device” from the menu to program the device to the
current state of the newly loaded LMK04800 file.
Once the device has been initially loaded, CodeLoader will
automatically program changed registers so it is not
necessary to re-load the device upon subsequent changes in the device configuration. It is possible to
disable this functionality by ensuring there is no checkmark by the “Options” “AutoReload with
Changes.”
Because a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting CodeLoader,
restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader for more information on Port Setup. Appendix H: Troubleshooting
Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode” “LMK04808B, 122.88 MHz VCXO, 122.88 MHz CLKin1”; then press Ctrl+L.
Figure 5: Setting the Default mode for LMK04808
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.
This is important because when CodeLoader is closed, it remembers the last settings used for a particular
device. Again, remember to press Ctrl+L as the first step after loading a default mode.
Figure 4 – Loading the Device
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5. Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2 are locked
to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD and LD_TYPE =
Active High, which are the default settings.
6. Enable Clock Outputs
While the LMK048xxB offers programmable clock output buffer formats, the evaluation board is shipped
with preconfigured output terminations to match the default buffer type for each output. Refer to the
CLKout port description in the Evaluation Board Inputs and Outputs section.
To measure phase noise at one of the clock outputs, for example, CLKout0:
1. Click on the Clock Outputs tab,
2. Uncheck “Powerdown” in the Digital Delay box to enable the channel,
3. Set the following settings as needed:
a. Digital Delay value
b. Clock Divider value
c. Analog Delay select and Analog Delay value (if not “Bypassed”)
d. Clock Output type.
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test
instrument with a single-ended 50-ohm input as follows.
a. For LVDS:
i. A balun (like ADT2-1T) is recommended for differential-to-single-ended
conversion.
b. For LVPECL:
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50-ohm load and the
other side can be run single-ended to the instrument.
c. For LVCMOS:
i. There are two single-ended outputs,
CLKoutX and CLKoutX*, and each output
can be set to Normal, Inverted, or Off. There
are nine (9) combinations of LVCMOS modes
in the Clock Output list.
ii. One side of the LVCMOS signal can be
terminated with a 50-ohm load and the other
side can be run single-ended to the
instrument.
iii. A balun may also be used. Ensure
CLKoutX and CLKoutX* states are
Figure 7: Setting LVCMOS modes
Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0
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complementary to each other, i.e.: Norm/Inv or Inv/Norm.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs.
Texas Instruments Incorporated’s Clock Design Tool can be used to calculate divider values to achieve
desired clock output frequencies. See: http://www.ti.com/tool/clockdesigntool.
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PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a
“dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to
minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a
frequency reference rather than a phase reference.
The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter
for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has
been configured for a wide loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on
the phase noise performance of the oscillator mounted on the board. The following tables contain the
parameters for PLL1 and PLL2 for each oscillator option.
Texas Instruments Incorporated’s Clock Design Tool can be used to optimize PLL phase noise/jitter for
given specifications. See: http://www.ti.com/tool/clockdesigntool/.
PLL 1 Loop Filter
Table 4: PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO
122.88 MHz VCXO PLL
Phase Margin
49˚
Kφ (Charge Pump)
100 uA
Loop Bandwidth 12 Hz Phase Detector Freq 1.024 MHz
VCO Gain
2.5 kHz/Volt
Reference Clock
Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2)
Loop Filter
Components C1_A1 = 100 nF C2_A1 = 680 nF R2_A1 = 39 kΩ
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand
N will change the loop bandwidth.
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PLL2 Loop Filter
Table 5: PLL2 Loop Filter Parameters for LMK048xxB
Integrated VCO PLL
LMK04803B
LMK04805B
LMK04806B
LMK04808B
C1_A2
0.047
nF
C2_A2
3.9
nF
C3 (internal)
0
nF
C4 (internal)
0
nF
R2_A2
0.62
kΩ
R3 (internal)
0.2
kΩ
R4 (internal)
0.2
kΩ
Charge Pump
Current, Kφ
3.2 mA
Phase Detector
Frequency
122.88 MHz
Frequency
1966.08
2211.84
2457.6
2949.12
MHz
Kvco
17.9
16.5
18.8
32.3
MHz/V
N
16
18
20
24
Phase Margin
75
75
75
76
degrees
Loop
Bandwidth
355 320 321 424 kHz
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand
N will change the loop bandwidth.
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Evaluation Board Inputs and Outputs
The following table contains descriptions of the inputs and outputs for the evaluation board. Unless
otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some
applicable CodeLoader programming controls are noted for convenience. Refer to the LMK04800 Family
Datasheet for complete register programming information.
Table 6: Evaluation Board Inputs and Outputs
Connector Name
Signal Type,
Input/Output
Description
Populated:
CLKout0, CLKout0*,
CLKout2, CLKout2*,
CLKout4, CLKout4*,
CLKout6, CLKout6*,
CLKout8, CLKout8*,
CLKout10, CLKout10*
Not Populated:
CLKout1, CLKout1*,
CLKout3, CLKout3*,
CLKout5, CLKout5*,
CLKout7, CLKout7*,
CLKout9, CLKout9*,
CLKout11, CLKout11*
Analog,
Output
Clock outputs with programmable output buffers.
The output terminations by default on the evaluation
board are shown below, and the output type selected by
default in CodeLoader is indicated by an asterisk (*):
Clock output pair
Default Board
Termination
CLKout0
LVPECL*
CLKout1
LVPECL
CLKout2
LVPECL*
CLKout3
LVPECL
CLKout4
LVDS* / LVCMOS
CLKout5
LVDS / LVCMOS
CLKout6
LVDS* / LVCMOS
CLKout7
LVDS / LVCMOS
CLKout8
LVDS* / LVCMOS
CLKout9
LVDS / LVCMOS
CLKout10
LVPECL*
CLKout11
LVPECL
Each CLKout pair has a programmable LVDS,
LVPECL, or LVCMOS buffer. The output buffer type
can be selected in CodeLoader in the Clock Outputs
tab via the CLKoutX_TYPE control.
All clock outputs are AC-coupled to allow safe testing
with RF test equipment.
All LVPECL clock outputs are source-terminated using
240-ohm resistors.
If an output pair is programmed to LVCMOS, each
output can be independently configured (normal,
inverted, or off/tri-state).
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Connector Name
Signal Type,
Input/Output
Description
Populated:
OSCout0, OSCout0*,
OSCout1, OSCout1*
Analog,
Output
Buffered outputs of OSCin port.
The output terminations on the evaluation board are
shown below, the output type selected by default in
CodeLoader is indicated by an asterisk (*):
OSC output pair
Default Board
Termination
OSCout0
LVDS* / LVCMOS
OSCout1
LVPECL* (fixed)
Only OSCout0 has a programmable LVDS, LVPECL,
or LVCMOS output buffer. The OSCout0 buffer type
can be selected in CodeLoader on the Clock Outputs
tab via the OSCout0_TYPE control. OSCout1 has
LVPECL buffer only but has programmable swing
amplitude.
Both OSCout pairs are AC-coupled to allow safe
testing with RF test equipment.
The OSCout1 output is source-terminated using 240-
ohm resistors.
If OSCout0 is programmed as LVCMOS, each output
can be independently configured (normal, inverted,
inverted, and off/tri-state).
Vcc Power,
Input
Main power supply input for the evaluation board.
A 3.9 V DC power source applied to this SMA will, by
default, source the onboard LDO regulators that power
the inner layer planes that supply the LMK048xxB and
its auxiliary circuits (e.g. VCXO).
The LMK048xxB contains internal voltage regulators
for the VCO, PLL and other internal blocks. The clock
outputs do not have an internal regulator, so a clean
power supply with sufficient output current capability
is required for optimal performance.
On-board LDO regulators and 0 Ωresistor options
provide flexibility to supply and route power to various
devices. See schematics for more details.
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Connector Name
Signal Type,
Input/Output
Description
Populated:
J1 Power, Input
Alternative power supply input for the evaluation board
using two unshielded wires (Vcc and GND).
Apply power to either Vcc SMA or J1, but not both.
Populated:
VccVCO/Aux Power, Input
Optional Vcc input to power the VCO circuit if
separated voltage rails are needed. The VccVCO/Aux
input can power these circuits directly or supply the on-
board LDO regulators. 0 Ω resistor options provide
flexibility to route power.
Populated:
VccVCXO/Aux Power, Input
Optional Vcc input to power the VCXO circuit if
separated voltage rails are needed. The
VccVCXO/Aux input can power these circuits directly
or supply the on-board LDO regulators. 0 Ω resistor
options provide flexibility to route power.
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Connector Name
Signal Type,
Input/Output
Description
Populated:
CLKin0, CLKin0*,
FBCLKin*/CLKin1*
Not Populated:
FBCLKin/CLKin1
Analog,
Input
Reference Clock Inputs for PLL1 (CLKin0, 1).
CLKin1 can alternatively be used as an External
Feedback Clock Input (FBCLKin) in 0-delay mode or
an RF Input (Fin) in External VCO mode.
Reference Clock Inputs for PLL1 (CLKin0, 1)
FBCLKin/CLKin1* is configured by default for a
single-ended reference clock input from a 50-ohm
source. The non-driven input pin (FBCLKin/CLKin1)
is connected to GND with a 0.1 uF. CLKin0/CLKin0*
is configured by default for a differential reference
clock input from a 50-ohm source.
CLKin1* is the default reference clock input selected in
CodeLoader. The clock input selection mode can be
programmed on the Bits/Pins tab via the
CLKin_Select_MODE control. Refer to the
LMK04800 Family Datasheet section “Input Clock
Switching” for more information.
AC coupled Input Clock Swing Levels
Input
Mode
Min
Max
Units
Differential
Bipolar or
CMOS
0.5
3.1
Vpp
Single Ended
0.25
2.4
Vpp
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external
feedback clock input to PLL1 for 0-delay mode. See
section, Programming 0-Delay Mode in CodeLoader
below, for more details on using 0-delay mode with the
evaluation board and the evaluation board software.
RF Input (Fin) for External VCO
CLKin1 is also shared for use with Fin as an RF input
for external VCO mode using the onboard VCO
footprint (U3) or add-on VCO board. To enable Dual
PLL mode with External VCO, the following registers
must be properly configured in CodeLoader:
•MODE = (3) Dual PLL, Ext VCO (Fin), (5)
Dual PLL, Ext VCO, 0-Delay, (11) PLL2, Ext
VCO (Fin)
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Connector Name
Signal Type,
Input/Output
Description
Not populated:
OSCin, OSCin* Analog, Input
Feedback VCXO clock input to PLL1 and Reference
clock input to PLL2.
By default, these SMAs are not connected to the traces
going to the OSCin/OSCin* pins of the LMK048xxB.
Instead, the single-ended output of the onboard VCXO
(U2) drives the OSCin* input of the device and the
OSCin input of the device is connected to GND with
0.1 uF.
A VCXO add-on board may be optionally attached via
these SMA connectors with minor modification to the
components going to the OSCin/OSCin* pins of
device. This is useful if the VCXO footprint does not
accommodate the desired VCXO device.
A single-ended or differential signal may be used to
drive the OSCin/OSCin* pins and must be AC coupled
.
If operated in single-ended mode, the unused input
must be connected to GND with 0.1 uF.
Refer to the LMK04800 Family Datasheet section
“Electrical Characteristics” for PLL2 Reference Input
(OSCin) specifications.
Test point:
VTUNE1_TP
Not populated:
Vtune1
Analog,
Output
Tuning voltage output from the loop filter for PLL1.
If a VCXO add-on board is used, this tuning voltage
can be connected to the voltage control pin of the
external VCXO when this SMA connector is installed
and connected through R72 by the user.
Test point:
VTUNE2_TP
Analog,
Output
Tuning voltage output from the loop filter for PLL2.
Populated:
uWire
Test points:
DATAuWire_TP
CLKuWIRE_TP
LEuWIRE_TP
CMOS,
Input/Output
10-pin header for uWire programming interface and
programmable logic I/O pins for the LMK048xxB.
The uWire interface includes CLKuWire,
DATAuWire, and LEuWire signals.
The programmable logic I/O signals accessible through
this header include: SYNC, Status_Holdover,
Status_LD, Status_CLKin0, and Status_CLKin1.
These logic I/O signals also have dedicated SMAs and
test points.
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Revised - August 2014 LMK04800 Family SNAU076B 19
Copyright © 2014, Texas Instruments Incorporated
www.ti.com
Connector Name
Signal Type,
Input/Output
Description
Test point:
LD_TP
Not populated:
Status_LD
CMOS,
Output
Programmable status output pin. By default, set to
output the digital lock detect status signal for PLL1 and
PLL2 combined.
In the default CodeLoader modes, LED D5 will
illuminate green when PLL lock is detected by the
LMK048xxB (output is high) and turn off when lock is
lost (output is low).
The status output signal for the Status_LD pin can be
selected on the Bits/Pins tab via the LD_MUX control.
Refer to the LMK04800 Family Datasheet section
“Status Pins” and “Digital Lock Detect” for more
information.
Note: Before a high-frequency internal signal (e.g. PLL
divider output signal) is selected by LD_MUX, it is
suggested to first remove the 270 ohm resistor to
prevent the LED from loading the output.
Test point:
Holdover_TP
Not populated:
Status_Hold
CMOS,
Output
Programmable status output pin. By default, set to the
output holdover mode status signal.
In the default CodeLoader mode, LED D8 will
illuminate red when holdover mode is active (output is
high) and turn off when holdover mode is not active
(output is low).
The status output signal for the Status_Holdover pin
can be selected on the Bits/Pins tab via the
HOLDOVER_MUX control.
Refer to the LMK04800 Family Datasheet section
“Status Pins” and “Holdover Mode” for more
information.
Note: Before a high-frequency internal signal (e.g. PLL
divider output signal) is selected by
HOLDOVER_MUX, it is suggested to first remove the
270 ohm resistor to prevent the LED from loading the
output.
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20 SNAU076B LMK04800 Family Revised - August 2014
Copyright © 2014, Texas Instruments Incorporated
www.ti.com
Connector Name
Signal Type,
Input/Output
Description
Test point:
CLKin0_SEL_TP
CLKin1_SEL_TP
Not populated:
Status_CLKin0,
Status_CLKin1
CMOS,
Input/Output
Programmable status I/O pins. By default, set as input
pins for controlling input clock switching of CLKin0
and CLKin1.
These inputs will not be functional because
CLKin_Select_MODE is set to 0 (CLKin0 Manual) by
default in the Bits/Pins tab in CodeLoader. To enable
input clock switching, CLKin_Select_MODE must be
3 or 6 and Status_CLKinX_TYPE must be 0 to 3 (pin
enabled as an input).
Input Clock Switching – Pin Select Mode
When CLKin_SELECT_MODE is 3, the
Status_CLKinX pins select which clock input is active
as follows:
Status_CLKin1
Status_CLKin0
Active Clock
0
0
CLKin0
0
1
CLKin1
1
0
Reserved
1
1
Holdover
Input Clock Switching – Auto with Pin Select
When CLKin_SELECT_MODE is 6, the active clock is
selected using the Status_CLKinX pins upon an input
clock switch event as follows:
Status_CLKin1 Status_CLKin0
Active
Clock
X
0
CLKin0
1
0
CLKin1
0
0
Reserved
Refer to the LMK04800 Family Datasheet section
“Input Clock Switching” for more information.
Status Outputs
When Status_CLKinX_TYPE is 3 to 6 (pin enabled as
an output), the status output signal for the
corresponding Status_CLKinX pin can be programmed
on the Bits/Pins tab via the Status_CLKinX_MUX
control.
Refer to the LMK04800 Family Datasheet section
“Status Pins” for more information.
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