Texas Instruments ADS9218EVM-PDK User manual

User’s Guide
ADS9218EVM-PDK Evaluation Module
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS9218EVM-PDK evaluation module
(EVM) performance demonstration kit (PDK). This kit is an evaluation platform for the ADS9218, which is an
18-bit, 10-MSPS, fully differential input, successive approximation register (SAR) analog-to-digital converter
(ADC) that features a low-voltage differential signaling (LVDS) digital interface. The EVM-PDK also includes
an adapter printed circuit board (PCB) that facilitates connection to a standard FPGA mezzanine card (FMC)
connecter used in many field-programmable gate array (FPGA) kits. The EVM-PDK eases the evaluation of the
ADS9218 device with hardware, software, and computer connectivity through the universal serial bus (USB)
interface. This user's guide includes complete circuit descriptions, schematic diagrams, and a bill of materials
(BOM). Throughout this document, the terms demonstration kit, evaluation board, evaluation module, EVM, and
EVM-PDK are synonymous with the ADS9218EVM-PDK.
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Table of Contents
1 Overview..................................................................................................................................................................................3
1.1 ADS9218EVM-PDK Features............................................................................................................................................ 3
1.2 ADS9218EVM Features.....................................................................................................................................................4
2 Analog Interface......................................................................................................................................................................5
2.1 ADS9218 Device Connections...........................................................................................................................................5
2.2 ADC Differential Input Fully Differential Amplifier (FDA).................................................................................................... 6
2.3 Common Mode Amplifier Drive.......................................................................................................................................... 7
2.4 Voltage Reference..............................................................................................................................................................7
3 Digital Interface.......................................................................................................................................................................8
3.1 Clock Connection............................................................................................................................................................... 9
4 Power Supplies..................................................................................................................................................................... 10
5 ADS9218EVM Software Installation.....................................................................................................................................11
6 EVM Operation...................................................................................................................................................................... 13
6.1 Connecting the Hardware and Starting Software.............................................................................................................13
6.2 Optional Connections to the EVM.................................................................................................................................... 15
6.3 Initial Required Setup on the Config Tab..........................................................................................................................16
6.4 Initial Required Setup on the Capture Tab....................................................................................................................... 17
7 Bill of Materials, Schematics, and Layout.......................................................................................................................... 18
7.1 Bill of Materials (BOM)..................................................................................................................................................... 18
7.2 Schematics.......................................................................................................................................................................20
7.3 Layout.............................................................................................................................................................................. 23
List of Figures
Figure 1-1. System Using GUI and TSWDC155EVM..................................................................................................................3
Figure 1-2. System Using FMC to VITA57 and FPGA Kit............................................................................................................4
Figure 1-3. ADS9218EVM Block Diagram...................................................................................................................................4
Figure 2-1. Connections to ADS9218.......................................................................................................................................... 5
Figure 2-2. FDA Driver Schematic...............................................................................................................................................6
Figure 2-3. Common-Mode Amplifier Drive................................................................................................................................. 7
Figure 2-4. Voltage Reference.....................................................................................................................................................7
Figure 3-1. FMC Connector Signals Definition............................................................................................................................ 8
Figure 3-2. Clock Connection...................................................................................................................................................... 9
Figure 4-1. Boost Converter, LDO, and Input Polarity Protection.............................................................................................. 10
Figure 5-1. Initial Software Installation.......................................................................................................................................11
Figure 5-2. Installation Process................................................................................................................................................. 12
Figure 6-1. Connecting the Hardware........................................................................................................................................13
Figure 6-2. Start the Software GUI............................................................................................................................................ 14
Figure 6-3. Optional Connections.............................................................................................................................................. 15
Figure 6-4. Initial Required Setup on the Config Tab.................................................................................................................16
Figure 6-5. Initial Required Setup on the Capture Tab.............................................................................................................. 17
Figure 7-1. ADS9218EVM ADC Connections, Amplifiers, and Reference Schematic.............................................................. 20
Figure 7-2. ADS9218EVM Power Section................................................................................................................................. 21
Figure 7-3. ADS9218EVM Connector to TSWDC155EVM........................................................................................................22
Figure 7-4. ADS9218EVM Layout............................................................................................................................................. 23
List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 3
Table 7-1. Bill of Materials..........................................................................................................................................................18
Trademarks
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
All trademarks are the property of their respective owners.
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1 Overview
The ADS9218EVM-PDK is a platform for evaluating the performance of the ADS9218 SAR ADC, which is a
fully differential input, 18-bit, 10-MSPS device. The evaluation kit includes the ADS9218EVM board and an
FMC connecter adapter board used to interface the ADC with many FPGA kits. The TSWDC155EVM (sold
separately) is a digital controller board that can be used with this evaluation kit and the EVM software GUI to
communicate with the device, graph measured results, and compute common figures of merit (such as SNR and
THD).
The following related documents are available for download through the Texas Instruments web site at
www.ti.com.
Table 1-1. Related Documentation
Device Literature Number
THS4552 SBOS831
REF7040 SNAS781
TPS61070 SLVS510
TPS7A20 SBVS338
LM66100 SLVSEZ8
1.1 ADS9218EVM-PDK Features
The ADS9218EVM-PDK includes the following features:
• Hardware and software required for diagnostic testing and accurate performance evaluation of the ADS9218
ADC
• The FMC connecter adapter board facilitates connection to common FPGA kits
• The TSWDC155EVM controller (sold separately) requires a separate 5-V, 2-A power source; the
ADS9218EVM requires a separate 5.5-V, 1-A power source
• The TSWDC155EVM controller (sold separately) provides a convenient communication interface to the
ADS9218 ADC over USB 3.0 (or higher) for power delivery and for digital inputs and outputs
• Easy-to-use evaluation software (no cost) for Microsoft® Windows® 10, 64-bit operating systems requires the
TSWDC155EVM (sold separately) for operation
• The software suite (no cost) includes graphical tools for data capture, histogram analysis, spectral analysis,
SNR, and THD
Figure 1-1 and Figure 1-2 illustrate two different system configurations available for use.
Signal
Source
Included in kit
ADS9218EVM
TSWDC155EVM
ADS9218
GUI
Signal
Source
Sold Separately
from Texas
Instruments
5.2V to 5.5V
DC power
SMI18-5-V-P5
5V DC wall supply
Figure 1-1. System Using GUI and TSWDC155EVM
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Signal
Source
Included in kit
ADS9218EVM FMCtoVITA57
Signal
Source
Not provided
by Texas
Instruments
Your custom
so

ware
FPGA Kit
5.2V to 5.5V
DC power
Figure 1-2. System Using FMC to VITA57 and FPGA Kit
1.2 ADS9218EVM Features
The ADS9218EVM includes the following features:
• Onboard low-noise and low-distortion ADC input drivers optimized to meet ADC performance
• Onboard precision 4.096-V voltage reference onboard ultra-low noise low-dropout (LDO) regulators for 5.0-V
analog supply and 1.8 V for the digital supply
• Subminiature version A (SMA) connections for external clock or clock provided via FMC connector
Figure 1-3 shows a block diagram for the ADS9218EVM.
Voltage
reference
Power
Clock
SMA
SMA
Ref
SMA SMA
SMA
SMA
External
Sampling
Clock
Clock
ADS9218
FMC connector
Power
Figure 1-3. ADS9218EVM Block Diagram
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2 Analog Interface
As an analog interface, the evaluation board uses fully differential amplifiers (FDAs) to drive the ADS9218 input
signals. The ADS9218 includes an integrated voltage reference, but an external reference can be used and is
jumper selectable on the hardware. This section covers driver details, including jumper configuration for different
input signal options.
2.1 ADS9218 Device Connections
The digital communications lines for the ADC (shown in Figure 2-1) all follow the low-voltage differential
signaling (LVDS) standard and are connected with optional termination resistors. A digital serial peripheral
interface (SPI) port is used to configure registers in the device. The SDO output line includes a termination.
AVDD_1V8
13
AVDD_1V8
37
AVDD_5V
1
AVDD_5V
10
DVDD_1V8
14
DVDD_1V8
35
DVDD_1V8
36
AINP_A
3
AINP_B
7
AINM_A
4
AINM_B
8
REFM 6
REFM 11
REFM 40
DOUTM_A 27
DOUTM_B 25
DOUTP_A 28
DOUTP_B 26
CS
17
PWDN
22 RESET
21
DCLKIN
31
DCLKM 23
DCLKP 24
FCLKM 29
FCLKP 30
REFIO 39
SCLK
18
SDI
19
SDO
20
SMPL_CLK
32
SPI_EN
16
SYNC 33
Thermal_Pad 41
VCMOUT
5
AGND 2
AGND 9
AGND 12
AGND 38
DGND 15
DGND 34
ADS9227IRHAT
U1
GND
NT1
Net-Tie
GND
REFIO
10V
1µF
C22
GND
1V8_VDD5V
10V
1µF
C19
10V
0.1µF
C20
10V
0.1µF
C21
GNDGNDGND
PWDNz PWDNz
RESETz RESETz
SMPL_SYNC SMPL_SYNC
SMPL_CLKP SMPL_CLKP
SPI_EN
CSz
SCLK
SDI
SDO 33
R22
10V
0.1µF
C16
GND
10V
1µF
C15
GND
1V8_VDD
10V
0.1µF
C23
GND
DOUTP_A
DOUTP_A
DOUTM_A DOUTM_A
DCLKP DCLKP
DCLKM
DCLKM
FCLKP FCLKP
FCLKM
FCLKM
DOUTP_B DOUTP_B
DOUTM_B
DOUTM_B
SCLK
SDI
SPI_EN
CSz
SDO
SMPL_CLKM
100
R26
DNP
DOUTP_A
DOUTM_A
100
R27
DNP
DOUTP_B
DOUTM_B
100
R28
DNP
DCLKP
DCLKM
100
R29
DNP
FCLKP
FCLKM
AINP_A AINP_A
AINM_A AINM_A
AINP_B AINP_B
AINM_B AINM_B
VCMOUT VCMOUT
REFIO
EXT_SMPL_CLKM
20.0R9
20.0
R12
20.0
R20
20.0R24
Figure 2-1. Connections to ADS9218
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2.2 ADC Differential Input Fully Differential Amplifier (FDA)
The THS4552 FDA is used to amplify the input signals applied to the SMA connector. The amplifier is a dual
configuration for the two different ADC channels. Each channel is configured with the same discreet feedback
components. The amplifier gain is set to 1 V/V and the bandwidth is set to 500 kHz for good performance up to
100 kHz. The ADS9218 Power Optimized Signal Chain Circuit reference design covers component selection and
can help adjust component values for different optimizations.
Figure 2-2 shows a schematic of the FDA driver components.
GND
1
2
3
4
5
J3
GND
1
2 3 4 5
J4
GND
GND
AINP_A
AINM_A
10V
0.1µF
C10
5V
GND
25V
1000pF
C33
DNP
GND
GND
VCM_FDA
1.00k
R7
1.00k
R10
10.0
R6
10.0
R13
24.9
R8
24.9
R11
49.9
R32
DNP
49.9
R30
DNP
GND
50V
47pF
C11
50V
47pF
C13
100V
470pF
C12
3
1
2
VOCM1
4
14
15
V+
V-
1316
THS4552IPWR
U6A
1.00k
R5
1.00k
R14
50V
270pF
C9
50V
270pF
C14
Figure 2-2. FDA Driver Schematic
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2.3 Common Mode Amplifier Drive
The ADS9218 has a common-mode output pin (VCMOUT). The common-mode signal must be buffered to drive
the THS4552 common-mode input pin. Figure 2-3 shows an example of the buffer circuit. R35 bypasses the
amplifier and is not populated. When R35 is populated, U8 is unpopulated so that the ADC VCMOUT pin directly
drives the FDA VCM input.
10V
0.1µF
C17
GND 5V
GND
VCMOUT
GND
10V
1uF
C24
VCM_FDA
1
2
3
4
5
OPA320AIDBVT
U8 402
R15
VCM
R35
VCMOUT
DNP
Figure 2-3. Common-Mode Amplifier Drive
2.4 Voltage Reference
As shown in Figure 2-4, the REF7040 is a very low-drift, low-noise, highly stable 4.096-V reference. This
reference can externally drive the REFIO pin of the ADS9218 by installing jumper J10. Alternatively, J10 can be
removed and the ADS9218 can use the internal voltage reference.
VIN
2
EN
1
OUTF 7
OUTS 6
GND 3
GND 4
GND 5
GND 8
REF7040QFKHT
U9
10V
0.1µF
C30
GND
5V
GND
10V
10uF
C31
GND
1 2
J10
REFIO
Figure 2-4. Voltage Reference
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3 Digital Interface
The ADS9218 uses an SPI interface to configure the registers (SCLK, SDI, SDO, CS, and SPI_EN).
The ADS9218 uses two LVDS interfaces for capturing conversion data for each ADC channel (DOUTP_A,
DOUTM_A, DOUTP_B, and DOUTM_B). The SPI and LVDS signals connect to the FMC connector. The FMC
connector signal definition is given in Figure 3-1. These signals are also available on tented via test points for
scope measurements. Top overlay text indicates the location of these test points.
SDI
SCLK
CSz
SDO
D3
D2
D1
D0
FCLKOUT
DCLKOUT
FX3_I2C_SCL
FX3_I2C_SDA
SPI_EN
PWDNz
SPRW_SUP_3P3
SPRW_SUP_3P3
SPRW_SUP_2P5
SPRW_SUP_2P5
SPRW_SUP_1P8
SPRW_SUP_1P8
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A10
A11
A11
A12
A12
A13
A13
A14
A14
A15
A15
A16
A16
A17
A17
A18
A18
A19
A19
A20
A20
A21
A21
A22
A22
A23
A23
A24
A24
A25
A25
A26
A26
A27
A27
A28
A28
A29
A29
A30
A30
A31
A31
A32
A32
A33
A33
A34
A34
A35
A35
A36
A36
A37
A37
A38
A38
A39
A39
A40
A40
J27A
ASP-134486-01
B1
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
B10
B10
B11
B11
B12
B12
B13
B13
B14
B14
B15
B15
B16
B16
B17
B17
B18
B18
B19
B19
B20
B20
B21
B21
B22
B22
B23
B23
B24
B24
B25
B25
B26
B26
B27
B27
B28
B28
B29
B29
B30
B30
B31
B31
B32
B32
B33
B33
B34
B34
B35
B35
B36
B36
B37
B37
B38
B38
B39
B39
B40
B40
J27B
ASP-134486-01
C1
C1
C2
C2
C3
C3
C4
C4
C5
C5
C6
C6
C7
C7
C8
C8
C9
C9
C10
C10
C11
C11
C12
C12
C13
C13
C14
C14
C15
C15
C16
C16
C17
C17
C18
C18
C19
C19
C20
C20
C21
C21
C22
C22
C23
C23
C24
C24
C25
C25
C26
C26
C27
C27
C28
C28
C29
C29
C30
C30
C31
C31
C32
C32
C33
C33
C34
C34
C35
C35
C36
C36
C37
C37
C38
C38
C39
C39
C40
C40
J27C
ASP-134486-01
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
D16
D16
D17
D17
D18
D18
D19
D19
D20
D20
D21
D21
D22
D22
D23
D23
D24
D24
D25
D25
D26
D26
D27
D27
D28
D28
D29
D29
D30
D30
D31
D31
D32
D32
D33
D33
D34
D34
D35
D35
D36
D36
D37
D37
D38
D38
D39
D39
D40
D40
J27D
ASP-134486-01
E1
E1
E2
E2
E3
E3
E4
E4
E5
E5
E6
E6
E7
E7
E8
E8
E9
E9
E10
E10
E11
E11
E12
E12
E13
E13
E14
E14
E15
E15
E16
E16
E17
E17
E18
E18
E19
E19
E20
E20
E21
E21
E22
E22
E23
E23
E24
E24
E25
E25
E26
E26
E27
E27
E28
E28
E29
E29
E30
E30
E31
E31
E32
E32
E33
E33
E34
E34
E35
E35
E36
E36
E37
E37
E38
E38
E39
E39
E40
E40
J27E
ASP-134486-01
F1
F1
F2
F2
F3
F3
F4
F4
F5
F5
F6
F6
F7
F7
F8
F8
F9
F9
F10
F10
F11
F11
F12
F12
F13
F13
F14
F14
F15
F15
F16
F16
F17
F17
F18
F18
F19
F19
F20
F20
F21
F21
F22
F22
F23
F23
F24
F24
F25
F25
F26
F26
F27
F27
F28
F28
F29
F29
F30
F30
F31
F31
F32
F32
F33
F33
F34
F34
F35
F35
F36
F36
F37
F37
F38
F38
F39
F39
F40
F40
J27F
ASP-134486-01
G1
G1
G2
G2
G3
G3
G4
G4
G5
G5
G6
G6
G7
G7
G8
G8
G9
G9
G10
G10
G11
G11
G12
G12
G13
G13
G14
G14
G15
G15
G16
G16
G17
G17
G18
G18
G19
G19
G20
G20
G21
G21
G22
G22
G23
G23
G24
G24
G25
G25
G26
G26
G27
G27
G28
G28
G29
G29
G30
G30
G31
G31
G32
G32
G33
G33
G34
G34
G35
G35
G36
G36
G37
G37
G38
G38
G39
G39
G40
G40
J27G
ASP-134486-01
H1
H1
H2
H2
H3
H3
H4
H4
H5
H5
H6
H6
H7
H7
H8
H8
H9
H9
H10
H10
H11
H11
H12
H12
H13
H13
H14
H14
H15
H15
H16
H16
H17
H17
H18
H18
H19
H19
H20
H20
H21
H21
H22
H22
H23
H23
H24
H24
H25
H25
H26
H26
H27
H27
H28
H28
H29
H29
H30
H30
H31
H31
H32
H32
H33
H33
H34
H34
H35
H35
H36
H36
H37
H37
H38
H38
H39
H39
H40
H40
J27H
ASP-134486-01
J1
J1
J2
J2
J3
J3
J4
J4
J5
J5
J6
J6
J7
J7
J8
J8
J9
J9
J10
J10
J11
J11
J12
J12
J13
J13
J14
J14
J15
J15
J16
J16
J17
J17
J18
J18
J19
J19
J20
J20
J21
J21
J22
J22
J23
J23
J24
J24
J25
J25
J26
J26
J27
J27
J28
J28
J29
J29
J30
J30
J31
J31
J32
J32
J33
J33
J34
J34
J35
J35
J36
J36
J37
J37
J38
J38
J39
J39
J40
J40
J27I
ASP-134486-01
K1
K1
K2
K2
K3
K3
K4
K4
K5
K5
K6
K6
K7
K7
K8
K8
K9
K9
K10
K10
K11
K11
K12
K12
K13
K13
K14
K14
K15
K15
K16
K16
K17
K17
K18
K18
K19
K19
K20
K20
K21
K21
K22
K22
K23
K23
K24
K24
K25
K25
K26
K26
K27
K27
K28
K28
K29
K29
K30
K30
K31
K31
K32
K32
K33
K33
K34
K34
K35
K35
K36
K36
K37
K37
K38
K38
K39
K39
K40
K40
J27J
ASP-134486-01
SMPL_SYNC
GND GND GND GND GND
GNDGNDGNDGNDGND
DCLKP
DCLKM
FCLKP
FCLKM
DOUTP_A
DOUTM_A
DOUTP_B
DOUTM_B
RESETz
FPGA_SMPL_CLKP
Figure 3-1. FMC Connector Signals Definition
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3.1 Clock Connection
The EVM allows for an external differential clock, an external single-ended clock, or a clock signal from
the TSWDC155EVM controller card. Jumper J11 selects either the external clock or a clock from the
TSWDC155EVM. J5 grounds the negative clock if a single-ended clock is applied. Figure 3-2 shows the clock
connection circuit.
GND
GND
1
2
J5
1
2
3 4 5
J1
GND
1
2
3 4 5
J2
EXT_SMPL_CLKP
EXT_SMPL_CLKM
49.9
R4
DNP
1
2
3
J11
SMPL_CLKP
EXT_SMPL_CLKP
FPGA_SMPL_CLKP
Figure 3-2. Clock Connection
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4 Power Supplies
The TSWDC155EVM can provide power using the 3.3-V supply, but is not enabled by default on the
TSWDC155EVM. Typical use requires external power on J17. The TSWDC155EVM provides the ADS9218EVM
with a 3.3-V supply. The ADS9218EVM has a TPS61070 boost converter that boosts the 3.3-V supply to 5.4
V. This voltage is applied to low-dropout regulators (LDOs) to derive the AVDD and the DVDD supply. The
TPS7A2050 provides the 5-V AVDD supply and the TPS7A2018 provides the 1.8-V DVDD supply. The required
power connection is made through jumper J18 can be set to allow external power to be applied on screw
terminal J17. In this case U2, an LM66100 device, provides reverse polarity protection if the connection is
miswired. Figure 4-1 shows a schematic for various protection circuits.
1
2
J17
GND
OUT 5
GND 2
IN
1
EN
3
NC
4
TPS7A2050PDBVR
U3
5V
GND
1µF
16V
C1
1µF
16V
C2
GND GND
IN
1
GND
2
CE
3 N/C 4
ST 5
OUT 6
LM66100DCKR
U2
GND
1V8_VDD
GND
1µF
16V
C3
1µF
16V
C4
GND GND
AVDD
VDD
EN
3
IN
1
NC
4
OUT 5
GND 2
TPS7A2018PDBVR
U4
SW 1
GND
2
EN
3
FB 4
VOUT 5
VBAT
6
TPS61070DDCR
U5
10uH
L1
GND
16V
10uF
C5
GND
1.96M
R2
200k
R3
GND GND
SPRW_SUP_3P3
LDO_IN
6V
D1
GND
1
2
3
J18
10V
1µF
C32
GND
16V
10uF
C6
2.2k
R1
Green
12
D2
GND
Figure 4-1. Boost Converter, LDO, and Input Polarity Protection
Power Supplies www.ti.com
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5 ADS9218EVM Software Installation
This section covers the installation and operation of the ADS9218EVM software graphical user interface (GUI).
This software requires the TSWDC155EVM (sold separately) controller to operate. The fist steps to installing
the software (as shown in Figure 5-1) is to download the latest version of the EVM GUI installer from the
Tools and Software folder of the ADS9218EVM, and run the GUI installer to install the EVM GUI software on
your computer. Accept all the license agreements and choose the destination location, project directory, and
start menu. Typically, the default values work, but you can customize these values as needed based on your
requirements.
Figure 5-1. Initial Software Installation
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Next, the installer prompts you to create a desktop icon and summarize the installation plan. Pressing Install
begins copying software onto your computer. This process takes a few minutes. At completion, you can launch a
readme text file and the application. Figure 5-2 shows these steps.
Figure 5-2. Installation Process
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6 EVM Operation
6.1 Connecting the Hardware and Starting Software
1. After installing the software, connect the EVM and set jumpers as shown in Figure 6-1.
2. Connect a 5-V wall-wart connector or other power source for the TSWDC155EVM (sold separately). The
TSWDC155EVM user guide provides information on this power source.
3. Physically connect J1 of the TSWDC155EVM to J27 of the ADS9218EVM. This component is the digital
communications and power signal connection.
4. Connect the USB on the TSWDC155EVM to the computer.
5. Set jumper J18 to the FMC_PWR position to allow for an external power connection. Connect an external
5.2-V to 5.5-V supply on screw terminal connection J17.
6. Start the software GUI as described in Figure 6-2.
7. Press the buttons (Initialize USB, Power Up, Program FPGA, and Initialize ads98xx) on the Config tab to
power up and configure the EVM (see Figure 6-4 for details).
8. Connect a differential signal generator. The maximum input range is ±3.2 V, and the common-mode input is
2.048 V.
9. Press the EN SYNC button on the Capture tab. Select the number of samples to be at least 32k, and choose
the Hanning window type for best frequency domain results. Press the Start Capture button to collect and
analyze the data; see Figure 6-5.
ADS9218EVM
(MED1613E2)
J13: 5V, 3A, 15W power adapter
( or Bench supply)
TSWDC155
(DC155A)
J5, J6, J29, J33
J8: USB- C to USB- A cable
J17: 5.3V- 5.5V, 1A, Bench supply
J5, J11, J18
Figure 6-1. Connecting the Hardware
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Select the GUI from
the start menu
Figure 6-2. Start the Software GUI
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6.2 Optional Connections to the EVM
Figure 6-3 shows optional connections to the clock. These connections are not required for initial setup of the
EVM but can be helpful to configure the EVM more closely to your end application. Review the Schematic to
understand how these connections are used.
Clock Source
Figure 6-3. Optional Connections
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6.3 Initial Required Setup on the Config Tab
After the EVM GUI is started, you must press some buttons (Initialize USB, Power Up, Program FPGA, and
Initialize ADS98xx) to perform the initial configurations. As shown in Figure 6-4, press these buttons in order
from top to bottom. Wait after each button press for the status to indicate that the step is complete. For the
Power Up and Program FPGA buttons, some status LEDs on the hardware illuminate. The power-up step takes
the longest time (approximately 30 seconds). After all four buttons are pressed, the power on the ADS9218EVM
is on and the ADS9218 device registers are configured.
Press the bu  ons circled below.
Wait a  er each bu  on press for
the status to indicate that the
step is complete.
Figure 6-4. Initial Required Setup on the Config Tab
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6.4 Initial Required Setup on the Capture Tab
In Figure 6-5, the device and EVM are powered up and configured. In this step, the necessary updates to the
Capture settings are made to capture the time domain data and to get a good frequency domain result. First, the
EN SYNC button is pressed to synchronize the communication channel. Next, update the number of samples to
at least 32k to get good frequency domain results (for example, accurate FFT display, SNR data, and THD data).
Finally, select the Hanning type window to eliminate spectral leakage in the FFT result.
When these changes are made, press the Start Capture button to collect time domain and frequency domain
data. To view data for channel 1 or channel 2, select the appropriate tab.
1. Press “EN SYNC”
3. Change window type to
“Hanning”
2. Choose at least 32k samples
for good FFT results.
4. Press “Start Capture” to
collect data
5. Choose the channel you
want to observe
Figure 6-5. Initial Required Setup on the Capture Tab
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7 Bill of Materials, Schematics, and Layout
7.1 Bill of Materials (BOM)
Table 7-1 lists the BOM for the ADS9218EVM-PDK.
Table 7-1. Bill of Materials
Designator Quantity Value Description Package
Reference
Part Number Manufacturer
!PCB1 1 Printed Circuit Board MED1613 Any
AVDD, VDD 2 Test Point, Compact, SMT Testpoint_Key
stone_Compa
ct
5016 Keystone
Electronics
C1, C2, C3, C4 4 1 uF CAP, CERM, 1 uF, 16 V, +/-
10%, X7R, 0603
0603 C1608X7R1C105K080
AC
TDK
C5, C6 2 10 uF CAP, CERM, 10 uF, 16 V, +/-
10%, X7R, 1206
1206 GRM31CR71C106KAC
7L
MuRata
C9, C14, C18, C29 4 270 pF CAP, CERM, 270 pF, 50 V, +/-
5%, C0G/NP0, 0603
0603 06035A271JAT2A AVX
C10, C16, C17, C20, C21,
C23, C25, C30
8 0.1 uF CAP, CERM, 0.1 µF, 10 V,+/-
10%, X7R, 0402
0402 C0402C104K8RACTU Kemet
C11, C13, C26, C28 4 47 pF CAP, CERM, 47 pF, 50 V, +/-
5%, C0G/NP0, 0603
0603 GRM1885C1H470JA01
D
MuRata
C12, C27 2 470 pF CAP, CERM, 470 pF, 100 V,
+/- 5%, C0G/NP0, 0603
0603 GRM1885C2A471JA01
D
MuRata
C15, C19, C22, C32 4 1 uF CAP, CERM, 1 µF, 10 V,+/-
10%, X7R, 0603
0603 0603ZC105KAT4A AVX
C24 1 1 uF CAP, CERM, 1 uF, 10 V, +/-
10%, X5R, 0603
0603 C0603C105K8PACTU Kemet
C31 1 10 uF CAP, CERM, 10 uF, 10 V, +/-
20%, X6S, 0603
0603 GRM188C81A106MA7
3D
MuRata
D1 1 6 V Diode, TVS, Bi, 6 V, SMB SMB SMBJ6.0CA Littelfuse
D2 1 Green LED, Green, SMD LED_0805 APT2012LZGCK Kingbright
H1, H2, H3, H4 4 Machine Screw, Round, #4-40
x 1/4, Nylon, Philips panhead
Screw NY PMS 440 0025 PH B&F Fastener
Supply
H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40
Nylon
Standoff 1902C Keystone
H9, H10, H11, H12 4 Bumpon, Hemisphere, 0.44 X
0.20, Clear
Transparent
Bumpon
SJ-5303 (CLEAR) 3M
J1, J2, J3, J4, J7, J8 6 SMA Connector Jack, Female
Socket 50Ohm Through Hole
Solder
CONN_SMA_
PTH
60312002114503 Wurth
Electronics
J5, J10 2 Header, 100mil, 2x1, Gold, TH Header,
100mil, 2x1,
TH
HTSW-102-07-G-S Samtec
J11, J18 2 Header, 100mil, 3x1, Gold, TH Header,
100mil, 3x1,
TH
HTSW-103-07-G-S Samtec
J17 1 Terminal Block, 3.5mm Pitch,
2x1, TH
7.0x8.2x6.5m
m
ED555/2DS On-Shore
Technology
J27 1 Socket, 1.27mm, 40x10,
Black, SMT
Connector,
1.27mm,
40x10, SMT
ASP-134486-01 Samtec
L1 1 10 uH Inductor, Wirewound,
Ceramic, 10 uH, 0.48 A, 0.36
ohm, SMD
2.5x1.8x1.8m
m
CBC2518T100M Taiyo Yuden
LBL1 1 Thermal Transfer Printable
Labels, 0.650" W x 0.200" H
- 10,000 per roll
PCB Label
0.650 x 0.200
inch
THT-14-423-10 Brady
Bill of Materials, Schematics, and Layout www.ti.com
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Table 7-1. Bill of Materials (continued)
Designator Quantity Value Description Package
Reference
Part Number Manufacturer
R1 1 2.2k RES, 2.2 k, 5%, 0.063 W,
0402
0402 CRCW04022K20JNED Vishay-Dale
R2 1 1.96Meg RES, 1.96 M, 1%, 0.063 W,
0402
0402 CRCW04021M96FKED Vishay-Dale
R3 1 200k RES, 200 k, 1%, 0.063 W,
0402
0402 CRCW0402200KFKED Vishay-Dale
R5, R7, R10, R14, R16,
R18, R21, R31
8 1.00k RES, 1.00 k, 0.1%, 0.1 W,
0603
0603 RT0603BRD071KL Yageo America
R6, R13, R17, R25 4 10.0 RES, 10.0, 0.1%, 0.1 W, 0603 0603 CRT0603-BY-10R0ELF Bourns
R8, R11, R19, R23 4 24.9 RES, 24.9, 0.1%, 0.1 W, 0603 0603 RT0603BRD0724R9L Yageo America
R9, R12, R20, R24 4 20.0 RES, 20.0, 0.1%, 0.1 W, 0603 0603 RT0603BRD0720RL Yageo America
R15 1 402 RES, 402, 1%, 0.063 W, 0402 0402 CRCW0402402RFKED Vishay-Dale
R22 1 33 RES, 33, 5%, 0.063 W, 0402 0402 CRCW040233R0JNED Vishay-Dale
R30, R32, R33, R34 0 49.9 RES, 49.9, 0.1%, 0.1 W, 0603 0603 RT0603BRD0749R9L Yageo America
R35 0 0 CRCW Series 0603 0.1 W 0
Ohm Jumper Surface Mount
Thick Film Chip Resistor
0603 CRCW06030000Z0EA
C
Vishay
U1 1 +/-6 V, Low IQ Ideal Diode
with Input Polarity Protection,
DCK0006A (SOT-SC70-6)
DCK0006A LM66100DCKR Texas
Instruments
U3 1 300-mA, ultra-low-noise, low-
IQ, low-dropout (LDO) linear
regulator with high PSRR 5-
SOT-23 -40 to 125
SOT23-5 TPS7A2050PDBVR Texas
Instruments
U4 1 Linear Voltage Regulator IC
Positive Fixed 1 Output 300
mA SOT-23-5
SOT23-5 TPS7A2018PDBVR Texas
Instruments
U5 1 Adjustable, 600-mA Switch,
90% Efficient PFM/PWM
Boost Converter in
ThinSOT-23, DDC0006A
(SOT-23-T-6)
DDC0006A TPS61070DDCR Texas
Instruments
U6 1 Low-Noise, Precision, 150-
MHz, Fully Differential
Amplifier, RTW0024A
(WQFN-24)
RTW0024A THS4552IRTWR Texas
Instruments
U8 1 Precision, 20 MHz, 0.9 pA
Ib, RRIO, CMOS Operational
Amplifier, 1.8 to 5.5 V, -40
to 125 degC, 5-pin SOT23
(DBV5), Green (RoHS & no
Sb/Br)
DBV0005A OPA320AIDBVT Texas
Instruments
U9 1 2 ppm/°C Maximum Drift, 0.23
ppmp-p 1/f Noise, Precision
Voltage Reference
LCCC8 REF7040QFKHT Texas
Instruments
C33, C34 0 1000 pF CAP, CERM, 1000 pF, 25 V,
+/- 10%, C0G/NP0, 0603
0603 C0603C102K3GACTU Kemet
FID1, FID2, FID3, FID4,
FID5, FID6
0 Fiducial mark. There is
nothing to buy or mount.
N/A N/A N/A
R4 0 49.9 RES, 49.9, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402 CRCW040249R9FKED Vishay-Dale
R26, R27, R28, R29 0 100 RES, 100, 1%, 0.063 W, 0402 0402 CRCW0402100RFKED Vishay-Dale
www.ti.com Bill of Materials, Schematics, and Layout
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7.2 Schematics
Figure 7-1 shows the amplifier drive circuit, voltage reference connections, common-mode amplifiers, external
clock connections, and ADC decoupling.
GND
1
2
3
4
5
J3
GND
1
2 3 4 5
J4
AVDD_1V8
13
AVDD_1V8
37
AVDD_5V
1
AVDD_5V
10
DVDD_1V8
14
DVDD_1V8
35
DVDD_1V8
36
AINP_A
3
AINP_B
7
AINM_A
4
AINM_B
8 REFM 6
REFM 11
REFM 40
DOUTM_A 27
DOUTM_B 25
DOUTP_A 28
DOUTP_B 26
CS
17
PWDN
22 RESET
21
SMPL_CLKM
31
DCLKM 23
DCLKP 24
FCLKM 29
FCLKP 30
REFIO 39
SCLK
18
SDI
19
SDO
20
SMPL_CLKP
32
SPI_EN
16
SYNC 33
Thermal_Pad 41
VCMOUT
5
AGND 2
AGND 9
AGND 12
AGND 38
DGND 15
DGND 34
ADS9227IRHAT
U1
GND
NT1
Net-Tie
GND
REFIO
10V
1µF
C22
GND
1V8_VDD5V
10V
1µF
C19
10V
0.1µF
C20
10V
0.1µF
C21
GNDGNDGND
SMPL_SYNC SMPL_SYNC
10V
0.1µF
C16
GND
10V
1µF
C15
GND
1V8_VDD
10V
0.1µF
C23
GND
DOUTP_A
DOUTP_A
DOUTM_A DOUTM_A
DCLKP DCLKP
DCLKM
DCLKM
FCLKP FCLKP
FCLKM
FCLKM
DOUTP_B DOUTP_B
DOUTM_B
DOUTM_B
100
R26
DNP
DOUTP_A
DOUTM_A
100
R27
DNP
DOUTP_B
DOUTM_B
100
R28
DNP
DCLKP
DCLKM
100
R29
DNP
FCLKP
FCLKM
GND
GND
GND
GND
1
2
J5
1
2
3 4 5
J1
GND
1
2
3
4
5
J2
EXT_SMPL_CLKP
EXT_SMPL_CLKM
49.9
R4
DNP
AINP_A AINP_A
AINM_A AINM_A
AINP_B AINP_B
AINM_B AINM_B
VCMOUT VCMOUT
AINP_A
AINM_A
10V
0.1µF
C17
GND 5V
GND
VCMOUT
GND
10V
1uF
C24
VCM_FDA
REFIO
1
2
3
J11
SMPL_CLKP
EXT_SMPL_CLKP
FPGA_SMPL_CLKP
VIN
2
EN
1
OUTF 7
OUTS 6
GND 3
GND 4
GND 5
GND 8
REF7040QFKHT
U9
10V
0.1µF
C30
GND
5V
GND
10V
10uF
C31
GND
1 2
J10
REFIO
10V
0.1µF
C10
5V
GND
1
2
3
4
5
OPA320AIDBVT
U8
402
R15
25V
1000pF
C33
DNP
GND
VCM
GND
VCM_FDA
1.00k
R7
1.00k
R10
10.0
R6
10.0
R13
24.9
R8
24.9
R11
20.0R9
20.0
R12
20.0
R20
20.0
R24
49.9
R32
DNP
49.9
R30
DNP
GND
50V
47pF
C11
50V
47pF
C13
100V
470pF
C12
GND 49.9
R33
DNP
GND
5V
10V
0.1µF
C25 GND
50V
47pF
C26
AINP_B
10.0
R17
1.00k
R18
24.9
R19
1
2 3 4 5
J7
VCM_FDA
100V
470pF
C27
25V
1000pF
C34
DNP
GND
AINM_B
1.00k
R21
24.9
R23
10.0
R25
50V
47pF
C28
1
2
3
4
5
J8
GND
GND
GND
49.9
R34
DNP
GND
R35
DNP VCMOUT
SCLK SCLK
SDI SDI
SDO 33R22
CSz
SDO
CSz SPI_EN
SPI_EN
RESETz RESETz
PWDNz PWDNz
SMPL_CLKP SMPL_CLKP
SMPL_CLKM EXT_SMPL_CLKM
3
1
2
VOCM1
4
14
15
V+
V-
1316
THS4552IPWR
U6A
11
9
10
12
7
6
VOCM2
8
5
V+
V-
THS4552IPWR
U6B
1.00k
R5
1.00k
R14
1.00k
R16
1.00k
R31
50V
270pF
C9
50V
270pF
C14
50V
270pF
C18
50V
270pF
C29
Figure 7-1. ADS9218EVM ADC Connections, Amplifiers, and Reference Schematic
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