THOMSON MK68590 User manual

iI a.)M~i']~1
COMPONENTS
COMMUNICATIONS PRODUCTS
~-~~--------
-----~------------------------
MOSTEK
TECHNICAL
MANUAL
MK68590
CONTROLLER FOR ETHERNET
LOCAL AREA NETWORK
1·91

1-92

SECTION
TABLE OF CONTENTS
Chapter 1
General Description
PAGE
1.0 Introduction
1,1 Overview ........................................................................ 1-1
1.2 Functional Capabilities ............................................................. 1-2
1.3 Functional Description ............................................................. 1-5
1.3.1 Serial Data Handling ........................................................ 1-5
1.3.2 Collision Detection and Implementation ......................................... 1-5
1.3.3 Buffer Management ........................................................ 1-5
1.3.4 Microprocessor Interface .................................................... 1-6
1.3.5 Pin Description ............................................................ 1-8
1.3.6 Lance Interface Description-Bus Master Mode .................................. 1-11
1.3.6.1 Read Sequence .................................................. 1-12
1.3.6.2 Write Sequence .................................................. 1-13
1.3.7 Lance Interface Description-Bus Slave Mode ................................... 1-13
2.0 Introduction
1.3.7.1 Read Sequence .................................................. 1-13
1.3.7.2 Write Sequence .................................................. 1-14
1.3.7.3 Reference Documents ............................................. 1-15
Chapter 2
Programming Specifications
2.1 Programming Specifications ........................................................ 2-1
2.2 Programming the LANCE .......................................................... 2-1
2.3 Control and Status Registers ....................................................... 2-1
2.3.1 Accessing the Control and Status Registers ................... ' .................. 2-1
2.3.1.1 Register Data Port (RDP) ........................................... 2-2
2.3.1.2 Register Address Port (RAP) ........................... : ............. 2-2
2.3.2 Control and Status Register Definition ......................................... 2-3
2.3.2.1 Control and Status Register 0 (CSRO) ................................. 2-3
2.3.2.2 Control and Status Register 1 (CSR1) ................................. 2-5
2.3.2.3 Control and Status Register 2 (CSR2) ................................. 2-5
2.3.2.4 Control and Status Register 3 (CSR3) ................................. 2-6
2.4 Initialization ...................................................................... 2-7
2.4.1 Initialization Block .......................................................... 2-7
2.4.1.1 Mode ........................................................... 2-8
2.4.1.2 Physical Address ................................................. 2-10
2.4.1.3 Logical Address Filter ............................................. 2-10
2.4.1.4 Receive Descriptor Ring Pointer ..................................... 2-12
2.4.1.5 Transmit Descriptor Ring Pointer ..................................... 2-13
2.5 Buffer Management .............................................................. 2-14
2.5.1 Descriptor Rings .......................................................... 2-14
2.5.1.1 Receive Message Descriptor Entry ................................... 2-14
2.5.1.1.1 Receive Message Descriptor 0 (RMDO) ...................... 2-14
2.5.1.1.2 Receive Message Descriptor 1 (RMD1) ....................... 2-14
2.5.1.1.3 Receive Message Descriptor 2 (RMD2) ...................... 2-16
2.5.1.1.4 Receive Message Descriptor 3 (RMD3) ...................... 2-16
2.5.1.2 Transmit Message Descriptor Entry .................................. 2-17
2.5.1.2.1 Transmit Message Descriptor 0 (TMDO) ...................... 2-17
2.5.1.2.2 Transmit Message Descriptor 1 (TMD1) ....................... 2-17
2.5.1.2.3 Transmit Message Descriptor 2 (TMD2) ...................... 2-18
2.5.1.2.4 Transmit Message Descriptor 3 (TMD3) ...................... 2-18
1-93

3.0 Introduction
Chapter 3
Functional Specifications
3.1 Functional Description ............................................................. 3-1
3.2 Logic ........................................................................... 3·1
3.2.1 Clock .................................................................... 3-1
3.2.2 Microsequencer ............................................................ 3·1
3.2.3 Control Data Path .......................................................... 3·1
3.2.4 Message Byte Count ........................................................ 3·1
3.2.5 Ring End Finders .......................................................... 3·1
3.3 Bus Control ..................................................................... 3·2
3.3.1 Bus Address Register ....................................................... 3·2
3.3.2 Memory Data Register ...................................................... 3-2
3.3.3 Bus Master Control ......................................................... 3·2
3.3.4 Memory Timeout ........................................................... 3·2
3.3.5 Bus Slave Control .......................................................... 3·2
3.3.6 Discrete User Apparent Registers ............................................. 3·2
3.4 Transceiver Data Path ............................................................. 3·2
3.4.1 Serial Data Output ......................................................... 3·2
3.4.2 Serial Data Input ........................................................... 3-3
3.4.3 SILO .................................................................... 3-3
3.4.4 SILO· Memory Byte Alignment ............................................... 3-4
3.4.5 Cyclic Redundancy Check ................................................... 3-4
3.5 Transmission ..................................................................... 3·5
3.5.1 Interpacket Delay .......................................................... 3-5
3.5.2 Collision Detection and Collision Jam .......................................... 3·5
3.5.3 Collision Backoff ........................................................... 3-6
3.5.4 Collision • Microcode Interaction .............................................. 3·6
3.5.5 Time Domain Reflectometry .................................................. 3·6
3.5.6 Heartbeat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . 3·6
3.6 Reception ....................................................................... 3·6
3.6.1 Station Address Detection ................................................... 3·7
3.6.1.1 Physical Address Register ........................................... 3-7
3.6.1.2 Logical Address Filter Register ....................................... 3·7
3.6.1.3 Promiscuous Mode ................................................ 3-7
3.6.1.4 Broadcast Address Detection ........................................ 3·7
3.6.2 Runt Packet Filtration ....................................................... 3·7
3.7 Loopback ....................................................................... 3-8
3.8 Microprogram Overview .......................•.................................... 3·8
3.8.1 Switch Routine ............................................................ 3·8
3:8.2 Initialization Routine ........................................................ 3·8
3.8.3 Polling Routine ............................................................ 3·8
3.8.4 Receive Polling Routine ..................................................... 3·9
3.8.5 Receive Routine ........................................................... 3-9
3.8.6 Receive DMA Routine ...................................................... 3·9
3.8.7 Transmit Polling Routine .................................................... 3·10
3.8.8 Transmit Routine .......................................................... 3·10
3.8.9 Transmit DMA Routine ..................................................... 3·10
3.8.10 Collision Trap Routine ...................................................... 3·11
3.8.11 CSR Trap Routine ................................................... , ..... 3·11
3.8.12 Memory Timeout Trap Routine ............................................... 3·11
3.8.13 Retry Trap Routine ......................................................... 3·11
3.8.14 Data Chain ............................................................... 3·11
Chapter 4
Electrical Specifications
4.0 Electrical Specifications ............................................................... ,4·1
1-94

FIGURE
NUMBER
LIST OF ILWSTRATIONS
TITLE
PAGE
1 LANCE Block Diagram ............................................................. 1-1
2 Ethernet and LANCE Packet Format ................................................. 1-2
3 Ethernet and LANCE Packet Bit Transmission Sequence ................................. 1-2
4 Ethernet Local Area Network System Block Diagram .................................... 1-3
5 Lance Conceptual View ............................................................ 1-4
6 LANCE Memory Management ................................................... , ... 1-6
7 LANCE Pin Assignment ............................................................ 1-7
8 Multiplexed Bus Interface .......................................................... 1-11
9 Demultiplexed Bus Interface ........................................................ 1-12
10 Bus Master Timing ............................................................... 1-13
11 Bus Slave Read Timing for CSRO, RAp, and CSR3 ..................................... 1-14
12 Bus Slave Write Timing for CSRO, RAP, and CSR3 ..................................... 1-14
13 Mapping of Logical Address to Filter Mask ........................................... 2-12
14 Output Load Diagram ............................................................. 4-5
15 Serial Link Timing Diagram ........................................................ 4-5
16 Bus Master Timing Diagram ........................................................ 4-6
17 LANCE Bus Slave Timing Diagram .................................................. 4-7
1-95 iii

1-96

1.0 INTRODUCTION
1.1 OVERVIEW
CHAPTER 1
GENERAL DESCRIPTION
The MK68590 LANCE (Local Area Network Controller for Ethernet) is a 48-pin VLSI device designed
to simplify greatly the interfacing of a microcomputer or a minicomputer to an Ethernet Local Area Net-
work. This chip is intended to operate
in a local environment that includes a closely coupled memory
and microprocessor. The LANCE uses scaled N-channel MOS technology and
is compatible with several
microprocessors. A block diagram of the chip is shown in Figure 1.
LANCE is a trademark of Mostek Corporation.
LANCE BLOCK DIAGRAM
Figure 1
BUFFER
CONTROL
TENA.-
A(B)
AX------------.---~~
CLSN
DAln6)
M
U
x
16 BIT INTERNAL BUS
1-97
f-----------~~H0I5
~--------- HLDA
---------.- DALci
MASTER f-------------I~ i3AiJ
CNTR
BUS
f---~~~----I~A~/As
f-----+- ... __ --I~ i5As
~--+-~_r~~~
~---------Cs
~READ
~BM(21
_.5
...-GNO(2)
1·1

1.2 FUNCTIONAL CAPABILITIES
The Local Area Network Controller for Ethernet (LANCE) interfacesto a microprocessor bus characterized
by time multiplexed address and data lines. Typically, data transfers are
16 bits wide, but byte transfers
occur if the buffer memory address boundaries are odd. The address bus is
24 bits wide.
The Ethernet packet format consists
of a 64·bit preamble, a 48·bit destination address, a 48·bit source
address, a 16·bit type field, and a 46 to 1500 byte data field terminated with a 32·bit CRC as shown
in Figure 2 and Figure
3. The variable widths of the packets accommodate both short status, command
and terminal traffic packets, and long data packets to printers and disks (1024 byte disk sectors for ex·
ample). Packets are spaced a minimum of
9.6 p.Sec apart to allow one node time enough to receive back·
to·back packets.
ETHERNET AND LANCE PACKET FORMAT
FIgure 2
r-------PACKET--------j
I--- MINIMUM PACKET SPACING (96 BIT TIMES,
*last Byte is Start of Frame Synchronization Byte--10101011
ETHERNET AND LANCE PACKET BIT TRANSMISSION SEQUENCE
Figure 3
1·2
r-' BYTE---1
PHYSICAl/MULTICAST BIT -.... .J
SBYrES
BBYrES
2 BYTES
46·1600 BYTES
4 BYTES
DESTINATION
SOURCE
TVPE
DATA
fRAME CHECK SEQUENCE
OCTETS WITHIN
FRAME TRANSMITTED
m'r"
LSBIIIIIIIIIMSB
L
BITS WITHIN
OCTETTRANSMITTED .......
LEFT-TO-RIGHT
1-98

The LANCE is intended to operate in a minimal configuration that requires close coupling between local
memory and a processor. Figure 5 shows the relationship between the chip and local memory. The local
memory provides packet buffering for the chip and serves as a communication link between the chip
and the processor. During initialization, the control processor loads into LANCE the starting address
of the initialization block plus the operating mode of the chip via two control registers. It is only during
this initial phase that the host processor talks directly to LANCE. All further communications are handled
via a DMA machine under microword control contained within the LANCE. Figure 4
is a block diagram
of the LANCE and SIA device used to create an Ethernet interface for a computer system.
ETHERNET LOCAL AREA NETWORK SYSTEM BLOCK DIAGRAM
Figure 4
c
o
M
P
U
T
E
R
S ... - __
Y
S
T
E
M
B
U
S
MICROPROCESSOR
·
MK68200
·
MK68000
·
8086
·
28000
·LSI·11
·
T·11
16·0ATA
--.
24·ADDRESS
LOCAL
MEMORY
LOCAL AREA
NETWORK 7
SERIAL
f-h
CONTROLLER FOR
+--f--
INTERFACE
ETHERNET
ADAPTER
(SIA)
( LANCEI
POWER
---f-
NETWORK INTERFACE MODULE
1-99
8
TRANSCEIVER
CABLE
NETWORK
CABLE
1-3

LANCE CONCEPTUAL VIEW
Figure 5
r---wC"E--- --,
I "'" ~
I CSR1 (AO-15) I r-
I CSR2 (A16-23) I r-- ~
I CSR3 I
I
DATA
I
.
~
~
I
SILO
I-
r-
I r I
I I
I I
I I
I RCVR XMTR
I I
L_~ ----t-..J
'--
~
r---
-
~
DATA
~
..
~
1-4 1-100
MEMORY
MODE
PHYSICAL ADDRESS
LOGICAL ADDRESS
POINTER
10 RECEIVE RINGS
RECEIVE RING LENGTH
POINTER 10 TRANSMIT RINGS
TRANSMIT RING LENGTH
RCV_ BUFFER LO-ADDRESS
STATUS' HI-ADDRESS
BUFFER BYTE LENGTH
RECEIVED MESSAGE LENGTH
RCV. BUFFER LO-ADDRESS
STATUS' HI-ADDRESS
BUFFER BYTE LENGTH
RECEIVED MESSAGE LENGTH
XMT. BUFFER LO-ADDRESS
STATUS' HI-ADDRESS
BUFFER BYTE LENGTH
BUFFER STATUS
'TDR
XMT. BUFFER LO-ADDRESS
STATUS' HI-ADDRESS
BUFFER BYTE LENGTH
BUFFER
STATUS' TDR
RCV. DATA PACKET(S)
RCV. DATA PACKET(S)
XMT.
DATA PACKET(S)
XMT. DATA PACKET(S)
} INITIALIZATION
BLOCK
RECEIVE
DESCRIPTOR
RING(S)
TRANSMIT
DESCRIPTOR
RING(S)
}
RECEIVE
DATA
BUFFER(S)
TRANSMIT
DATA
BUFFER(S)