Winbond W78C438C User manual

W78C438C
8-BIT MICROCONTROLLER
Publication Release Date: July 1998
- 1- Revision A1
GENERAL DESCRIPTION
The W78C438C is a high-performance single-chip CMOS 8-bit microcontroller that is a derivative of
the W78C58 microcontroller family. The W78C438C is functionally compatible with the W78C32,
except that it provides either a 64 KB program/1 MB data memory address or memory-mapped chip
select logic, five general I/O ports, and four external interrupts.
In the W78C32, two I/O ports, Port 1 and Port 3, are available for general-purpose use (Port 3 also
supports alternative functions), and Port 2 and Port 0 are used as the address bus and data bus,
respectively. To enable Port 0 and Port 2 to also be used as general purpose I/O ports, the
W78C438C provides two dedicated address ports (AP5 and AP6) that serve as address output for 64
KB of memory and one address/data port (DP4) that serves as ROM code input and external RAM
data input/output. Unlike the W78C32, this product does not require an external latch device for
multiplexing low byte addresses. The W78C438C also provides four pins (AP7.0−AP7.3) to support
either 64 KB program/1 MB data memory space or memory-mapped chip select logic, one parallel I/O
port (Port 8) without bit addressing mode, and two additional external interrupts (
INT2
,
INT3
).
The W78C438C is programmed in a manner fully compatible with that used to program the W78C32,
except that the external data RAM is accessed by the "MOVX @Ri" instruction. Address paging is
performed by loading page addresses into the HB (high byte) register, which is not a standard register
in the W78C32, before execution of the "MOVX @Ri" instruction.
FEATURES
•8-bit CMOS microcontroller
•Fully static design
•DC to 40 MHz operation
•ROM-less operation
•256-byte on-chip scratchpad RAM
•Either 64 KB program/1 MB data memory address space or 4 memory-mapped chip select pins
•One 8-bit data/address port
•Two 8-bit and one 4-bit (optional) address ports
•Five 8-bit bidirectional I/O ports
−Four 8-bit bit-addressable I/O ports and one 8-bit parallel I/O port
•Eight-source, two-level interrupt capability
•Three 16-bit timer/counters
•Four external interrupts
•One full-duplex serial channel
•Built-in power management
−Idle mode
−Power-down mode
•Packages:
−84-pin PLCC: W78C438CP-24/40
−100-pin PQFP: W78C438CF-24/40

W78C438C
- 2-
PIN CONFIGURATIONS
12
13
14
15
16
17
18
19
20
21
22
23
24
3
33
43
53 63
73
83 94
0
60
61
62
63
64
25
26
27
28
29
30
4
14 24 34 44 54 64 74 84 95 0
65
66
67
68
69
70
71
72
73
74
0
18911
W78C438CP
INT3
P1.5
P1.6
P1.7
RESET
P8.1
P8.0
P8.2
P8.4
P8.5
P8.3
P8.6
P8.7
INT2
RXD, P3.0
VDD
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
2
.
2
32
31
567 12
3
48
48 0
8
1
8
2
8
37
6
7
7
7
8
7
9
P
0
.
0
P
0
.
1
P
0
.
2
P
0
.
3
D
P
4
.
1
D
P
4
.
0
N
C
V
D
D
N
C
D
P
4
.
2
D
P
4
.
3
D
P
4
.
4
D
P
4
.
5
D
P
4
.
6
D
P
4
.
7
P
1
.
0
P
1
.
1
P
1
.
2
P
1
.
3
P
1
.
4
P
0
.
4
7
5
5
1
59
58
57
55
56
54
5
25 3
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V
S
S
A
P
7
.
3
,
/
C
S
3
A
P
7
.
2
,
/
C
S
2
N
CA P
7
.
0
,
/
C
S
0
A
P
7
.
1
,
/
C
S
1
A
P
6
.
7
A
P
6
.
6
A
P
6
.
5
A
P
6
.
4
A
P
6
.
3
A
P
6
.
2
A
P
6
.
1
A
P
6
.
0
P
2
.
0
P
2
.
1
P
3
.
6
,
/
W
R
P2.4
P2.5
P2.6
P2.7
EA
PSEN
ALE
AP5.7
AP5.6
AP5.5
AP5.4
AP5.3
AP5.2
AP5.1
V
P2.3
AP5.0
P0.7
P0.6
P0.5
V
84-pin PLCC
DD
SS

W78C438C
Publication Release Date: July 1998
- 3- Revision A1
Pin Configurations, continued
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
18
19
9
20
21
22
23
24
01 2
3 3 3
3 4 5
3 3 3
63 7 8
3 3
9 0
4
0
25
26
27
28
29
30 4
123456789
4 4 4 4 4 4 4 4 5 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
97
89012
3
45678 6 5 12
3
4888888888999999999
1
0
V
D
DN
C
P
0
.
3
P
0
.
1
P
0
.
2
P
0
.
0
D
P
4
.
0
D
P
4
.
1
D
P
4
.
2
D
P
4
.
3
D
P
4
.
4
D
P
4
.
5
D
P
4
.
6
D
P
4
.
7
T
2
,
P
1
.
0
P
1
.
2
P
1
.
3
P
1
.
4
N
C
NC
NC
NC
NC
P2.4
P2.5
P2.7
P2.6
V
AP5.7
AP5.6
AP5.5
AP5.4
ALE
AP5.0
PSEN
AP5.1
P0.6
P0.5
P0.4
NC
NC
NC
P0.7
EA
P2.3
AP5.3
AP5.2
NC
V
W78C438CF
X
T
A
L
2
X
T
A
L
1
V
S
S
N
C
P
3 .
7 ,
/
R
D
A
P
7
.
3
,
/
C
S
3
A
P
7
.
2
,
/
C
S
2
A
P
7
.
1
,
/
C
S
1
A
P
6
.
7
A
P
6
.
2
A
P
6
.
1
A
P
6
.
4
A
P
6
.
6
A
P
6
.
3
A
P
6
.
5
A
P
6 .
0
P
2
.
0
P
2
.
1
P
2
.
2
A
P
7
.
0
,
/
C
S
0
NC
NC
NC
NC
NC
P1.7
NC
NC
NC
P1.5
P1.6
P8.0
RESET
P8.1
P8.2
P8.3
P8.4
P8.5
P8.7
P8.6
VDD
RXD, P3.0
TXD, P3.1
T0, P3.4
T1, P3.5
WR, P3.6
INT2
INT3
INT1, P3.3
INT0, P3.2
T
2
E
X
,
P
1
.
1
100-pin PQFP DD
SS

W78C438C
- 4-
PIN DESCRIPTION
P0.0 − P0.7 I/O Port 0
These pins function the same as those in the W78C32, except that a multiplexed address/data bus is
not provided during accesses to external memory.
P1.0 − P1.7 I/O Port 1
Functions are the same as in the W78C32.
P2.0 − P2.7 I/O Port 2
Functions are the same as in the W78C32, except that an upper address bus is not provided during
accesses to external memory.
P3.0 − P3.7 I/O Port 3
Functions are the same as in the W78C32.
DP4.0 − DP4.7 Data/Address Bus
DP4 provides multiplexed low-byte address/data during access to external memory.
AP5.0 − AP5.7 Address Bus
AP5 outputs the <7:0> address of the external ROM multiplexed with the <7:0> address of the
external data RAM.
AP6.0 − AP6.7 Address Bus
AP6 outputs the <15:8> address of the external ROM multiplexed with the <15:8> address of the
external data RAM. During the execution of "MOVX @Ri," the output of AP6 comes from the HB
register, which is the page register for the high byte address, and its address is 0A1H.
AP7.0 − AP7.3 Address Bus/Chip Select Pins
Set bit 7 of the EPMA (Extended Program Memory Address) register to determine the functions of
port 7. When this bit is "0" (default value), AP7 allows the external memory data to be accessed by
outputting the <19:16> address of the external memory from bits<3:0> of the EPMA register during
the execution of "MOVC A, @A+DPTR" or "MOVX dest, src." At all other times, AP7<3:0> will output
0H.
When this bit is "1," AP7<3:0> (CS3−0) are the chip select pins, which support memory-mapped
peripheral device select, and only one pin is active low at any one time. These pins are decoded by
AP6<7:6>. For details, see the table below.
AP6.7 AP6.6 DESCRIPTION
0 0 AP70: low; others: high
0 1 AP71: low; others: high
1 0 AP72: low; others: high
1 1 AP73: low; others: high

W78C438C
Publication Release Date: July 1998
- 5- Revision A1
P8.0 − P8.7 I/O Port
Functions are the same as those of Port 1 in the W78C31, except that they are mapped by the P8
register and not bit-addressable. The P8 register is not a standard register in the W78C32. Its address
is at 0A6H.
INT2
,
INT3
External Interrupt, Input
Functions are similar to those of external
INT0
,
INT1
in the W78C32, except that the functions/status
of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control)
register. The XICON register is bit-addressable but is not a standard register in the W78C32. Its
address is at 0C0H. For details, see the Functional Description below.
EA
External Address, Input
Functions same as W78C32.
RST, XTAL1, XTAL2,
PSEN
, ALE
Functions same as W78C32.
BLOCK DIAGRAM
SFR
RAM
256
Bytes
CPU
Serial
Port
Data Bus
CORE
Interrupt
INT0
Timer0
Timer2
Port 0
Port 1
Port 2
Alternate
Port 8
DP4
AP5
AP6
AP7
Alternate
INT1
Timer1
INT2
INT3
Port 3
Alternate

W78C438C
- 6-
FUNCTIONAL DESCRIPTION
The W78C438C is a functional extension of the W78C58 microcontroller. It contains a 256 ×8 RAM,
64 KB program/1 MB data memory address or memory-mapped chip select logic, two 8-bit address
ports, one 8-bit data port, five general I/O ports, four external interrupts, three timers/counters, and
one serial port.
Dedicated Data and Address Port
The W78C438C provides four general-purpose I/O ports for W78C32 applications; the address and
data bus are separated from Port 0 and Port 2 so that these ports can be used as general-purpose I/O
ports. In this product, DP4 is the data bus for external ROM and RAM, AP5<7:0> are the low byte
address, AP6<7:0> are the high byte address,
PSEN
enables the external ROM to DP4, and P3.6
(
WR
) and P3.7 (
RD
) are the write/read control signals for the external RAM. The external latch for
multiplexing the low byte address is no longer needed in this product. The W78C438C uses AP5 and
AP6 to support 64 KB external program memory and 64 KB external data memory, just as a standard
W78C32 does.
The W78C438C provides four pins, AP7.3−AP7.0 (CS3−CS0), to support either 64 KB program/1 MB
data memory space or memory-mapped chip select logic. Bit 7 of the EPMA (Extended Program
Memory Address) register, which is described in Table 1 below, determines the functions of these
pins.
When this bit is "0" (the default value), AP7<3:0> support external program/data memory addresses
up to 64 KB/1 MB for applications which need additional external memory to store large amounts of
data.
Although there is 1M bytes memory space, instructions stored here can not be run at full range of this
area except the first 64 Kbytes. It is owing to the fact that during the instruction fetch cycle, AP7<3:0>
always output 0s to address lines A19−A16. This limits the program code to store at address 0−
0FFFFH (64K). The rest of the area (10000H−FFFFFH) can be treated as ROM data storage which
can be read by "MOVC A, @A+DPTR" instruction.
When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is
executed to access the external RAM data, AP7<3:0> output address <19:16> from bits <3:0> of the
EPMA (Extended Program Memory Address) register. At other times, AP7<3:0> always output 0H to
ensure the instruction fetch is within the 64K program memory address. Different banks can be
selected by modifying the content of the EPMA register before the execution of "MOVC A,
@A+DPTR" or "MOVX dest, src."
[Example]. Access the external ROM/RAM data from external memory space.
CLR A; Clear Accumulator.
MOV DPTR, #0H ; Clear DPTR.
MOV 0A2H, #02 ; Initialize EPMA(0A2H). EPMA.7 = 0: extended memory space
; EPMA.<3:0> = 0010B, the address range: 20000−2FFFFH.
MOVC A, @A+DPTR ; Read the external ROM data from location 20000H.
MOVX A, @DPTR ; Read the external RAM data from location 20000H.
CLR A
MOV 0A2H, #03H ; EPMA.<3:0> = 0011B, the address range: 30000H−3FFFFH.
MOVC A, @A+DPTR ; Read the external ROM data from location 30000H.
MOVX @DPTR, A ; Write the contents of Accumulator to external RAM data.
; location 30000H.

W78C438C
Publication Release Date: July 1998
- 7- Revision A1
(A) EPMA.7 = 0
W78C438 EPROM
RAM
AP5
PSEN
ADDR 1MB
(20-bit)
ADDR (20-bit)
DATA
AP6
DP4
WR
RD P3
OE
WE
OE
AP7
P1
P0
P2
P8
INT1
INT3
INT0
INT2
\ 8
\ 4\ 8
\ 8
64K PROGRAM
DATA AREA
When bit 7 of the EPMA is "1," AP7<3:0> are the output pins that support memory-mapped peripheral
chip select logic, which eliminates the need for glue logic. These pins are decoded by AP6<7:6>.
Only one pin is active low at any time. That is, they are active individually with 16K address
resolution. For example, CS0 is active low in the address range from 0000H to 3FFFH, CS1 is active
low in the address range from 4000H to 7FFFH, and so forth.
(B) EPMA.7 = 1
W78C438
AP5
PSEN
AP6
DP4
WR
RD
P3
P1
P0
P2
P8
INT1
INT3
INT0
INT2 RAM
ADDR (14-bit)
DATA
WE
OE
AP7.0
AP7.1
AP7.2
AP7.3
0000h
3FFFh
4000h
7FFFh
8000h
BFFFh
C000h
FFFFh
\ 8
\ 8
\ 6
\ 8
\ 8
Device Device Device
(16k) (16k) (16k) (16k)
EPROM
OE
64K PROGRAM
DATA AREA
ADDR (16-bit)

W78C438C
- 8-
The EPMA register is a nonstandard 8-bit SFR at address 0A2H in the standard W78C32. To
read/write the EPMA register, one can use the "MOV direct" instruction or "read-modify-write"
instructions. Bits <6:4> of the EPMA register are reserved bits, and their output values are 111B if
they are read. The content of EPMA is 70H after a reset. The EPMA register does not support bit-
addressable instructions.
BIT NAME FUNCTION
7EPMA7 EPMA7 = 0: 64 KB program/1 MB data memory space mode
EPMA7 = 1: memory-mapped chip select mode
6EPMA6 Reserved
5EPMA5 Reserved
4EPMA4 Reserved
3EPMA3 Value of AP7.3
2EPMA2 Value of AP7.2
1EPMA1 Value of AP7.1
0EPMA0 Value of AP7.0
Table 1. Functional Description of EPMA Register
Additional I/O Port
The W78C438C provides one parallel I/O port, Port 8. Its function is the same as that of Port 1 in the
W78C31, except that it is mapped by the P8 register and is not bit-addressable. The P8 register is not
a standard register in the standard W78C32. Its address is at 0A6H. To read/write the P8 register, one
can use the "MOV direct" instruction or "read-modify-write" instructions.
[Example]: MOV 0A6H, A ; Output data via Port 8.
MOV A, 0A6H ; Input data via Port 8.
Additional External Interrupt
The W78C438C provides two additional external interrupts,
INT2
and
INT3
, whose functions are
similar to those of external interrupts 0 and 1 in the W78C32. The functions (or the status) of these
interrupts are determined by (or shown by) the bits in the XICON (External Interrupt Control) register.
For details, see Table 2. The XICON register is bit-addressable but is not a standard register in the
standard 80C32. Its address is at 0C0H. To set/clear the bit of the XICON register, one can use the
"SETB(
CLR
) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. The interrupt
vector addresses and the priority polling sequence within the same level are shown in Table 3.
[Example].
SETB 0C0H ;
INT2
is falling-edge triggered.
SETB 0C3H ;
INT2
is high-priority.
SETB 0C2H ; Enable
INT2
.
CLR 0C4H ;
INT3
is low-level triggered.

W78C438C
Publication Release Date: July 1998
- 9- Revision A1
BIT ADDR. NAME FUNCTION
70C7H PX3 High/low priority level for INT3 is specified when this bit is set/cleared by software.
60C6H EX3 Enable/disable interrupt from INT3 when this bit is set/cleared by software.
50C5H IE3 If IT3 is "1," IE3 is set/cleared automatically by hardware when interrupt is
detected/serviced.
40C4H IT3
INT
3
is falling-edge/low-level triggered when this bit is set/cleared by software.
30C3H PX2 High/low priority level for
INT
2
is specified when this bit is set/cleared by software.
20C2H EX2 Enable/disable interrupt from INT2 when this bit is set/cleared by software.
10C1H IE2 If IT2 is "1," IE2 is set/cleared automatically by hardware when interrupt is
detected/serviced.
00C0H IT2
INT
2
is falling-edge/low-level triggered when this bit is set/cleared by software.
Table 2. Functions of XICON Register
INTERRUPT SOURCE VECTOR ADDRESS PRIORITY SEQUENCE
External Interrupt 0 03H 0 (Highest)
Timer/Counter 0 0BH 1
External Interrupt 1 13H 2
Timer/Counter 1 1BH 3
Serial Port 23H 4
Timer/Counter 2 2BH 5
External Interrupt 2 33H 6
External Interrupt 3 3BH 7 (Lowest)
Table 3. Priority of Interrupts
Newly Added Special Function Registers
The W78C438C uses four newly defined special function registers, which are described in Table 4. To
read/write these registers, use the "MOV direct" or "read-modify-write" instructions.
REGISTER ADDR. FUNCTION LENGTH R/W
TYPE VALUE
AFTER
RESET
1HB A1H During the execution of "MOVX @Ri," the content of HB is output to
AP6. 8 R/W 00H
2EPMA A2H EPMA.7 determines functions of AP7.
EPMA.3−EPMA.0 determine values of AP7<3:0> when EPMA.7 is
"0."
8 R/W 70H
3P8 A6H The content of P8 is output to port 8. 8 R/W 0FFH
4XICON C0H The bits of XICON determine/show the functions/status of INT2 −
INT3 .Bit-addressable.
8 R/W 00H
Table 4. Newly Added Special Function Registers of the W78C438C

W78C438C
- 10 -
Notes:
1. The instructions used to access these nonstandard registers may cause assembling errors with respect to the 2500 A. D.
assembler, but these errors can be ignored by adding directive ".RAMCHK OFF" ahead these instructions.
2. In the newly added SFR of W78C438C, only XICON register is bit-addressable.
Power Reduction Function
The W78C438C supports power reduction just as the W78C32 does. The following table shows the
status of the external pins during the idle and power-down modes.
FUNCTION ALE, PSEN P0
− P3, P8 DP4 AP5, AP6 AP7
Idle 1 1 Port Data Floating Address Note
Power Down 0 0 Port Data Floating Address Note
Note: AP7 is either 0 or a value decoded by AP6<7:6>, depending on the value of EPMA.7.
Programming Difference
The W78C438C is programmed in the same way as the W78C32, except that the external data RAM
is accessed by a "MOVX @Ri" instruction. To support address paging, there is an additional 8-bit SFR
"HB" (high byte), which is a nonstandard register, at address 0A1H. During execution of the "MOVX
@Ri" instruction, the contents of HB are output to AP6. The page address is modified by loading the
HB register with a new value before execution of the "MOVX @Ri" instruction. To read/write the HB
register, one can use the "MOV direct" instruction or "read-modify-write" instructions. The HB register
does not support bit-addressable instructions.
[Example]. MOV R1, #0H ; R1 = 0.
MOV 0A1H, #0FFH ; HB contents FFH.
MOVX A, @R1 ; Read the contents of external RAM location FF00H into
; Accumulator.
MOV 0A1H, #12H ; HB contents 12H.
MOVX @R1, A ; Copies the contents of Accumulator into external RAM
; location 1200H.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply VDD−VSS -0.3 +7.0 V
Input Voltage VIN VSS -0.3 VDD +0.3 V
Operating Temperature TOPR 0 70 °C
Storage Temperature TSTG -55 +150 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

W78C438C
Publication Release Date: July 1998
- 11 - Revision A1
DC CHARACTERISTICS
VDD−VSS = 5V ±10%, TA= 25°C, FOSC = 20 MHz, unless otherwise specified.
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Oper. Voltage VDD 4.5 55.5 V
Oper. Current IDD * No load - - 20 mA
Idle Current IIDLE Program idle mode --7mA
Pwdn Current IPWDN Program power-down mode - - 50 µA
Input Leakage
Current ILK1
INT2
,
INT3
Internal pull-high Notes 1, 2
-300 -+10 µA
Input Leakage
Current ILK2 RESET
Internal pull-low Notes 1, 2
-10 -+300 µA
Input Leakage
Current ILK3
EA
, Port 0, DP4 Note 1 -10 -+10 µA
Input Leakage
Current ILK4 P1, P2, P3, P8 Note 1 -50 -+10 µA
Output Low Voltage VOL1 IOL1 = 2 mA (Port 1, 2, 3, 8) - - 0.45 V
Output High Voltage VOH1 IOH1 = -100 µA(Port 1, 2, 3, 8) 2.4 --V
Output Low Voltage VOL2 IOL2 = 4mA Note 3
(ALE,
PSEN
, P0, DP4) - - 0.45 V
Output High Voltage VOH2 IOH2 = -400 µANote 3
(ALE,
PSEN
, P0, DP4) 2.4 --V
Output Low Voltage VOL3 IOL2 = 2 mA (AP5, AP6, AP7) - - 0.45 V
Output High Voltage VOH3 IOH2 = -100 µA(AP5, AP6, AP7) 2.4 --V
Input Voltage VILT VDD = 5V ±10% 0-0.8 V
Input Voltage VIHT VDD = 5V ±10% 2.4 -Note 4 V
Input Voltage VILC VDD = 5V ±10%, XTAL1 Note 5 0-0.8 V
Input Voltage VIHC VDD = 5V ±10%, XTAL1 Note 5 3.5 -Note 4 V
Input Voltage VILR VDD = 5V ±10%, RESET Note 5 0-0.8 V
Input Voltage VIHR VDD = 5V ±10%, RESET Note 5 2.4 -Note 4 V
Notes:
1. 0 < VIN < VDD, for INT2 ,
INT
3
, RESET,
EA
, Port 0, DP4, P1, P2, P3 and P8 inputs in leakage.
2. Using an internal pull low/high resistor (approx. 30K).
3. ALE, PSEN , P0 and DP4 in external program or data access mode.
4. The maximum input voltage is VDD +0.2V.
5. XTAL1 is a CMOS input and RESET is a Schmitt trigger input.

W78C438C
- 12 -
AC CHARACTERISTICS
AC specifications are a function of the particular process used to manufacture the product, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation.
Clock Input Waveform
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Operating Speed FOP 0-40 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 10 - - nS 3
Clock Low TCL 10 - - nS 3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Address Valid to
PSEN
Low TAPL 2 TCP - - nS
PSEN
Low to Data Valid TPDV - - 2 TCP nS
Data Memory Read/Write Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Address Valid to
RD
Low TARL 4 TCP -4 TCP +∆nS
RD
Low to Data Valid TRDV - - 4 TCP nS
Data Hold After
RD
High TRDQ 0-2 TCP nS
RD
Pulse Width TRS 6 TCP -∆6 TCP -nS
Address Valid to
WR
Low TAWL 4 TCP -4 TCP +∆nS
Data Valid to
WR
Low TDWL 1 TCP - - nS
Data Hold After
WR
High TWDQ 1 TCP - - nS
WR
Pulse Width TWS 6 TCP -∆6 TCP -nS
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

W78C438C
Publication Release Date: July 1998
- 13 - Revision A1
TIMING WAVEFORMS
Program Fetch Cycle
S1 S2
XTAL1
PSEN
S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
AP6<7:0>
AP5<7:0>
DP4<7:0>
address
code
address
TAPL
TPDV
Data Memory Read/Write Cycle
S1 S2 S3S8 S9 S10 S11 S12S4 S5 S6 S7
XTAL1
PSEN
data
addr.
RD
DP4<7:0>
WR
DP4<7:0> DATA OUT addr.
addr.
TRS
TARL
TRDV TRDQ
TWS
TDWL TWDQ
TAWL
AP6<7:0> DPH or HB SFR out PGM address
PGM address
DPL or Ri out
AP5<7:0>
AP7<3:0> addr <19:16> out
(When bit7 of EPMA is 0.)

W78C438C
- 14 -
TYPICAL APPLICATION CIRCUITS
Using 128K ×8 bit External EPROM (W27E010)
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
18
19
20
21
22
23
24
25
26
27
28
29
30 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
12
3
489 7
89012
3
456789
06 5 888888889999999991
0
P1.5
AP5.7
P
2
.
2
P2.3
P2.4
P0.5
P0.7
P0.6
AP5.6
AP5.5
AP5.4
AP5.3
AP5.2
AP5.1
AP5.0
P2.5
P2.6
P2.7
PSEN
ALE
EA
A
P
6
.
7
01 2
333
3 4 5
333
63 7 8
3 3
9 0
4 4
123456789
444444445
A
X
T
L
1
X
T
A
L
2
5 V
8.2 K
10 U
C2
C1
R
P1.6
P1.7
RESET
P8.1
P8.2
P8.3
P8.4
P8.5
P3.0, RXD
P3.1, TXD
P3.3, INT1
P3.4, T0
INT3
P3.2, INT0
P3.5, T1
P3.6, WR
INT2
P8.0
P8.6
P8.7
A
P
7
.
3
,
/
C
S
3
A
P
7
.
2
,
/
C
S
2
A
P
7
.
1
,
/
C
S
1
A
P
7
.
0
,
/
C
S
0
A
P
6
.
6
A
P
6
.
5
A
P
6
.
4
A
P
6
.
3
A
P
6
.
2
P
3
.
7
,
/
R
D
A
P
6
.
0
A
P
6
.
1
P
2
.
1
P
2
.
0
P0.4
P
1
.
4
P
1
.
3
P
1
.
2
P
1
.
1
P
1
.
0
D
P
4
.
7
D
P
4
.
6
D
P
4
.
5
D
P
4
.
4
D
P
4
.
3
D
P
4
.
2
D
P
4
.
1
D
P
4
.
0
P
0
.
0
P
0
.
1
P
0
.
2
P
0
.
3
VDD
VDD
VSS
W78C438C
A0
12 A1
11 A2
10 A3
9 A4
8 A5
7 A6
6 A7
5 A8
27 A9
26 A10
23 A11
25 A12
4 A13
28 A14
29 A15
3
CE
OE
O0 13
O1 14
O2 15
O3 17
O4 18
O5 19
O6 20
O7 21
GND
A16
Vpp
Vcc
PGM
Vss
2
22
24
1
32
31
16
V
D
D
N
C
N
C
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
W27E010
V
S
SN
C
Figure A

W78C438C
Publication Release Date: July 1998
- 15 - Revision A1
CRYSTAL C1 C2 R
16 MHz 30P 30P −
24 MHz 15P 15P −
33 MHz 10P 10P 6.8K
40 MHz 5P 5P 6.8K
Above table shows the reference values for crystal applications.
Notes:
1. For C1, C2, R components refer to Figure A.
2. It is recommended that the crystals be replaced with oscillators for applications above 35 MHz.
PACKAGE DIMENSIONS
84-pin PLCC
2A
H
D
D
eb
EHE
y
A
A
Seating Plane
D
G
E
11 84 751
12
32
33 53
54
74 Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inches Dimension in mm
A
b
c
D
e
HE
L
y
A
A1 2
E
b1
HD
G
GD
E
0.020
0.143
0.026
0.016
0.006
1.148
1.095
1.180
0.090
0.148
0.028
0.018
0.008
1.153
1.115
1.190
0.100
0.050
0.185
0.153
0.032
0.022
0.012
1.158
1.135
1.200
0.110
0.004
0.51
3.63
0.66
0.41
0.15
29.17
27.81
29.98
2.29
3.76
0.71
0.46
0.20
29.29
28.32
30.23
2.54
1.27
4.70
3.89
0.81
0.56
0.30
29.41
28.83
30.48
2.79
0.10
0.044 0.056 1.12 1.42
29.4129.2929.17
1.1581.1531.148
28.8328.3227.81
1.1351.115
1.095
010 10 0
30.48
30.23
29.981.200
1.190
1.180
θ
on final visual inspection spec.
4. General appearance spec. should be based
3. Controlling dimension: Inches
protrusion/intrusion.
2. Dimension b1 does not include dambar
flash.
1. Dimension D & E do not include interlead
Notes:

W78C438C
- 16 -
Package Dimensions, continued
100-pin QFP
51
5031
30
180
81100
1
A
H
D
D
eb
EHE
y
AA
Seating Plane L
L1
See Detail F
Detail F
c
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
0.102
0120
0.004
2.413
1.397
19.10
1.194
18.80
0.991
18.49
0.095
0.055
0.988
0.752
0.047
0.976
0.740
0.039
0.964
0.728
0.65
20.13
14.13
0.254
0.407
2.972
3.30
20.00
14.00
2.845
19.87
13.87
0.101
0.254
2.718
0.10
0.792
0.556
0.010
0.016
0.117
0.130
0.787
0.551
0.112
0.026
0.782
0.546
0.004
0.010
0.107
0.004
Notes:
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in inches Dimension in mm
A
b
c
D
e
HD
HE
L
y
A
A
L1
1
2
E
0.012
0.006 0.152
0.305
24.49 24.80 25.10
12
0.020
0.087
0.032
0.103
0.498 0.802
2.21 2.616
2
θ
θ
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]
Note: All data and specifications are subject to change without notice.