Winbond W928C73 User manual

Preliminary W928C73
POCSAG MICROCONTROLLER
Publication Release Date: June 2000
-1-Revision A1
GENERAL DESCRIPTION
The W928C73 is a high performance 8 bits microcontroller with build-in POCSAG decoder and LCD
driver. It is possible to switch the normal mode, idle mode and power down mode for power saving
purpose. The W928C73 is an extended µC from standard 8031 (excluding UART) that it can be easily
applied to pager system or other telecommunication system.
FEATURES
•512, 1200 and 2400 bps POCSAG decoder
•6 independent user addresses
•Instruction set compatible with MCS51
•System clock
−OSC2: 76.8 KHz
•128 bytes on-chip fast RAM
•384 bytes on-chip MOVX RAM
•16K bytes on-chip program ROM
•32 ×32 bits on-chip flash RAM
•Timer
−Two 16-bit timer/counters
−One RTC timer
−One Watch-dog timer
−One Buzzer timer
•Four 8-bit bit-addressable I/O ports
•Three external interrupt source, INT0, INT1 (BAT_DET_INT), INT3 (KEY_INT)
•Battery low detector
•Battery detector
•Power fail detector
•Power down wake-up via external interrupts
•Two 16-bit Data Pointers (Selected by DPS.0)
•10 source, 10 vector interrupts structure with two priority-level interrupts
•Built-in programmable power-saving modes -Idle mode & Power-down mode
•Operating voltage range: 2.4V to 3.3V
•32 segment ×4 common, 1/3 bias, 1/4 duty LCD driver output
•Packaged in 64-pin LQFP
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Preliminary W928C73
-2-
PIN CONFIGURATION
W928C73
P1.5/MOTOR
P1.6/BUZZER
P1.7/LED
Vss
RESET
EA
TEST1
TEST2
P3.0
P
2.2
P
2.3
V
2.7
P
V
D
D
X
O
U
T
2
X
I
N
2
BL_RF
DI
BS1
BS2
BS3
P3.1 SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG29
SEG28
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
3
S
E
G
35
/ /
S
E
G
34
P
3.2
/
I
N
T
0
P
3.3
/
I
N
T
1
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
10
S
E
G
11
S
E
G
12
S
E
G
13
3
64 LQFP
P
0.4
P
0.5
P
0.6
/
K
E
Y
2
/
K
E
Y
1
/
K
E
Y
0
PSEN
P
2.4
2.6
P2.5 P

Preliminary W928C73
Publication Release Date: June 2000
-3-Revision A1
PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTIONS
VSS IGROUND: ground potential
RST
I H RESET: A low on this pin for two machine cycles while the oscillator is
running resets the device.
P1.5 OMotor output, hi-drive
P1.6 OBuzzer clock output, hi-drive
P1.7 OLED output, hi-drive
BL_RF IConnect to LVS of IF chip
DI IPOCSAG signal input
BS1 ORF control 1
BS2 ORF control 2
BS3 ORF control 3
EA
IExternal access enable pin. Should connect to VDD.
TEST1 INo connection. Test pin. Internal pull low
TEST2 INo connection. Test pin. Internal pull low
PSEN
ONo connection. Test pin.
P3.0 I/O Bit addressable general I/O port 3.0
P3.1 I/O Bit addressable general I/O port 3.1
P3.2/INT0 I/O Bit addressable general I/O port 3.2 or INT0 defined by SFR
P3.3/INT1 IBattery fail interrupt input. Connect to V1.5. If voltage potential of battery is
less than the 0.8V, the INT1 interrupt flag will be set.
SEG0 OLCD segment signal out
SEG1 OLCD segment signal out
SEG2 OLCD segment signal out
SEG3 OLCD segment signal out
SEG4 OLCD segment signal out
SEG5 OLCD segment signal out
SEG6 OLCD segment signal out
SEG7 OLCD segment signal out
SEG8 OLCD segment signal out
SEG9 OLCD segment signal out
SEG10 OLCD segment signal out
SEG11 OLCD segment signal out
SEG12 OLCD segment signal out
SEG13 OLCD segment signal out

Preliminary W928C73
-4-
Pin Descriptions, continued
SYMBOL TYPE DESCRIPTIONS
SEG14 OLCD segment signal out
SEG15 OLCD segment signal out
SEG16 OLCD segment signal out
SEG17 OLCD segment signal out
SEG18 OLCD segment signal out
SEG19 OLCD segment signal out
SEG20 OLCD segment signal out
SEG21 OLCD segment signal out
SEG22 OLCD segment signal out
SEG23 OLCD segment signal out
SEG24 OLCD segment signal out
SEG25 OLCD segment signal out
SEG26 OLCD segment signal out
SEG27 OLCD segment signal out
SEG28 OLCD segment signal out
SEG29 OLCD segment signal out
P2.2/SEG34 OLCD segment signal out
P2.3/SEG35 OLCD segment signal out
P2.4/VDD3ILCD voltage input (VDD)
P2.5 I/O I/O pin
P2.6 I/O I/O pin
P2.7 I/O I/O pin
COM0 OLCD common signal output pins.
COM1 OLCD common signal output pins.
COM2 OLCD common signal output pins.
COM3 OLCD common signal output pins.
P0.4 IBit addressable general I/O port 0.4 and Key_0 interrupt
P0.5 IBit addressable general I/O port 0.5 and Key_1 interrupt
P0.6 IBit addressable general I/O port 0.6 and Key_2 interrupt
VDD IPOWER SUPPLY: Supply voltage for operation.
XOUT2 OOutput pin for clock_2. It is the inversion of XIN2.
XIN2 IInput pin for clock_2
Note 1: I/O TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

Preliminary W928C73
Publication Release Date: June 2000
-5-Revision A1
BLOCK DIAGRAM
ALU Stack PointerPSW
ACC B
T1 register T2 register
Port
3
Port
1
Port
0
Port
2
128B MOV RAM
384B MOVX RAM
SFR
Instruction
Decoder &
Sequencer
Port
4~8
16KB
DPTR
DPTR 1
PC
Address REG
Address bus
Data bus
L_Clock
Clock Generator
System control
I
N
T
E
R
R
U
P
T
Timer 0
Timer 1
Buzzer Timer
RTC Timer
Watchdog Timer
RESET
program ROM
Power on &
power low
reset
XIN2 XOUT2
LCD
Driver
32x4
LCD_OFF
LCD_ON
P0.3
P0.7
P1.5
P1.7
P1.0
P1.2
P3.0
P3.3
P2.5
P2.7
P4.0~4.7
P5.0~5.7
P6.0~6.7
P7.0~7.7
P8.0~8.3
1K FLASH RAM

Preliminary W928C73
-6-
FUNCTIONAL DESCRIPTION
The W928C73 is a high performance 8 bits POCSAG microcontroller with build-in LCD driver and
POCSAG decoder. The uC is 8031 instruction set compatible with one addition: DEC DPTR (op-code
A5H, the DPTR is decreased by 1). The W928C73 has all the standard features of the 8031 except
the UART, and has a few extra peripherals and features like watchdog, RTC, buzzer timers, LCD
driver, and build-in POCSAG decoder.
The W928C73 features a faster running and better performance 8-bit CPU by reducing the machine
cycle duration from the standard 8031 period of twelve clocks to four clock cycles for the majority of
instructions. The W928C73 also provides dual Data Pointers (DPTRs) to speed up block data memory
transfers. In addition, the W928C73 contains on-chip 384B MOVX SRAM. It only can be accessed by
MOVX instruction; this on-chip data memory can be enabled by software commend.
Memory Organization
The W928C73 separates the memory into two sections, the Program Memory and Data Memory. The
Program Memory is used to store the instruction op-codes, while the Data Memory is used for storing
data or memory mapped devices. The
EA
pin must connect to high to access on-chip program ROM.
16 K bytes
Program
Memory
System testing
0000H
0080H
0200H
3FFFH
Interrupt vector 0000H
017FH
384 Bytes
Data
MOVX RAM
00H
7FH Direct & indirect
Addressing RAM
LCD RAM
EEH
FFH
80H
FFH Direct addressing
SFR
Program Memory Internal Data Memory Internal Data Memory Special Function Register
On-chip memory space of W928C73
Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP),
which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the
return address is placed on the stack. There is no restriction as to where the stack can begin in the
RAM. By default however, the Stack Pointer contains 07H at reset. The user can then change this to
any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and
then address saved onto the stack. Conversely, while popping from the stack the contents will be read
first, then the SP is decreased.

Preliminary W928C73
Publication Release Date: June 2000
-7-Revision A1
LCD Data Area
When LCD ON, the indirect RAM area EEH−FFH work as the LCD data RAM (LCD00−LCD35).
Instruction such as "MOV @R0, #I" (Where R0 = EEH−FFH) are used to control the LCD data RAM.
The data in the LCD data RAM (bit7−bit0) are transferred to the segment output pins automatically
without program control. When the bit value of the LCD data RAM is "1", the LCD is turned on. When
the bit value of the LCD data RAM is "0", LCD is turned off. The relation between the LCD data RAM
and segment/common pins is shows below.
LCD COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Data RAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EEH SEG1 SEG0
EFH SEG3 SEG2
F0H SEG5 SEG4
F1H SEG7 SEG6
F2H SEG9 SEG8
F3H SEG11 SEG10
F4H SEG13 SEG12
F5H SEG15 SEG14
F6H SEG17 SEG16
F7H SEG19 SEG18
F8H SEG21 SEG20
F9H SEG23 SEG22
FAH SEG25 SEG24
FBH SEG27 SEG26
FCH SEG29 SEG28
FFH SEG35 SEG34

Preliminary W928C73
-8-
Descriptions Of Special Function Registers(SFRS)
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B7 R 1No use
B6 Key_2 R 1Key_2 input. A corresponding
key_INT(INT3_3) can be enabled.
B5 Key_1 R 1Key_1 input. A corresponding
key_INT(INT3_3) can be enabled.
B4 Key_0 R 1Key_0 input. A corresponding
key_INT(INT3_3) can be enabled.
B3 DEC_ADDT RMatched Unmatched 1POCSAG address matched flag. A
corresponding INT(INT2) could be setup.
B2 F_ADR W 1Flash ROM serial address output
B1 DEC_
SYNVAL
RSYNC Lost SYNC 1Decoder synchronization condition
80H/P0
B0 F_data R/W 1Flash ROM data I/O
81H/SP B7~0 SP R/W 00000111 Stack pointer address. Always points to
top of the stack.
82H/DPL B7~0 DPL R/W 00000000 Low byte of 16 bit data pointer
83H/DPH B7~0 DPH R/W 00000000 High byte of 16 bit data pointer
84H/DPL1 B7~0 DPL1 R/W 00000000 Low byte of 16 bit data pointer 1
85H/DPH1 B7~0 DPH1 R/W 00000000 High byte of 16 bit data pointer 1
86H/DPS B0 DPS.0 R/W Pointer 1 Pointer 0 0Selection of data pointer, B7~1 are not
used
B7 SMOD 0No use. Clear to “o”after power_on reset
B6 SMOD0 0No use. Clear to “o”after power_on reset
B5 - 0No use. Clear to “o”after power_on reset
B4 - 0No use. Clear to “o”after power_on reset
B3 GF1 0General purpose user defined flag
B2 GF0 0General purpose user defined flag
B1 PD WEnable Disable 0Power down mode enable bit. Set this bit
to “1”will stop the CPU and oscillation.
87H/PCON
B0IDL WEnable Disable 0Idle mode enable bit. Set this bit to “1”will
stop the CPU clock, but the oscillator keep
running.
B7 TF1 R/W Overflow 0Timer 1 overflow flag,. TF1 will
automatically clear after INT service
routine.
B6 TR1 WEnable Disable 0Timer 1 enable
B5 TF0 R/W Overflow 0Timer 0 overflow flag, TF0 will
automatically clear after INT service
routine
B4 TR0 R/W Enable Disable 0Timer 0 enable
88H/TCON
B3 IE1
(Bat_fail)
R/W INT No INT 0Interrupt 1(battery fail INT) flag. Set by
hardware when a pre-selected INT level
(high or low) is detected on INT1. The INT
flag will keep only if the level is held.

Preliminary W928C73
Publication Release Date: June 2000
-9-Revision A1
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B2 IT1 R/W High level Low level 0Interrupt 1 level selection. Set by software
to specify high (>0.8V) / low (<0.8V) level
external INT 1 triggered.
B1 IE0 R/W INT No INT 0Interrupt 0 edge detect: Set by hardware
when an edge/level is detected on INT0.
This bit is cleared by hardware when the
service routine is vectored to only if the
interrupt was edge triggered. Otherwise it
follows the pin.
B0 IT0 R/W Falling
edge
Low level 0Interrupt 0 type selection. Set/cleared by
software to specify falling edge/ low level
triggered external inputs
B7 T1_GATE R/W 0
B6 T1_T R/W Timer 0
B5 T1_M1 R/W 0
B4 T1_M0 R/W 0
B3 T0_GATE R/W 0
B2 T0_T R/W Timer 0
B1 T0_M1 R/W 0
89H/TMOD
B0 T0_M0 R/W 0
Timer 1 & timer 0 control:
Tx_GATE (gating control):
When this bit is set, Timer/counter x will be
enabled if both INTx pin is high and TRx
control bit is set.
When this bit is cleared, Timerx is enabled
whenever TRx control bit is set.
Tx_C/T (timer or counter select):
When cleared, the timer is incremented by
internal clocks.
When set, the timer counts high-to-low
edges of the Tx pin.
M1 M0 Mode
0 0 8-bits with 5-bit pre-scalar.
0 1 16-bits, no pre-scalar.
1 0 8-bits with auto-reload from THx
1 1 (Timer 0) TL0 is an 8-bit
timer/counter controlled by the standard
Timer 0 control bits. TH0 is an 8-bit timer
only controlled by Timer 1 control bits.
(Timer 1) Timer/counter is stopped.
8AH/TL0 B7~0 TL0 R/W 00000000 Low byte of timer 0
8BH/TL1 B7~0 TL1 R/W 00000000 Low byte of timer 1
8CH/TH0 B7~0 TH0 R/W 00000000 High byte of timer 0
8DH/TH1 B7~0 TH1 R/W 00000000 High byte of timer 1
B7 WD1 R/W 0
B6 WD0 R/W 0
WD1 WD0 (watchdog timeout period)
0 0 Fs/214+512 clock
0 1 Fs/216+512 clock
1 0 Fs/218+512 clock
11 Fs/221+512 clock
B5 RTC1 R/W 0
8EH/CKCON
B4 RTC0 R/W 0
RTC1 RTC0 (RTC timeout period)
0 0 32 Hz for RTLCD = 74
0 1 8 Hz
1 0 2 Hz
1 1 1 Hz

Preliminary W928C73
-10 -
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B3 - R/W 1
B2 - R/W 1
Set B3 and B2 to 1 after power on reset.
B1 ELC R/W Enable Disable 1ELC: enable L_clock.
Keep this bit high for whole operation.
B0 EHC R/W 0Clear to “0”after reset.
B7 LED W
High
Low 1LED output port P1.7 (HI-drive)
B6 Buz_out W
High
Low 1Initial value of buzzer output pin
B5 Motor WHigh Low 1Motor output pin(Hi-drive)
B4 W 1No use
B3 DEC_RST W
High
Low 1Decoder reset control bit
B2 DEC_ON W
High
Low 1Decoder enable control bit
B1 DEC_
DATA
WHigh Low 1Decoder option setup data output control bit
90H/P1
B0 DEC_CLK WHigh Low 1Decoder option setup clock output control bit
B7 - W 0
B6 - W 0
B5 - W 0
B4 - W 0
B3 - W 0
B2 - W 0
Clear B7~B2 to 0 after power on reset.
B1 ENBT WEnable Disable 0Buzzer timer enable (used as a general timer)
91H/PBCON
B0 ENBUZ WEnable Disable 0Buzzer output enable
92H/TONE0 B7~0 TONE0 W 00000000 Auto reload value of buzzer timer
96H/PLC B7~0 PLC R 00000000 Low byte of program counter
97H/PLH B7~0 PLH R 00000000 High byte of program counter
A0H/P2 B7 P2.7 W/R
High
Low 1I/O P2.7
B6 P2.6 W/R 1
B5 P2.5 W/R 1
B4 P2.4 W/R 1
B6~B4 no use when LCD is on.
B3 P2.3 W/R
High
Low 1No use if SEG35~32 work as LCD segment.
I/O P2.3 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)
B2 P2.2 W/R
High
Low 1I/O P2.2 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)
B1 P2.1 W/R
High
Low 1No use if SEG35~32 work as LCD segment.
I/O P2.1 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)