Winbond W928C73 User manual

Preliminary W928C73
POCSAG MICROCONTROLLER
Publication Release Date: June 2000
-1-Revision A1
GENERAL DESCRIPTION
The W928C73 is a high performance 8 bits microcontroller with build-in POCSAG decoder and LCD
driver. It is possible to switch the normal mode, idle mode and power down mode for power saving
purpose. The W928C73 is an extended µC from standard 8031 (excluding UART) that it can be easily
applied to pager system or other telecommunication system.
FEATURES
•512, 1200 and 2400 bps POCSAG decoder
•6 independent user addresses
•Instruction set compatible with MCS51
•System clock
−OSC2: 76.8 KHz
•128 bytes on-chip fast RAM
•384 bytes on-chip MOVX RAM
•16K bytes on-chip program ROM
•32 ×32 bits on-chip flash RAM
•Timer
−Two 16-bit timer/counters
−One RTC timer
−One Watch-dog timer
−One Buzzer timer
•Four 8-bit bit-addressable I/O ports
•Three external interrupt source, INT0, INT1 (BAT_DET_INT), INT3 (KEY_INT)
•Battery low detector
•Battery detector
•Power fail detector
•Power down wake-up via external interrupts
•Two 16-bit Data Pointers (Selected by DPS.0)
•10 source, 10 vector interrupts structure with two priority-level interrupts
•Built-in programmable power-saving modes -Idle mode & Power-down mode
•Operating voltage range: 2.4V to 3.3V
•32 segment ×4 common, 1/3 bias, 1/4 duty LCD driver output
•Packaged in 64-pin LQFP
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Preliminary W928C73
-2-
PIN CONFIGURATION
W928C73
P1.5/MOTOR
P1.6/BUZZER
P1.7/LED
Vss
RESET
EA
TEST1
TEST2
P3.0
P
2.2
P
2.3
V
2.7
P
V
D
D
X
O
U
T
2
X
I
N
2
BL_RF
DI
BS1
BS2
BS3
P3.1 SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG29
SEG28
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
3
S
E
G
35
/ /
S
E
G
34
P
3.2
/
I
N
T
0
P
3.3
/
I
N
T
1
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
9
S
E
G
10
S
E
G
11
S
E
G
12
S
E
G
13
3
64 LQFP
P
0.4
P
0.5
P
0.6
/
K
E
Y
2
/
K
E
Y
1
/
K
E
Y
0
PSEN
P
2.4
2.6
P2.5 P

Preliminary W928C73
Publication Release Date: June 2000
-3-Revision A1
PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTIONS
VSS IGROUND: ground potential
RST
I H RESET: A low on this pin for two machine cycles while the oscillator is
running resets the device.
P1.5 OMotor output, hi-drive
P1.6 OBuzzer clock output, hi-drive
P1.7 OLED output, hi-drive
BL_RF IConnect to LVS of IF chip
DI IPOCSAG signal input
BS1 ORF control 1
BS2 ORF control 2
BS3 ORF control 3
EA
IExternal access enable pin. Should connect to VDD.
TEST1 INo connection. Test pin. Internal pull low
TEST2 INo connection. Test pin. Internal pull low
PSEN
ONo connection. Test pin.
P3.0 I/O Bit addressable general I/O port 3.0
P3.1 I/O Bit addressable general I/O port 3.1
P3.2/INT0 I/O Bit addressable general I/O port 3.2 or INT0 defined by SFR
P3.3/INT1 IBattery fail interrupt input. Connect to V1.5. If voltage potential of battery is
less than the 0.8V, the INT1 interrupt flag will be set.
SEG0 OLCD segment signal out
SEG1 OLCD segment signal out
SEG2 OLCD segment signal out
SEG3 OLCD segment signal out
SEG4 OLCD segment signal out
SEG5 OLCD segment signal out
SEG6 OLCD segment signal out
SEG7 OLCD segment signal out
SEG8 OLCD segment signal out
SEG9 OLCD segment signal out
SEG10 OLCD segment signal out
SEG11 OLCD segment signal out
SEG12 OLCD segment signal out
SEG13 OLCD segment signal out

Preliminary W928C73
-4-
Pin Descriptions, continued
SYMBOL TYPE DESCRIPTIONS
SEG14 OLCD segment signal out
SEG15 OLCD segment signal out
SEG16 OLCD segment signal out
SEG17 OLCD segment signal out
SEG18 OLCD segment signal out
SEG19 OLCD segment signal out
SEG20 OLCD segment signal out
SEG21 OLCD segment signal out
SEG22 OLCD segment signal out
SEG23 OLCD segment signal out
SEG24 OLCD segment signal out
SEG25 OLCD segment signal out
SEG26 OLCD segment signal out
SEG27 OLCD segment signal out
SEG28 OLCD segment signal out
SEG29 OLCD segment signal out
P2.2/SEG34 OLCD segment signal out
P2.3/SEG35 OLCD segment signal out
P2.4/VDD3ILCD voltage input (VDD)
P2.5 I/O I/O pin
P2.6 I/O I/O pin
P2.7 I/O I/O pin
COM0 OLCD common signal output pins.
COM1 OLCD common signal output pins.
COM2 OLCD common signal output pins.
COM3 OLCD common signal output pins.
P0.4 IBit addressable general I/O port 0.4 and Key_0 interrupt
P0.5 IBit addressable general I/O port 0.5 and Key_1 interrupt
P0.6 IBit addressable general I/O port 0.6 and Key_2 interrupt
VDD IPOWER SUPPLY: Supply voltage for operation.
XOUT2 OOutput pin for clock_2. It is the inversion of XIN2.
XIN2 IInput pin for clock_2
Note 1: I/O TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

Preliminary W928C73
Publication Release Date: June 2000
-5-Revision A1
BLOCK DIAGRAM
ALU Stack PointerPSW
ACC B
T1 register T2 register
Port
3
Port
1
Port
0
Port
2
128B MOV RAM
384B MOVX RAM
SFR
Instruction
Decoder &
Sequencer
Port
4~8
16KB
DPTR
DPTR 1
PC
Address REG
Address bus
Data bus
L_Clock
Clock Generator
System control
I
N
T
E
R
R
U
P
T
Timer 0
Timer 1
Buzzer Timer
RTC Timer
Watchdog Timer
RESET
program ROM
Power on &
power low
reset
XIN2 XOUT2
LCD
Driver
32x4
LCD_OFF
LCD_ON
P0.3
P0.7
P1.5
P1.7
P1.0
P1.2
P3.0
P3.3
P2.5
P2.7
P4.0~4.7
P5.0~5.7
P6.0~6.7
P7.0~7.7
P8.0~8.3
1K FLASH RAM

Preliminary W928C73
-6-
FUNCTIONAL DESCRIPTION
The W928C73 is a high performance 8 bits POCSAG microcontroller with build-in LCD driver and
POCSAG decoder. The uC is 8031 instruction set compatible with one addition: DEC DPTR (op-code
A5H, the DPTR is decreased by 1). The W928C73 has all the standard features of the 8031 except
the UART, and has a few extra peripherals and features like watchdog, RTC, buzzer timers, LCD
driver, and build-in POCSAG decoder.
The W928C73 features a faster running and better performance 8-bit CPU by reducing the machine
cycle duration from the standard 8031 period of twelve clocks to four clock cycles for the majority of
instructions. The W928C73 also provides dual Data Pointers (DPTRs) to speed up block data memory
transfers. In addition, the W928C73 contains on-chip 384B MOVX SRAM. It only can be accessed by
MOVX instruction; this on-chip data memory can be enabled by software commend.
Memory Organization
The W928C73 separates the memory into two sections, the Program Memory and Data Memory. The
Program Memory is used to store the instruction op-codes, while the Data Memory is used for storing
data or memory mapped devices. The
EA
pin must connect to high to access on-chip program ROM.
16 K bytes
Program
Memory
System testing
0000H
0080H
0200H
3FFFH
Interrupt vector 0000H
017FH
384 Bytes
Data
MOVX RAM
00H
7FH Direct & indirect
Addressing RAM
LCD RAM
EEH
FFH
80H
FFH Direct addressing
SFR
Program Memory Internal Data Memory Internal Data Memory Special Function Register
On-chip memory space of W928C73
Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP),
which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the
return address is placed on the stack. There is no restriction as to where the stack can begin in the
RAM. By default however, the Stack Pointer contains 07H at reset. The user can then change this to
any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and
then address saved onto the stack. Conversely, while popping from the stack the contents will be read
first, then the SP is decreased.

Preliminary W928C73
Publication Release Date: June 2000
-7-Revision A1
LCD Data Area
When LCD ON, the indirect RAM area EEH−FFH work as the LCD data RAM (LCD00−LCD35).
Instruction such as "MOV @R0, #I" (Where R0 = EEH−FFH) are used to control the LCD data RAM.
The data in the LCD data RAM (bit7−bit0) are transferred to the segment output pins automatically
without program control. When the bit value of the LCD data RAM is "1", the LCD is turned on. When
the bit value of the LCD data RAM is "0", LCD is turned off. The relation between the LCD data RAM
and segment/common pins is shows below.
LCD COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Data RAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EEH SEG1 SEG0
EFH SEG3 SEG2
F0H SEG5 SEG4
F1H SEG7 SEG6
F2H SEG9 SEG8
F3H SEG11 SEG10
F4H SEG13 SEG12
F5H SEG15 SEG14
F6H SEG17 SEG16
F7H SEG19 SEG18
F8H SEG21 SEG20
F9H SEG23 SEG22
FAH SEG25 SEG24
FBH SEG27 SEG26
FCH SEG29 SEG28
FFH SEG35 SEG34

Preliminary W928C73
-8-
Descriptions Of Special Function Registers(SFRS)
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B7 R 1No use
B6 Key_2 R 1Key_2 input. A corresponding
key_INT(INT3_3) can be enabled.
B5 Key_1 R 1Key_1 input. A corresponding
key_INT(INT3_3) can be enabled.
B4 Key_0 R 1Key_0 input. A corresponding
key_INT(INT3_3) can be enabled.
B3 DEC_ADDT RMatched Unmatched 1POCSAG address matched flag. A
corresponding INT(INT2) could be setup.
B2 F_ADR W 1Flash ROM serial address output
B1 DEC_
SYNVAL
RSYNC Lost SYNC 1Decoder synchronization condition
80H/P0
B0 F_data R/W 1Flash ROM data I/O
81H/SP B7~0 SP R/W 00000111 Stack pointer address. Always points to
top of the stack.
82H/DPL B7~0 DPL R/W 00000000 Low byte of 16 bit data pointer
83H/DPH B7~0 DPH R/W 00000000 High byte of 16 bit data pointer
84H/DPL1 B7~0 DPL1 R/W 00000000 Low byte of 16 bit data pointer 1
85H/DPH1 B7~0 DPH1 R/W 00000000 High byte of 16 bit data pointer 1
86H/DPS B0 DPS.0 R/W Pointer 1 Pointer 0 0Selection of data pointer, B7~1 are not
used
B7 SMOD 0No use. Clear to “o”after power_on reset
B6 SMOD0 0No use. Clear to “o”after power_on reset
B5 - 0No use. Clear to “o”after power_on reset
B4 - 0No use. Clear to “o”after power_on reset
B3 GF1 0General purpose user defined flag
B2 GF0 0General purpose user defined flag
B1 PD WEnable Disable 0Power down mode enable bit. Set this bit
to “1”will stop the CPU and oscillation.
87H/PCON
B0IDL WEnable Disable 0Idle mode enable bit. Set this bit to “1”will
stop the CPU clock, but the oscillator keep
running.
B7 TF1 R/W Overflow 0Timer 1 overflow flag,. TF1 will
automatically clear after INT service
routine.
B6 TR1 WEnable Disable 0Timer 1 enable
B5 TF0 R/W Overflow 0Timer 0 overflow flag, TF0 will
automatically clear after INT service
routine
B4 TR0 R/W Enable Disable 0Timer 0 enable
88H/TCON
B3 IE1
(Bat_fail)
R/W INT No INT 0Interrupt 1(battery fail INT) flag. Set by
hardware when a pre-selected INT level
(high or low) is detected on INT1. The INT
flag will keep only if the level is held.

Preliminary W928C73
Publication Release Date: June 2000
-9-Revision A1
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B2 IT1 R/W High level Low level 0Interrupt 1 level selection. Set by software
to specify high (>0.8V) / low (<0.8V) level
external INT 1 triggered.
B1 IE0 R/W INT No INT 0Interrupt 0 edge detect: Set by hardware
when an edge/level is detected on INT0.
This bit is cleared by hardware when the
service routine is vectored to only if the
interrupt was edge triggered. Otherwise it
follows the pin.
B0 IT0 R/W Falling
edge
Low level 0Interrupt 0 type selection. Set/cleared by
software to specify falling edge/ low level
triggered external inputs
B7 T1_GATE R/W 0
B6 T1_T R/W Timer 0
B5 T1_M1 R/W 0
B4 T1_M0 R/W 0
B3 T0_GATE R/W 0
B2 T0_T R/W Timer 0
B1 T0_M1 R/W 0
89H/TMOD
B0 T0_M0 R/W 0
Timer 1 & timer 0 control:
Tx_GATE (gating control):
When this bit is set, Timer/counter x will be
enabled if both INTx pin is high and TRx
control bit is set.
When this bit is cleared, Timerx is enabled
whenever TRx control bit is set.
Tx_C/T (timer or counter select):
When cleared, the timer is incremented by
internal clocks.
When set, the timer counts high-to-low
edges of the Tx pin.
M1 M0 Mode
0 0 8-bits with 5-bit pre-scalar.
0 1 16-bits, no pre-scalar.
1 0 8-bits with auto-reload from THx
1 1 (Timer 0) TL0 is an 8-bit
timer/counter controlled by the standard
Timer 0 control bits. TH0 is an 8-bit timer
only controlled by Timer 1 control bits.
(Timer 1) Timer/counter is stopped.
8AH/TL0 B7~0 TL0 R/W 00000000 Low byte of timer 0
8BH/TL1 B7~0 TL1 R/W 00000000 Low byte of timer 1
8CH/TH0 B7~0 TH0 R/W 00000000 High byte of timer 0
8DH/TH1 B7~0 TH1 R/W 00000000 High byte of timer 1
B7 WD1 R/W 0
B6 WD0 R/W 0
WD1 WD0 (watchdog timeout period)
0 0 Fs/214+512 clock
0 1 Fs/216+512 clock
1 0 Fs/218+512 clock
11 Fs/221+512 clock
B5 RTC1 R/W 0
8EH/CKCON
B4 RTC0 R/W 0
RTC1 RTC0 (RTC timeout period)
0 0 32 Hz for RTLCD = 74
0 1 8 Hz
1 0 2 Hz
1 1 1 Hz

Preliminary W928C73
-10 -
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B3 - R/W 1
B2 - R/W 1
Set B3 and B2 to 1 after power on reset.
B1 ELC R/W Enable Disable 1ELC: enable L_clock.
Keep this bit high for whole operation.
B0 EHC R/W 0Clear to “0”after reset.
B7 LED W
High
Low 1LED output port P1.7 (HI-drive)
B6 Buz_out W
High
Low 1Initial value of buzzer output pin
B5 Motor WHigh Low 1Motor output pin(Hi-drive)
B4 W 1No use
B3 DEC_RST W
High
Low 1Decoder reset control bit
B2 DEC_ON W
High
Low 1Decoder enable control bit
B1 DEC_
DATA
WHigh Low 1Decoder option setup data output control bit
90H/P1
B0 DEC_CLK WHigh Low 1Decoder option setup clock output control bit
B7 - W 0
B6 - W 0
B5 - W 0
B4 - W 0
B3 - W 0
B2 - W 0
Clear B7~B2 to 0 after power on reset.
B1 ENBT WEnable Disable 0Buzzer timer enable (used as a general timer)
91H/PBCON
B0 ENBUZ WEnable Disable 0Buzzer output enable
92H/TONE0 B7~0 TONE0 W 00000000 Auto reload value of buzzer timer
96H/PLC B7~0 PLC R 00000000 Low byte of program counter
97H/PLH B7~0 PLH R 00000000 High byte of program counter
A0H/P2 B7 P2.7 W/R
High
Low 1I/O P2.7
B6 P2.6 W/R 1
B5 P2.5 W/R 1
B4 P2.4 W/R 1
B6~B4 no use when LCD is on.
B3 P2.3 W/R
High
Low 1No use if SEG35~32 work as LCD segment.
I/O P2.3 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)
B2 P2.2 W/R
High
Low 1I/O P2.2 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)
B1 P2.1 W/R
High
Low 1No use if SEG35~32 work as LCD segment.
I/O P2.1 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)

Preliminary W928C73
Publication Release Date: June 2000
-11 -Revision A1
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B0 P2.0 W/R
High
Low 1No use if SEG35~32 work as LCD segment.
I/O P2.0 value if SEG35~32 work as
P2.3~P2.0 function (P2M (A1.1H) = 0)
B7 LCDWAVE WA Type B Type 0
B6 - W 0
B5 - W 0
B4- W 0
Clear B7~B4 to “0”after reset.
Default LCDWAVE =0 (B type)
B3 FLCD1 W 0
B2 FLCD0 W0
FLCD1 FLCD0 LCD frequency
0 0 512 Hz, set RTLCD = 74
0 1 256 Hz
1 0 128 Hz
1 1 64 Hz
LCD scan rate = LCD frequency/ 4
B1 P2M WSEG out P2 0P2.0~2.3/SEG32~35 pin function selection.
This bit can only be set while LCD is on.
While set to 1, these 4 pins work as
SEG32~35 output. If clear to 0, these 4 pins
will work as P2.0~2.3.
A1H/LCDR
B0 LCDON WLCD ON LCD OFF 0LCD driver enable control
A2H/RTLCD B7~0 RTLCD W 11111111 RTC timer value. Set RTLCD = 74 for 76.8
KHz crystal
B7 EA WEnable Disable 0Global interrupt enable control
B6 ES1 WEnable Disable 0POCSAG receiving buffer interrupt enable
control
B5 - W 0Clear this bit to 0 after power on reset
B4 - W 0Clear this bit to 0 after power on reset
B3 ET1 WEnable Disable 0Timer 1 interrupt enable control
B2 EX1 WEnable Disable 0External interrupt 1 (battery fail INT) enable
control
B1 ET0 WEnable Disable 0Timer 0 interrupt enable control
A8H/IE
B0 EX0 WEnable Disable 0External interrupt 0 enable control
B7
INT33
WEnable Disable 0Clear this bit to 0 after reset
B6 INT32 WEnable Disable 0Enable INT32 (key2)
B5 INT31 WEnable Disable 0Enable INT31 (key1)
B4 INT30 WEnable Disable 0Enable INT30 (key0)
B3 - W 0
B2 - W 0
B1 - W 0
AAH/SDTMF
B0 - W 0
Clear B3~B0 after reset

Preliminary W928C73
-12 -
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B7 DEC_BL RBattery
low
Battery
OK
1Battery condition.
If battery voltage is lower than 1 volt, this bit
will change to 1, otherwise this bit will be 0.
This bit works only if BL_RF pin is connect to
IF IC LVS output.
B6 F_Mode WHigh Low 1Flash ROM mode control bit
B5 F_CLK WHigh Low 1Flash ROM clock output bit
B4 F_ctrl WHigh Low 1Flash ROM control bit
B3
Bat_fail/
INT1
RBattery
OK
Battery
fail or no
battery
1Battery fail condition.
If battery voltage is lower than 0.8 volt, this bit
will change to 0, otherwise this bit will be 1.
An additional level interrupt(INT1) can be
enabled to monitor this bit.
B2 P3.2/INT0 R/W 1I/O P3.2 & external interrupt 0 input
B1 P3.1 R/W 1I/O P3.1
B0H/P3
B0 P3.0 R/W 1I/O P3.0
B2/HB B7~0 HB R/W 00000000 High byte address of "MOVX @Ri"
B7 BTF WHigh Low 0Buzzer timer interrupt priority level
B6 PS1 WHigh Low 0POCSAG receiving buffer interrupt priority
level
B5 - W 0Clear this bit to 0 after reset
B4 - W 0Clear this bit to 0 after reset
B3 PT1 WHigh Low 0Timer 1 interrupt priority level
B2 PX1 WHigh Low 0Interrupt 1 (INT1) interrupt priority level
B1 PT0 WHigh Low 0Timer 0 interrupt priority level
B8H/IP
B0 PX0 WHigh Low 0Interrupt 0 (INT0) interrupt priority level
B7 - W 0
B6 - W 0
B5 - W 0
B4 - W 0
Clear B7~B4 to 0 after reset
B3 OVFH R 0No use
B2 OVFL R 0OSC2 clock stable flag
B1 SIF R 0POCSAG receiving buffer interrupt request
flag
C0H/CSCON
B0 REN1 WEnable Disable 0POCSAG receiving buffer enable control
C1H/SMODE B7~0 SMODE W 00000000 POCSAG mode control, Set SMODE =
11101101 after reset
C2H/SB1 B7~0 SB1 R 00000000 POCSAG receiving buffer 1
C3H/SB2 B7~0 SB2 R 00000000 POCSAG receiving buffer 2

Preliminary W928C73
Publication Release Date: June 2000
-13 -Revision A1
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
C4H/SB3 B7~0 SB3 R 00000000 POCSAG receiving buffer 3
C9H/T2MOD B7 DME0 WOn-chip External 1MOVX RAM selection (384 bytes), set to 1
after reset
B6 - W 0Clear this bit to "0" after reset
B5 - W 0Clear this bit to "0" after reset
B4 - W 0Clear this bit to "0" after reset
B3 - W 0Clear this bit to "0" after reset
B2 TONESEL WPWM 50-50duty 0Buzzer tone duty control
B1 - W 0Clear this bit to "0" after reset
B0 - W 0Clear this bit to "0" after reset
B7 CY R 0Carry flag:
Set for an arithmetic operation which results
in a carry being generated from the ALU. It
is also used as the accumulator for the bit
operations.
B6 AC R 0Auxiliary carry: Set when the previous
operation resulted in a carry (during
addition) or a borrowing (during subtraction)
from the high order nibble.
B5 F0 R/W 0User define flag
B4 RS1 R/W 0
B3 RS0 R/W 0
RS1 RS0 Register bank selection
0 0 Bank 0 00-07(B0-B7)
0 1 Bank 1 08-0F(B0-B7)
1 0 Bank 2 10-17(B0-B7)
1 1 Bank 3 18-1F(B0-B7)
B2 OV R 0Overflow flag:
Set when a carry was generated from the
seventh bit but not from the 8th bit as a
result of the previous operation or vice-
versa.
B1 F1 R/W 0User defined flag
D0H/PSW
B0 P R 0Parity flag:
Set/cleared by hardware to indicate
odd/even number of 1's in the accumulator.
B7 RTIF R 0RTC interrupt request flag
B6 POR R/W XPower-on reset flag:
Hardware will set this flag on a power up
condition. This flag can be read or written by
software. A write by software is the only way
to clear this bit once it is set.
B5 - R/W 0Clear this be after reset
D8H/WDCON
B4 - R/W 0Clear this be after reset

Preliminary W928C73
-14 -
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
B3 WDIF R 0Watchdog Timer Interrupt Flag:
If the watchdog interrupt is enabled, hardware will set this
bit to indicate that the watchdog interrupt has occurred. If
the interrupt is not enabled, then this bit indicates that the
time-out period has elapsed.
B2 WTRF XWatchdog Timer Reset Flag:
Hardware will set this bit when the watchdog timer causes
a reset. Software can read it but must clear it manually. A
power-fail reset will also clear the bit. This bit helps
software in determining the cause of a reset. If EWT = 0,
the watchdog timer will have no affect on this bit.
B1 EWT XEnable Watchdog timer Reset: Setting this bit will enable
the Watchdog timer Reset function.
D8H/WDCON
B0 RWT 0Reset Watchdog Timer: This bit helps in putting the
watchdog timer into a know state. It also helps in resetting
the watchdog timer before a time-out occurs. Failing to set
the EWT before time-out will cause an interrupt, if EWDI
(EIE.4) is set, and 512 clocks after that a watchdog timer
reset will be generated if EWT is set. This bit is self-
clearing.
B7 P0IO.7 W 0R/W control for P0.7 (key3):
No use, clear this bit to 0 after.
B6 P0IO.6 W 0R/W control for P0.6 (key2):
1: input mode without pull high R
0: output mode or input with pull high R
Clear this bit after reset for key2 input with pull high R
function.
B5 P0IO.5 W 0R/W control for P0.5 (key1):
1: input mode without pull high R
0: output mode or input with pull high R
Clear this bit after reset for key1 input with pull high R
function.
B4 P0IO.4 W 0R/W control for P0.4 (key0):
1: input mode without pull high R
0: output mode or input with pull high R
Clear this bit after reset for key0 input with pull high R
function.
B3 P0IO.3 W 0R/W control for P0.3:
Set this bit to “1”after reset for DEC_ADDT input
B2 P0IO.2 W 0R/W control for P0.2:
Clear this bit to “0”after reset for F_ADR output function
B1 P0IO.1 W 0R/W control for P0.1:
Set this bit to “1”after reset for DEC_SYNVAL input
D9H/P0IO
B0 P0IO.0 W 0R/W control for P0.0:
Set this bit to “1”after reset.
For read-in F_data, set this bit to ”1”.
For write-out F_data, clear this bit to “0”.

Preliminary W928C73
Publication Release Date: June 2000
-15 -Revision A1
Descriptions Of Special Function Registers (SFRS), continued
ADDRESS
/NAME BIT BIT NAME R/W 10INITIAL FUNCTION
DAH/P1IO B7~0 P1IO W 00000000 Bit addressable R/W control for P1:
1: input mode without pull high R
0: output mode or input with pull high R
Set DA to “00000000 “after r
eset, since P1
are all output mode.
DBH/P2IO B7~0 P2IO W 00000000 Bit addressable R/W control for P2
1: input mode without pull high R
0: output mode or input with pull high R
Set DB to “X0000000 “after reset.
The value of P2IO.7 depends on the functi
on
of P2.7 (input of output)
DCH/P3IO B7~0 P3IO W 00000000 Bit addressable R/W control for P3
1: input mode without pull high R
0: output mode or input with pull high R
Set DC to “10001XXX “after reset.
The values of P3IO.2~P3IO.0 depend on the
functions of P3.2~P3.0 (input of output)
DDH/P48IO B4 P8IO W 0
B3 P7IO W 0
B2 P6IO W 0
B1 P5IO W 0
B0 P4IO W 0
Clear DDH to “00”after reset.
E0H/ACC B7~0 ACC R/W 00000000 Accumulator
E8H/EIE B7 ERTLC WEnable Disable 0RTC timer and LCD clock enable
B6 EBTI WEnable Disable 0Buzzer timer interrupt enable
B5 ERTI WEnable Disable 0RTC timer interrupt enable
B4 EWDI WEnable Disable 0Watchdog timer interrupt enable
B3 IE3 R 0External interrupt 3 request flag
B2 EX3 WEnable Disable 0External interrupt 3 enable
B1 IE2 R 0External interrupt 2 request flag
B0 EX2 WEnable Disable 0External interrupt 2 enable
F0/B B7~0 B R/W 00000000 B register
F8H/EIP B7 SMSC WH_clock L_clock 0System clock selection
B6 PBTI WHigh Low 0Buzzer timer interrupt priority
B5 PRTI W
High
Low 0RTC timer interrupt priority
B4 PWDI W
High
Low 0Watchdog timer interrupt priority
B3 IT3 WFalling Rising 0INT3 (key_INT) trigger edge selection
B2 PX3 W
High
Low 0External interrupt 3 priority
B1 IT2 WFalling Rising 0INT2 (ADDT) trigger edge selection
B0 PX2 W
High
Low 0External interrupt 2 priority
Notes:
1. The SFRs in bold are bit addressable, others are byte addressable.
2. The SFRs can only be accessed by direct addressing.
3. P2.4 is pulled high internal, when external use VDD to connect p2.4 for LCD. The S/W must do the following instruction mov
P2IO,#10H and clr P2.4
4. P0IO~P8IO default are output mode(0), when need input mode then set P0IO~P8IO are 1.

Preliminary W928C73
-16 -
Data Pointers
The original 8031 had only one 16-bit Data Pointer (DPL, DPH). In the W928C73, there is an
additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which
were unused in the original 8031. In addition there is an additional instruction, DEC DPTR (op-code
A5H), which helps in improving programming flexibility for the user.
MOVX Instruction
The W928C73, like the standard 8031, uses the MOVX instruction to access the external Data
Memory. The external data memory includes 384 bytes on-chip data RAM.
The MOVX instruction is of two types, the MOVX @Ri and MOVX @DPTR. In the MOVX @Ri, the
address of the external data comes from two sources. The lower 8-bits of the address are stored in the
Ri register of the selected working register bank. The upper 8-bits of the address are store in the HB
register (B2h of SFR). In the MOVX @DPTR type, the full 16-bit address is supplied by the Data
Pointer.
Since the W928C73 has two Data Pointers, DPTR and DPTR1, the user has to select between the
two by setting or clearing the DPS bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR,
which exists at location 86h. Rest bits in this SFR have no effect, and are set to 0. When DPS is 0,
then DPTR is selected, and when set to 1, DPTR1 is selected. The user can switch between DPTR
and DPTR1 by toggling the DPS bit. The quickest way to do this is by the INC instruction. The HB
register and dual Data Pointers will provide enough flexibility for performing block move operations.
SYSTEM CLOCK
The W928C73 provides one oscillation circuit, OSC2 -L_clock (76.8 KHz), for the whole system.
During the power on reset, the L_clock is activated. The RTC Timer, WDT timer, buzzer output and
LCD frequency clock sources directly come from L_clock. The CPU, timer0, timer1 and interrupt
operation are based on the machine cycle. The machine cycle consists of four oscillator clock
sequence (4 states).
ELC is the control bit to activate the L_clock. The OVFL is the clock stable flag for the L_clock. The
power on state of system is ELC = 1. For proper operation, the L_clock is suggested to turn on all the
time. The clock architecture of the system is shown below.
L_Clock
/PD
/IDL CPU
WDT,RTC,
LCD, BUZ
Timer/Counter 0, 1
Interrupt
ELC
OSC2
/4

Preliminary W928C73
Publication Release Date: June 2000
-17 -Revision A1
Power Management
Operation Mode (Normal Mode)
After the power on reset, the W928C73 will enter the normal operation mode. In this mode, all the
system is operable with the main clock.
Idle Mode
While setting the PCON.0 to 1, the system will go to idle mode. In idle mode, the CPU is stopped but
rest of the system and the oscillator is still running as previous state The idle mode can be waked up
by all the interrupt sources.
Power Down Mode
The instruction setting PCON.1 is the last executed prior to going into the Power-down mode. In
Power-down mode the oscillator is stopped. The contents of the on-chip RAM and SFRS are
preserved. The port pins output the values held by their respective SFRs. PSEN are held LOW.
In Power-down mode VDD may be reduced to minimize power consumption. However, the supply
voltage must not be reduce until Power-down mode is active, and must be restored before the
hardware reset is applied and frees the oscillator. Reset must be held active until the oscillator has
restarted and stabilized.
The wake-up operation of W928C73 after power-down mode has two approaches, wake-up using
external interrupt INT0, INT1or wake-up using RESET. For INT0 or INT1 wake-up, the controller will
enter the interrupt service routine and is in the slow operation mode and the contents of the on-chip
RAM and SFRS are preserved. For RESET wake-up, the RESET pin has to be kept HIGH for a
minimum of 24 oscillator periods, the uC will enter the power on reset state after wake up.
OPERATION MODE NORMAL MODE IDLE POWER DOWN
Setting Command Power on reset
Idle mode wake up
3. Power down mode wake up
Set PCON.0 to
1Set PCON.1 to1
Oscillator L_clock on Clock keeps
oscillation Clock stops
CPU Operable Stopped Stopped
Interrupt All interrupt operable INT0, INT1
Watchdog Timer Operable Stopped
Timer0, Timer1 L_clock/4 operable Stopped
RTCL_clock operable Stopped
Buzzer Timer L_clock operable Stopped
Release Condition All enabled
interrupts 1. RESET
2. External interrupt
INT0, INT1
Release Time 214 main clock

Preliminary W928C73
-18 -
Timer 0 & 1
The W928C73 has two 16-bit Timer. Each of these Timer has two 8 bit registers which form the 16 bit
counting register. For Timer 0 they are TH0, the upper 8 bits register, and TL0, the lower 8 bit register.
Similarly Timer 1 has two 8 bit registers, TH1 and TL1. The two can be configured to operate as
timers, counting machine cycles.
The timer clock is 1/4 of the system clock. The T0 and T1 inputs are sampled in every machine cycle
at C4. If the sampled value is high in one machine cycle and low in the next, then a valid high to low
transition on the pin is recognized and the count register is incremented. Since it takes two machine
cycles to recognize a negative transition on the pin, the maximum rate at which counting will take
place is 1/24 of the master clock frequency. In the "Timer" mode, the recognized negative transition on
pin T0 and T1 can cause the count register value to be updated only in the machine cycle following
the one in which the negative edge was detected.
The "Timer" function is selected by the "C/T" bit in the TMOD Special Function Register. Each Timer
has one selection bit for its own; bit 2 of TMOD selects the function for Timer 0 and bit 6 of TMOD
selects the function for Timer 1. In addition each Timer can be set to operate in any one of four
possible modes. The mode selection is done by bits M0 and M1 in the TMOD SFR.
Mode 0
In Mode 0, the timer act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we have a
13 bit timer. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The upper 3 bits of
TLx are ignored.
The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx
moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves
from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if
TRx is set and either GATE = 0 or
INT
x = 1. When C/
T
is set to 0, then it will count clock cycles,
and if C/
T
is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for
timer 1. When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The
timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that
when used as a timer, the time-base is clock cycles/4.
System Clock 1/4
TR0 = TCON.4
(TR1 = TCON.6)
INT1 = P3.3
INT0 = P3.2
GATE = TMOD.3
(GATE = TMOD.7)
TL0
(TL1)
00
01 TH0
(TH1)
Interrrpt
TF0
(TF1)
C/T = TMOD.2
(C/T = TMOD.6) M1, M0 = TMOD1, TMOD0
(M1, M0 = TMOD5, TMOD4)
Timer 1 functions are shown in brakets
Mode 0 and 1 of Timer 0 & 1

Preliminary W928C73
Publication Release Date: June 2000
-19 -Revision A1
Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
Mode 2
In Mode 2, the timer is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count register, while
THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit in TCON is
set and TLx is reloaded with the contents of THx, and the counting process continues from here. The
reload operation leaves the contents of the THx register unchanged. Counting is enabled by the TRx
bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1, mode 2 allows
counting of either clock cycles (clock/4) or pulses on pin Tn.
System Clock 1/4
TR0 = TCON.4
(TR1 = TCON.6)
INT1 = P3.3
INT0 = P3.2
GATE = TMOD.3
(GATE = TMOD.7)
TL0
(TL1)
TH0
(TH1)
Interrrpt
TF0
(TF1)
C/T = TMOD.2
(C/T=TMOD.6)
Timer 1 functions are shown in brakets
Mode 2 of Timer 0 & 1
Mode 3
Mode 3 has different operating methods for the two timer. For timer 1, mode 3 simply freezes the
counter. Timer 0, however, configures TL0 and TH0 as two separate 8 bit count registers in this mode.
The logic for this mode is shown in the figure. TL0 uses the Timer 0 control bits C/T, GATE, TR0, INT0
and TF0. The TL0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin
T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle counter (clock/12 or clock/4) and
takes over the use of TR1 and TF1 from Timer 1. Mode 3 is used in cases where an extra 8 bit timer is
needed. With Timer 0 in Mode 3, Timer 1 can still be used in Modes 0, 1 and 2., but its flexibility is
somewhat limited. While its basic functionality is maintained, it no longer has control over its overflow
flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer and retains the use of GATE and
INT1 pin. In this condition it can be turned on and off by switching it out of and into its own Mode 3.

Preliminary W928C73
-20 -
System Clock 1/4
TR0 = TCON.4
INT0 = P3.2
GATE = TMOD.3
TL0
TH0
Interrrpt
TF0
C/T = TMOD.2
Interrrpt
TF1
TR1 = TCON.6
Mode 3 of Timer 0 & 1
Watchdog Timer
The watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. When the time out occurs a request flag is
set, which can cause an interrupt or a system reset depend on the EWDI or EWT enable SFR. The
interrupt and reset functions are independent of each other and may be used separately or together
depending on the users software. The watchdog timer should first be restarted by using RWT. This
ensures that the timer starts from a known state.
L_Clock Divider1 Fosc/8192
Fosc=76.8KHz
9.375Hz
WD1~0
Selector
WDIF
RWT
WD1 WD0
Interrupt
4.64
Hz 2.34 Hz 1.17 Hz 0.59 Hz 0.29 HZ 0.15 Hz 0.07 Hz 0.04 Hz
EWDI
512 clock
delay
EWT
WTRF
Reset
divider2
WDIF:D8.3H
EWT:D8.1H
RWT:D8.0H
WTRF:D8.2H EWDI:E8.4H WD1, WD0:8E.7H, 8E.6H
Buzzer Timer
The W928C73 provides a buzzer timer. The buzzer timer can output a single tone signal to the BUZ
pin that frequency range from 150Hz to 38400 Hz.
The operation of buzzer timer is as following. First set the proper value of tone0 then set the ENBUZ
to 1, the uC will output the corresponding frequency (50% duty cycle) to P1.6/BUZ output pin. The
timer can also generate different duty cycle to control the buzzer volume.