Winbond W90P710 Operating instructions

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Table No.: 1200-0003-07-A
W90P710 Programming Guide
Revision 2.1
01/06/2006

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The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
Revision History
Revision Date Comment
1.0 08/30/2005 Initial Version for W90P710
2.0 Major Revision
2.1 01/06/2006 Modify some contents and re-order the
sections

NO: W90P710 Programming Guide VERSION: 2.1 PAGE: 3
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distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
Table of Contents
1Overview...................................................................................................................................... 15
1.1 Features ............................................................................................................................... 18
1.1.1 Architecture ................................................................................................................... 18
1.1.2 External Bus Interface ................................................................................................... 18
1.1.3 Instruction and Data Cache ........................................................................................... 18
1.1.4 Ethernet MAC Controller................................................................................................ 18
1.1.5 DMA Controller .............................................................................................................. 19
1.1.6 USB Host Controller ...................................................................................................... 19
1.1.7 USB Device Controller................................................................................................... 19
1.1.8 SDIO Host Controller ..................................................................................................... 19
1.1.9 LCD Controller............................................................................................................... 20
1.1.10 2 Channel AC97/I2S Audio Codec Host Interface ......................................................... 21
1.1.11 UART............................................................................................................................. 21
1.1.12 Timers............................................................................................................................ 21
1.1.13 Advanced Interrupt Controller........................................................................................ 21
1.1.14 GPIO ............................................................................................................................. 22
1.1.15 Real Time Clock ............................................................................................................ 22
1.1.16 Smart Card Host Interface ............................................................................................. 22
1.1.17 I2C Master ..................................................................................................................... 23
1.1.18 Universal Serial Interface (USI) ..................................................................................... 23
1.1.19 4-Channel PWM ............................................................................................................ 23
1.1.20 Keypad Interface ........................................................................................................... 24
1.1.21 PS2 Host Interface Controller ........................................................................................ 24
1.1.22 Power Management ...................................................................................................... 24
2EBI (External Bus Interface) ........................................................................................................ 25
2.1 Overview............................................................................................................................... 25
2.2 Block Diagram ...................................................................................................................... 26
2.2.1 SDRAM interface........................................................................................................... 26
2.3 Registers .............................................................................................................................. 27
2.4 Functional Descriptions ........................................................................................................ 27
2.4.1 EBI Control Register (EBICON)..................................................................................... 27

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Table No.: 1200-0003-07-A
2.4.2 ROM/Flash control register............................................................................................ 28
2.4.3 SDRAM configuration registers ..................................................................................... 29
2.4.4 External I/O control registers ......................................................................................... 30
2.4.5 A system memory initialization example flow chart........................................................ 30
2.4.6 REMAPPING ................................................................................................................. 32
3Cache Controller.......................................................................................................................... 35
3.1 Overview............................................................................................................................... 35
3.2 Block Diagram ...................................................................................................................... 36
3.3 Registers .............................................................................................................................. 38
3.4 Functional Descriptions ........................................................................................................ 38
3.4.1 On-Chip RAM ................................................................................................................ 38
3.4.2 Non-Cacheable Area ..................................................................................................... 39
3.4.3 Cache Flushing.............................................................................................................. 39
3.4.4 Cache Enable and Disable ............................................................................................ 39
3.4.5 Cache Load and Lock.................................................................................................... 40
3.4.6 Cache Unlock ................................................................................................................ 41
4EMC (Ethernet MAC Controller) .................................................................................................. 42
4.1 Overview............................................................................................................................... 42
4.2 Block Diagram ...................................................................................................................... 43
4.3 Registers .............................................................................................................................. 44
4.3.1 EMC Control registers .................................................................................................. 44
4.3.2 EMC Status Registers ................................................................................................... 45
4.4 Functional Descriptions ........................................................................................................ 45
4.4.1 Initialize Rx Buffer Descriptors....................................................................................... 45
4.4.2 Initialize Tx Buffer Descriptors ....................................................................................... 48
4.4.3 MII ................................................................................................................................. 50
4.4.4 Control Frames.............................................................................................................. 52
4.4.5 Packet Processing......................................................................................................... 52
5GDMA .......................................................................................................................................... 58
5.1 Overview............................................................................................................................... 58
5.2 Block Diagram ...................................................................................................................... 59
5.3 Registers .............................................................................................................................. 60
5.4 Functional Descriptions ........................................................................................................ 60

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distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
5.4.1 GDMA Configuration ..................................................................................................... 60
5.4.2 Transfer Count............................................................................................................... 62
5.4.3 Transfer Termination ..................................................................................................... 63
5.4.4 GDMA operation started by software............................................................................. 63
5.4.5 GDMA operation started by nXDREQ ........................................................................... 65
5.4.6 Fixed Address................................................................................................................ 66
5.4.7 Block Mode Transfer ..................................................................................................... 66
5.4.8 Single Mode Transfer .................................................................................................... 66
5.4.9 Demand Mode Transfer................................................................................................. 66
6USB Host Controller..................................................................................................................... 68
6.1 Overview............................................................................................................................... 68
6.2 Registers Map....................................................................................................................... 69
6.3 Block Diagram ...................................................................................................................... 70
6.4 Data Structures..................................................................................................................... 71
6.4.1 Endpoint Descriptor (ED) Lists ...................................................................................... 72
6.4.2 Transfer Descriptor........................................................................................................ 73
6.4.3 Host Controller Communication Area ............................................................................ 75
6.5 Programming Note................................................................................................................76
6.5.1 Initialization.................................................................................................................... 76
6.5.2 USB States .................................................................................................................... 77
6.5.3 Add/Remove Endpoint Descriptors................................................................................ 78
6.5.4 Add/Remove Transfer Descriptors ................................................................................ 80
6.5.5 IRP Processing.............................................................................................................. 82
6.5.6 Interrupt Processing ...................................................................................................... 84
6.5.7 Done Queue Processing................................................................................................ 88
6.5.8 Root Hub ....................................................................................................................... 90
7USB Device Controller ................................................................................................................. 94
7.1 Overview............................................................................................................................... 94
7.2 Block Diagram ...................................................................................................................... 95
7.3 Register Map ........................................................................................................................ 95
7.4 Functional descriptions .........................................................................................................97
7.4.1 Initialization.................................................................................................................... 97
7.4.2 Endpoint Configuration .................................................................................................. 98

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Table No.: 1200-0003-07-A
7.4.3 Interrupt Service Routine ............................................................................................... 98
7.4.4 Endpoint 0 Operation..................................................................................................... 99
7.4.5 Get Descriptor ............................................................................................................. 100
7.4.6 Endpoint A ~ C Operation............................................................................................ 101
7.4.7 Example....................................................................................................................... 102
8SDIO Host Controller ................................................................................................................. 103
8.1 Overview............................................................................................................................. 103
8.2 Block Diagram .................................................................................................................... 103
8.3 Registers ............................................................................................................................ 104
8.4 SDIO Host Controller .......................................................................................................... 105
8.4.1 SDIO host controller Initialization Sequence................................................................ 105
8.4.2 Move data from SDRAM to SDIO host controller buffer .............................................. 106
8.4.3 Move data from SDIO host controller buffer to SDRAM .............................................. 106
8.5 SD Host Interface ............................................................................................................... 106
8.5.1 Send Command to SD/MMC Card .............................................................................. 106
8.5.2 Get Response from SD/MMC Card ............................................................................. 107
8.5.3 SD/MMC to Buffer Access ........................................................................................... 107
8.5.4 Buffer to SD/MMC Access ........................................................................................... 107
9LCD Controller ........................................................................................................................... 108
9.1.1 Overview...................................................................................................................... 108
9.1.2 Programming Procedure.............................................................................................. 112
9.2 Initialization......................................................................................................................... 115
9.3 Configure LCD Controller ................................................................................................... 115
9.4 Configure LCD Interrupt...................................................................................................... 117
9.5 Configure LCD Timing Generation...................................................................................... 117
9.6 Configure OSD function...................................................................................................... 117
9.7 Configure TFT Palette Look-up Table................................................................................. 119
9.8 Configure Gray level dithered data duty pattern ................................................................. 120
9.9 Configure Video/ OSD scaling factor .................................................................................. 120
9.10 Configure the starting address and the stride of frame buffer and FIFO............................. 121
9.11 Configure how to show image on the panel........................................................................ 124
9.12 Enable FIFO ....................................................................................................................... 125
9.13 Enable LCD Controller........................................................................................................ 126

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Table No.: 1200-0003-07-A
9.14 Check running state and process interrupt status............................................................... 126
10 Audio Controller...................................................................................................................... 128
10.1 Overview............................................................................................................................. 128
10.2 Block Diagram .................................................................................................................... 129
10.3 Registers ............................................................................................................................ 130
10.4 AC97 Interface.................................................................................................................... 130
10.4.1 Cold Reset External AC97 Codec ............................................................................... 132
10.4.2 Read AC97 Registers.................................................................................................. 132
10.4.3 Write AC97 Registers .................................................................................................. 134
10.4.4 AC97 Playback ............................................................................................................ 135
10.4.5 AC97 Record ............................................................................................................... 137
10.5 I2S Interface ....................................................................................................................... 138
10.5.1 I2S Play ....................................................................................................................... 138
10.5.2 I2S Record................................................................................................................... 140
11 UART ..................................................................................................................................... 142
11.1 Overview............................................................................................................................. 142
11.2 Registers ............................................................................................................................ 142
11.3 Functional Descriptions ...................................................................................................... 144
11.3.1 Baud Rate.................................................................................................................... 144
11.3.2 Initializations ................................................................................................................ 145
11.3.3 Polled I/O Functions .................................................................................................... 147
11.3.4 Interrupted I/O Functions ............................................................................................. 148
11.3.5 IrDA SIR ...................................................................................................................... 153
12 Timers .................................................................................................................................... 154
12.1 Overview............................................................................................................................. 154
12.2 Block Diagram .................................................................................................................... 155
12.3 Registers ............................................................................................................................ 155
12.4 Functional Descriptions ...................................................................................................... 156
12.4.1 Interrupt Frequency ..................................................................................................... 156
12.4.2 Initialization.................................................................................................................. 156
12.4.3 Timer Interrupt Service Routine................................................................................... 159
12.4.4 Watchdog Timer .......................................................................................................... 160
13 AIC (Advanced Interrupt Controller) ....................................................................................... 163

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distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
13.1 Overview............................................................................................................................. 163
13.2 Block Diagram .................................................................................................................... 164
13.3 Registers ............................................................................................................................ 165
13.4 Functional Descriptions ...................................................................................................... 167
13.4.1 Interrupt channel configuration .................................................................................... 167
13.4.2 Interrupt Masking......................................................................................................... 167
13.4.3 Interrupt Clearing and Setting...................................................................................... 168
13.4.4 Software Priority Scheme ............................................................................................ 168
13.4.5 Hardware Priority Scheme........................................................................................... 171
14 General-Purpose Input/Output (GPIO) ................................................................................... 174
14.1 Overview............................................................................................................................. 174
14.2 Register Map ...................................................................................................................... 176
14.3 Functional Description ........................................................................................................ 177
14.3.1 Multiple Functin Setting ............................................................................................... 177
14.3.2 GPIO Output Mode...................................................................................................... 178
14.3.3 GPIO Input Mode......................................................................................................... 179
15 Real Time Clock (RTC) .......................................................................................................... 181
15.1 Overview............................................................................................................................. 181
15.2 Block Diagram .................................................................................................................... 182
15.3 Register Map ...................................................................................................................... 182
15.4 Functional Description ........................................................................................................ 183
15.4.1 Initialization.................................................................................................................. 183
15.4.2 RTC Read/Write Enable .............................................................................................. 183
15.4.3 Frequency Compensation............................................................................................ 183
15.4.4 Application Note .......................................................................................................... 184
15.5 Programming Note.............................................................................................................. 185
15.5.2 Set Calendar and Time Alarm ..................................................................................... 187
15.5.3 Set tick interrupt........................................................................................................... 189
16 Smart Card Host Interface...................................................................................................... 191
16.1 Overview............................................................................................................................. 191
16.2 Registers ............................................................................................................................ 191
16.3 Functional Description ........................................................................................................ 193
16.3.1 Initialization Sequence................................................................................................. 193

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Table No.: 1200-0003-07-A
16.3.2 Timers Usage .............................................................................................................. 194
16.3.3 Receiver FIFO Data Time-out...................................................................................... 196
16.3.4 Parity Error management............................................................................................. 197
17 I2C Synchronous Serial Interface Controller........................................................................... 199
17.1 Overview............................................................................................................................. 199
17.2 Block Diagram .................................................................................................................... 201
17.3 Register Map ...................................................................................................................... 201
17.4 Functional Description ........................................................................................................ 202
17.4.1 Prescale Frequency..................................................................................................... 202
17.4.2 Start and Stop Signal................................................................................................... 202
17.4.3 Slave Address Transfer ............................................................................................... 202
17.4.4 Data Transfer............................................................................................................... 203
17.4.5 Below list Some Examples of I2C Data Transaction.................................................... 203
18 Universal Serial Interface ....................................................................................................... 209
18.1 Overview............................................................................................................................. 209
18.2 Block Diagram .................................................................................................................... 210
18.3 Register Map ...................................................................................................................... 210
18.4 Functional Description ........................................................................................................ 211
18.4.1 Active Universal Serial Interface.................................................................................. 211
18.4.2 Initialize Universal Serial Interface............................................................................... 211
18.4.3 Universal Serial Interface Transmit/Receive................................................................ 212
19 Pulse Width Modulation (PWM) Timer ................................................................................... 213
19.1 Overview............................................................................................................................. 213
19.2 Block Diagram .................................................................................................................... 215
19.3 Register Map ...................................................................................................................... 215
19.4 Functional Description ........................................................................................................ 216
19.4.1 Prescaler and clock selector........................................................................................ 216
19.4.2 Basic PWM timer operation and double buffering reload automatically....................... 217
19.4.3 PWM Timer Start Procedure........................................................................................ 218
19.4.4 PWM Timer Stop Procedure........................................................................................ 220
20 Keypad Interface .................................................................................................................... 222
20.1 Overview............................................................................................................................. 222
20.2 Block Diagram .................................................................................................................... 223

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Table No.: 1200-0003-07-A
20.3 Register Map ...................................................................................................................... 223
20.4 Functional Description ........................................................................................................ 223
20.4.1 KPI Interface Programming Flow................................................................................. 224
20.4.2 KPI Low Power Mode Configuration............................................................................ 225
21 PS/2 Host Interface Controller................................................................................................ 227
21.1 Overview............................................................................................................................. 227
21.2 Scan Code Set.................................................................................................................... 227
21.3 Register Map ...................................................................................................................... 229
21.4 Functional Description ........................................................................................................ 229
21.4.1 Initialization.................................................................................................................. 229
21.4.2 Send Commands......................................................................................................... 230
21.4.3 Read scan code and ASCII code................................................................................. 231
21.4.4 Interrupt Service Routine ............................................................................................. 232
21.4.5 Example....................................................................................................................... 235