Abov A96G166 User manual

A96G166/A96A166/A96S166
User’s Manual
16 MHz 8-bit MCU, 16 KB Flash Memory, 12-bit ADC,
3 Timers, USART, I2C, High Current Port
User’s Manual Version 1.13
Global Top Smart MCU Innovator
www.abovsemi.com
Introduction
This user’s manual targets application developers who use A96G166/A96A166/A96S166 for their
specific needs. It provides complete information of how to use A96G166/A96A166/A96S166 device.
Standard functions and blocks including corresponding register information of
A96G166/A96A166/A96S166 are introduced in each chapter, while instruction set is in Appendix.
A96G166/A96A166/A96S166 is based on M8051 core, and provides standard features of 8051 such
as 8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-
bit data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
16Kbytes of FLASH, 256bytes of IRAM, 512bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output,
watch timer, buzzer driving port, USART, I2C, CRC, 12-bit A/D converter, on-chip POR, LVR, LVI, on-
chip oscillator and clock circuitry.
As a field proven best seller, A96G166/A96A166/A96S166 has been sold more than 3 billion units up
to now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.
Reference document
A96G166/A96A166/A96S166 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite, https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents A96G166/A96A166/A96S166 User’s manual
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Contents
Introduction..............................................................................................................................................1
Reference document...............................................................................................................................1
1Description ...................................................................................................................................12
1.1 Device overview..................................................................................................................12
1.2 A96G166/A96A166/A96S166 block diagram......................................................................14
2Pinouts and pin description..........................................................................................................15
2.1 Pinouts................................................................................................................................15
2.2 Pin description.....................................................................................................................20
3Port structures..............................................................................................................................24
4Memory organization....................................................................................................................26
4.1 Program memory ................................................................................................................26
4.2 Data memory.......................................................................................................................27
4.3 External data memory.........................................................................................................29
4.4 SFR map.............................................................................................................................30
4.4.1 SFR map summary ................................................................................................30
4.4.2 SFR map ................................................................................................................32
4.4.3 Compiler compatible SFR ......................................................................................37
5I/O ports .......................................................................................................................................39
5.1 Port register.........................................................................................................................39
5.1.1 Data register (Px) ...................................................................................................39
5.1.2 Direction register (PxIO).........................................................................................39
5.1.3 Pull-up register selection register (PxPU) ..............................................................39
5.1.4 Open-drain Selection Register (PxOD)..................................................................39
5.1.5 De-bounce Enable Register (PxDB) ......................................................................39
5.1.6 Port Function Selection Register (PxFSR).............................................................39
5.1.7 Register Map..........................................................................................................40
5.2 P0 port.................................................................................................................................41
5.2.1 P0 port description .................................................................................................41
5.2.2 Register description for P0.....................................................................................41
5.3 P1 port.................................................................................................................................44
5.3.1 P1 port description .................................................................................................44
5.3.2 Register description for P1.....................................................................................44
5.4 P2 port.................................................................................................................................48
5.4.1 P2 port description .................................................................................................48
5.4.2 Register description for P2.....................................................................................48
5.5 P3 port.................................................................................................................................50
5.5.1 P3 port description .................................................................................................50
5.5.2 Register description for P3.....................................................................................50
6Interrupt controller........................................................................................................................52
6.1 External interrupt.................................................................................................................54
6.2 Block diagram .....................................................................................................................55
6.3 Interrupt vector table...........................................................................................................56
6.4 Interrupt sequence..............................................................................................................57
6.5 Effective timing after controlling interrupt bit.......................................................................59
6.6 Multi-interrupt......................................................................................................................60
6.7 Interrupt enable accept timing.............................................................................................61
6.8 Interrupt service routine address ........................................................................................61

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6.9 Saving/restore general purpose registers...........................................................................61
6.10 Interrupt timing....................................................................................................................62
6.11 Interrupt register overview ..................................................................................................63
6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3)...................................................63
6.11.2 Interrupt Priority Register (IP and IP1)...................................................................63
6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1)....................................63
6.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1 and EIPOL2) .63
6.11.5 Register map..........................................................................................................64
6.11.6 Interrupt register description...................................................................................65
7Clock generator............................................................................................................................70
7.1 Clock generator block diagram ...........................................................................................71
7.2 Register map.......................................................................................................................71
7.3 Register description ............................................................................................................72
8Basic Interval Timer .....................................................................................................................74
8.1 BIT block diagram...............................................................................................................74
8.2 BIT register map..................................................................................................................74
8.3 BIT register description.......................................................................................................75
9Watchdog timer............................................................................................................................76
9.1 Setting window open period of watchdog timer ..................................................................77
9.2 WDT block diagram ............................................................................................................78
9.3 Register map.......................................................................................................................78
9.4 Register description ............................................................................................................79
10 Watch timer..................................................................................................................................81
10.1 WT block diagram...............................................................................................................81
10.2 Register map.......................................................................................................................82
10.3 Watch timer register description .........................................................................................82
11 Timer 0/1/2...................................................................................................................................84
11.1 Timer 0................................................................................................................................84
11.1.1 8-bit timer/counter mode ........................................................................................84
11.1.2 8-bit PWM mode.....................................................................................................86
11.1.3 8-bit capture mode .................................................................................................88
11.1.4 Timer 0 block diagram............................................................................................90
11.1.5 Register map..........................................................................................................90
11.1.6 Register description................................................................................................91
11.2 Timer 1................................................................................................................................92
11.2.1 16-bit timer/counter mode ......................................................................................93
11.2.2 16-bit capture mode ...............................................................................................95
11.2.3 16-bit PPG mode....................................................................................................97
11.2.4 16-bit complementary PWM mode (dead time)......................................................99
11.2.5 16-bit timer 1 block diagram.................................................................................101
11.2.6 Register map........................................................................................................102
11.2.7 Register description..............................................................................................102
11.3 Timer 2..............................................................................................................................105
11.3.1 16-bit timer/counter mode ....................................................................................106
11.3.2 16-bit capture mode .............................................................................................108
11.3.3 16-bit PPG mode..................................................................................................110
11.3.4 16-bit timer 2 block diagram.................................................................................112
11.3.5 Register map........................................................................................................112
11.3.6 Register description..............................................................................................113
12 Buzzer driver..............................................................................................................................115

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12.1 Buzzer driver block diagram .............................................................................................115
12.2 Register map.....................................................................................................................116
12.3 Register description ..........................................................................................................116
13 12-bit ADC..................................................................................................................................117
13.1 Conversion timing .............................................................................................................117
13.2 Block diagram ...................................................................................................................118
13.3 ADC operation...................................................................................................................119
13.4 Register map.....................................................................................................................120
13.5 Register description ..........................................................................................................120
14 I2C..............................................................................................................................................123
14.1 Block Diagram...................................................................................................................123
14.2 Bit transfer.........................................................................................................................124
14.3 Start/ repeated start/ stop .................................................................................................124
14.4 Data transfer .....................................................................................................................125
14.5 Acknowledge.....................................................................................................................125
14.6 Synchronization/ arbitration ..............................................................................................126
14.7 Block operation .................................................................................................................127
14.7.1 I2C block initialization process.............................................................................128
14.7.2 I2C interrupt service .............................................................................................129
14.7.3 Master transmitter ................................................................................................130
14.7.4 Slave receiver.......................................................................................................132
14.8 Register Map.....................................................................................................................133
14.9 I2C register description.....................................................................................................134
15 USART 0/1.................................................................................................................................138
15.1 Block diagram ...................................................................................................................139
15.2 Clock generation...............................................................................................................140
15.3 External clock (XCK).........................................................................................................141
15.4 Synchronous mode operation...........................................................................................141
15.5 Data format .......................................................................................................................142
15.6 Parity bit............................................................................................................................143
15.7 USART transmitter............................................................................................................143
15.7.1 Sending Tx data ...................................................................................................143
15.7.2 Transmitter flag and interrupt...............................................................................144
15.7.3 Parity generator....................................................................................................144
15.7.4 Disabling transmitter.............................................................................................144
15.8 USART receiver................................................................................................................144
15.8.1 Receiving Rx data ................................................................................................145
15.8.2 Receiver flag and interrupt...................................................................................145
15.8.3 Parity checker.......................................................................................................146
15.8.4 Disabling receiver.................................................................................................146
15.8.5 Asynchronous data reception...............................................................................146
15.9 SPI mode ..........................................................................................................................148
15.9.1 SPI clock formats and timing................................................................................148
15.10 Receiver time out (RTO)...................................................................................................151
15.11 Register map.....................................................................................................................152
15.12 Register description ..........................................................................................................153
15.13 Baud rate settings (example)............................................................................................160
15.14 0% error baud rate............................................................................................................161
16 CRC............................................................................................................................................162
16.1 Block Diagram...................................................................................................................162

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16.2 Register map.....................................................................................................................163
16.3 Register description ..........................................................................................................164
16.1 Polynomial.........................................................................................................................166
17 Power down operation ...............................................................................................................167
17.1 Peripheral operation in IDLE/ STOP mode.......................................................................167
17.2 IDLE mode........................................................................................................................168
17.3 STOP mode ......................................................................................................................169
17.4 Released operation of STOP mode..................................................................................170
17.5 Register map.....................................................................................................................171
17.6 Register description ..........................................................................................................171
18 Reset..........................................................................................................................................172
18.1 Reset block diagram .........................................................................................................172
18.2 Power on reset..................................................................................................................173
18.3 External resetb input.........................................................................................................176
18.4 Low voltage reset process................................................................................................177
18.5 LVI block diagram .............................................................................................................178
18.6 Register Map.....................................................................................................................179
18.7 Reset operation register description.................................................................................179
19 Memory programming................................................................................................................182
19.1 Flash control and status registers.....................................................................................182
19.1.1 Register map........................................................................................................182
19.1.2 Register description..............................................................................................183
19.2 Memory map.....................................................................................................................189
19.2.1 Flash memory map...............................................................................................189
19.3 Serial in-system program mode........................................................................................190
19.3.1 Flash operation.....................................................................................................190
19.4 Mode entrance method of ISP mode................................................................................195
19.4.1 Mode entrance method for ISP ............................................................................195
19.5 Security.............................................................................................................................196
19.6 Configure option................................................................................................................197
19.7 Password function.............................................................................................................199
20 Electrical characteristics.............................................................................................................201
20.1 Absolute maximum ratings................................................................................................201
20.2 Recommended operating conditions ................................................................................201
20.3 A/D converter characteristics............................................................................................202
20.4 VDC1.55 Reference Voltage Characteristics....................................................................203
20.5 Power on reset characteristics..........................................................................................203
20.6 Low voltage reset and low voltage indicator characteristics.............................................204
20.7 High speed internal RC oscillator characteristics .............................................................205
20.8 Low speed internal RC oscillator characteristics ..............................................................205
20.9 DC characteristics.............................................................................................................206
20.10 AC characteristics.............................................................................................................207
20.11 USART characteristics......................................................................................................208
20.12SPI characteristics ............................................................................................................211
20.13 I2C characteristics.............................................................................................................212
20.14 Data retention voltage in stop mode.................................................................................213
20.15 Internal flash ROM characteristics....................................................................................214
20.16 Input/output capacitance...................................................................................................214
20.17 Main clock oscillator characteristics..................................................................................215
20.18 Sub-clock oscillator characteristics...................................................................................216

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20.19 Main oscillation stabilization characteristics .....................................................................217
20.20 Sub-oscillation characteristics...........................................................................................217
20.21 Operating voltage range ...................................................................................................218
20.22 Recommended circuit and layout......................................................................................218
20.23 Typical characteristics.......................................................................................................219
21 Package information ..................................................................................................................222
21.1 16 SOPN package information .........................................................................................222
21.2 20 TSSOP package information .......................................................................................223
21.3 20 SOP package information............................................................................................224
21.4 24 QFN package information............................................................................................225
21.5 28 SOP package information............................................................................................226
21.6 32 LQFP package information ..........................................................................................227
22 Development tools .....................................................................................................................228
22.1 Compiler............................................................................................................................228
22.2 OCD (On-chip debugger) emulator and debugger ...........................................................228
22.3 Programmers ....................................................................................................................229
22.3.1 E-PGM+................................................................................................................229
22.3.2 OCD emulator ......................................................................................................229
22.3.3 Gang programmer................................................................................................229
22.4 Flash programming...........................................................................................................230
22.4.1 On-board programming........................................................................................230
22.4.2 Circuit design guide..............................................................................................231
22.5 On-chip debug system......................................................................................................232
22.5.1 Two-pin external interface....................................................................................233
23 Ordering information ..................................................................................................................237
Appendix .............................................................................................................................................239
Instruction table...........................................................................................................................239
Revision history...................................................................................................................................245

A96G166/A96A166/A96S166 User’s manual List of figures
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List of figures
Figure 1. A96G166/A96A166/A96S166 Block Diagram........................................................................14
Figure 2. A96G166 16SOPN Pin Assignment.......................................................................................15
Figure 3. A96G166 20TSSOP/20SOP Pin Assignment ........................................................................16
Figure 4 A96A166 20SOP Pin Assignment ...........................................................................................16
Figure 5. A96S166 20TSSOP Pin Assignment .....................................................................................17
Figure 6. A96G166 20 QFN Pin Assignment ........................................................................................18
Figure 7. A96G166 28SOP Pin Assignment .........................................................................................19
Figure 8. A96G166 32 LQFP Pin Assignment.......................................................................................19
Figure 9. General Purpose I/O Port ......................................................................................................24
Figure 10. External Interrupt I/O Port ....................................................................................................25
Figure 11. Program Memory Map .........................................................................................................27
Figure 12. Data Memory Map ...............................................................................................................28
Figure 13. Lower 128bytes of RAM ......................................................................................................28
Figure 14. XDATA Memory Area ...........................................................................................................29
Figure 15. Interrupt Group Priority Level...............................................................................................53
Figure 16. External Interrupt Description ..............................................................................................54
Figure 17. Interrupt Controller Block Diagram ......................................................................................55
Figure 18. Interrupt Sequence Flow......................................................................................................58
Figure 19. Case A: Effective Timing of Interrupt Enable Register.........................................................59
Figure 20. Case B: Effective Timing of Interrupt Flag Register.............................................................59
Figure 21. Effective Timing of Multi-Interrupt ........................................................................................60
Figure 22. Interrupt Response Timing Diagram ....................................................................................61
Figure 23. Correspondence between Vector Table Address and the Entry Address of ISR .................61
Figure 24. Saving/Restore Process Diagram and Sample Source.......................................................61
Figure 25. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ...............................62
Figure 26. Clock Generator Block Diagram ..........................................................................................71
Figure 27. Basic Interval Timer Block Diagram.....................................................................................74
Figure 28. Watch Dog Timer Interrupt Timing Waveform......................................................................77
Figure 29. Watch Dog Timer Block Diagram.........................................................................................78
Figure 30. Watch Timer Block Diagram ................................................................................................81
Figure 31. 8-bit Timer/Counter Mode for Timer 0..................................................................................85
Figure 32. 8-bit Timer/Counter 0 Example ............................................................................................85
Figure 33. 8-bit PWM Mode for Timer 0 ................................................................................................86
Figure 34. PWM Output Waveforms in PWM Mode for Timer 0 ...........................................................87
Figure 35. 8-bit Capture Mode for Timer 0............................................................................................88
Figure 36. Input Capture Mode Operation for Timer 0 ..........................................................................89
Figure 37. Express Timer Overflow in Capture Mode...........................................................................89
Figure 38. 8-bit Timer 0 Block Diagram ................................................................................................90
Figure 39. 16-bit Timer/Counter Mode of Timer 1 .................................................................................93
Figure 40. 16-bit Timer/Counter Mode Operation Example ..................................................................94
Figure 41. 16-bit Capture Mode of Timer 1 ...........................................................................................95
Figure 42. 16-bit Capture Mode Operation Example ............................................................................96
Figure 43. Express Timer Overflow 16-bit Capture Mode.....................................................................96
Figure 44. 16-bit PPG Mode of Timer 1 ................................................................................................97
Figure 45. 16-bit PPG Mode Operation Example .................................................................................98
Figure 46. 16-bit Complementary PWM Mode for Timer 1 ...................................................................99
Figure 47. 16-bit Complementary PWM Mode Timing chart for Timer 1 ............................................100
Figure 48. 16-bit Timer 1 Block Diagram ............................................................................................101

List of figures A96G166/A96A166/A96S166 User’s manual
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Figure 49. 16-bit Timer/Counter Mode of Timer 2 ...............................................................................106
Figure 50. 16-bit Timer/Counter Mode Operation Example ................................................................107
Figure 51. 16-bit Capture Mode of Timer 2 .........................................................................................108
Figure 52. 16-bit Capture Mode Operation Example ..........................................................................109
Figure 53. Express Timer Overflow in Capture Mode .........................................................................109
Figure 54. 16-bit PPG Mode of Timer 2 ..............................................................................................110
Figure 55. 16-bit PPG Mode Operation Example ............................................................................... 111
Figure 56. 16-bit Timer 2 Block Diagram ............................................................................................112
Figure 57. Buzzer Driver Block Diagram.............................................................................................115
Figure 58. 12-bit ADC Block Diagram .................................................................................................118
Figure 59. A/D Analog Input Pin with a Capacitor ...............................................................................118
Figure 60. Control Registers and Align Bits ........................................................................................119
Figure 61. ADC Operation Flow Sequence .........................................................................................119
Figure 62. I2C Block Diagram..............................................................................................................123
Figure 63. Bit Transfer on the I2C-Bus ...............................................................................................124
Figure 64. START and STOP Condition..............................................................................................124
Figure 65. Data Transfer on the I2C-Bus ............................................................................................125
Figure 66. Acknowledge on the I2C-Bus.............................................................................................126
Figure 67. Clock Synchronization during Arbitration Procedure .........................................................126
Figure 68. Arbitration Procedure of Two Masters................................................................................127
Figure 69. I2C SCL Max Clock, SCL, SDA Settings ...........................................................................128
Figure 70. USARTn Block Diagram (n=0, 1).......................................................................................139
Figure 71. Clock Generation Block Diagram.......................................................................................140
Figure 72. Synchronous Mode XCKn Timing (n = 0, 1) ......................................................................141
Figure 73. A Frame Format .................................................................................................................142
Figure 74. Start Bit Sampling ..............................................................................................................146
Figure 75. Sampling of Data and Parity Bit.........................................................................................147
Figure 76. Stop Bit Sampling and Next Start Bit Sampling.................................................................147
Figure 77. SPI Clock Formats when UCPHA = 0................................................................................149
Figure 78. SPI Clock Formats when UCPHA = 1................................................................................150
Figure 79. Example for RTO in USART ..............................................................................................151
Figure 80. 0% Error Baud Rate Block Diagram ..................................................................................161
Figure 81. CRC Block Diagram...........................................................................................................162
Figure 82. IDLE Mode Release Timing by an External Interrupt ........................................................168
Figure 83. STOP Mode Release Timing by External Interrupt............................................................169
Figure 84. STOP Mode Release Flow ................................................................................................170
Figure 85. Reset Block Diagram .........................................................................................................172
Figure 86. Fast VDD Rising Time .......................................................................................................173
Figure 87. Internal RESET Release Timing On Power-Up .................................................................173
Figure 88. Configuration Timing when Power-on................................................................................174
Figure 89. Boot Process Waveform ....................................................................................................174
Figure 90. Timing Diagram after RESET ............................................................................................176
Figure 91. Oscillator generating waveform example ..........................................................................176
Figure 92. Block Diagram of LVR........................................................................................................177
Figure 93. Internal Reset at Power Fail Situation ...............................................................................177
Figure 94. Configuration Timing When LVR RESET...........................................................................178
Figure 95. LVI Block Diagram .............................................................................................................178
Figure 96. Read Device Internal Checksum (Full Size) ......................................................................186
Figure 97. Read Device Internal Checksum (User Define Size).........................................................187
Figure 98. Flash Memory Map ............................................................................................................189

A96G166/A96A166/A96S166 User’s manual List of figures
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Figure 99. Address Configuration of Flash Memory ...........................................................................189
Figure 100. The Sequence of Page Program and Erase of Flash Memory........................................190
Figure 101. The Sequence of Bulk Erase of Flash Memory ...............................................................191
Figure 102. ISP Mode .........................................................................................................................195
Figure 103. Using OCD/E-PGM+/E-GANG4/E-GANG6. ....................................................................200
Figure 104. AC Timing.........................................................................................................................207
Figure 105. SPI master mode timing (UCPHA = 0, MSB first)............................................................209
Figure 106. SPI/Synchronous master mode timing (UCPHA = 1, MSB first)......................................209
Figure 107. SPI slave mode timing (UCPHA = 0, MSB first) ..............................................................210
Figure 108. SPI/Synchronous slave mode timing (UCPHA = 1, MSB first) ........................................210
Figure 109. SPI0/1 Timing...................................................................................................................211
Figure 110. I2C Timing ........................................................................................................................212
Figure 111. Stop Mode Release Timing when Initiated by an Interrupt ..............................................213
Figure 112. Stop Mode Release Timing when Initiated by RESETB ..................................................213
Figure 113. Crystal/Ceramic Oscillator ...............................................................................................215
Figure 114. External Clock ..................................................................................................................215
Figure 115. Crystal Oscillator ..............................................................................................................216
Figure 116. Crystal Oscillator ..............................................................................................................216
Figure 117. Clock Timing Measurement at XIN ..................................................................................217
Figure 118. Clock Timing Measurement at SXIN ................................................................................217
Figure 119. Operating Voltage Range.................................................................................................218
Figure 120. Recommended Voltage Range........................................................................................218
Figure 121. RUN (IDD1) Current ........................................................................................................219
Figure 122. IDLE (IDD2) Current ........................................................................................................220
Figure 123. SUB RUN (IDD3) Current ................................................................................................220
Figure 124. SUB IDLE (IDD4) Current ................................................................................................221
Figure 125. SUB IDLE (IDD4) Current ................................................................................................221
Figure 126 16 SOPN Package Outline ...............................................................................................222
Figure 127. 20 TSSOP Package Outline ............................................................................................223
Figure 128. 20 SOP Package Outline .................................................................................................224
Figure 129. 24 QFN Package Outline .................................................................................................225
Figure 130. 28 SOP Package Outline .................................................................................................226
Figure 131. 32 LQFP Package Outline ...............................................................................................227
Figure 132. Debugger (OCD1/OCD2) and Pinouts ............................................................................228
Figure 133. E-PGM+ (Single Writer) and Pinouts ...............................................................................229
Figure 134. E-Gang4 and E-Gang6 (for Mass Production) ................................................................230
Figure 135. PCB Design Guide for On-Board Programming ..............................................................231
Figure 136. On-Chip Debugging System in Block Diagram................................................................232
Figure 137. 10-bit Transmission Packet..............................................................................................233
Figure 138. Data Transfer on Twin Bus ..............................................................................................234
Figure 139. Bit Transfer on Serial Bus ................................................................................................234
Figure 140. Start and Stop Condition..................................................................................................234
Figure 141. Acknowledge on Serial Bus .............................................................................................235
Figure 142. Clock Synchronization during Wait Procedure ................................................................235
Figure 143. Connection of Transmission ............................................................................................236
Figure 144. A96G166/A96A166/A96S166 Device Numbering Nomenclature ....................................238

List of tables A96G166/A96A166/A96S166 User’s manual
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List of tables
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts .................................12
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (continued) ..............13
Table 2. Normal Pin Description............................................................................................................20
Table 2. Normal Pin Description (continued).........................................................................................21
Table 2. Normal Pin Description (continued).........................................................................................22
Table 3. SFR Map Summary .................................................................................................................30
Table 4. XSFR Map Summary ..............................................................................................................31
Table 5. SFR Map .................................................................................................................................32
Table 5. SFR Map (continued) ..............................................................................................................33
Table 5. SFR Map (continued) ..............................................................................................................34
Table 5. SFR Map (continued) ..............................................................................................................35
Table 6. XSFR Map ...............................................................................................................................36
Table 7. Port Register Map....................................................................................................................40
Table 8. Interrupt Vector Address Table ................................................................................................56
Table 9. Interrupt Register Map.............................................................................................................64
Table 10. Clock Generator Register Map..............................................................................................71
Table 11. Basic Interval Timer Register Map.........................................................................................74
Table 12. Setting of window open period ..............................................................................................78
Table 13. Watchdog Timer Register Map ..............................................................................................78
Table 14. Watch Timer Register Map ....................................................................................................82
Table 15. Timer 0 Operating Mode........................................................................................................84
Table 16. Timer 0 Register Map ............................................................................................................90
Table 17. TIMER 1 Operating Modes....................................................................................................92
Table 18. TIMER 1 Register Map ........................................................................................................102
Table 19. TIMER 2 Operating Modes..................................................................................................105
Table 20. TIMER 2 Register Map ........................................................................................................112
Table 21. Buzzer Frequency at 8MHz .................................................................................................115
Table 22. Buzzer Driver Register Map ................................................................................................116
Table 23. ADC Register Map...............................................................................................................120
Table 24. I2C Register Map .................................................................................................................133
Table 25. Equations for Calculating Baud Rate Register Setting........................................................140
Table 26. CPOL Functionality..............................................................................................................148
Table 27. Example Condition of RTO..................................................................................................151
Table 28. USART Register Map ..........................................................................................................152
Table 29. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies .......................160
Table 30. CRC mode...........................................................................................................................162
Table 31. CRC Register Map ..............................................................................................................163
Table 32. Peripheral Operation Status during Power-down Mode......................................................167
Table 33. Power-down Operation Register Map .................................................................................171
Table 34. Hardware Setting Values in Reset State .............................................................................172
Table 35. Boot Process Description ....................................................................................................175
Table 36. Reset Operation Register Map............................................................................................179
Table 37. Flash Control and Status Register Map ..............................................................................182
Table 38. Program and Erase Time ....................................................................................................188
Table 39. Operation Mode...................................................................................................................195
Table 40. Mode entrance method for ISP ...........................................................................................195
Table 41. Security Policy using Lock Bits............................................................................................196

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Table 42. Security mode using password lock bit ...............................................................................199
Table 43. Absolute Maximum Ratings .................................................................................................201
Table 44. Recommended Operating Conditions .................................................................................201
Table 45. A/D Converter Characteristics .............................................................................................202
Table 47. VDC1.55 Reference Voltage Characteristics ......................................................................203
Table 48. Power-on Reset Characteristics..........................................................................................203
Table 49. LVR and LVI Characteristics................................................................................................204
Table 50. High Speed Internal RC Oscillator Characteristics .............................................................205
Table 51. Low Speed Internal RC Oscillator Characteristics ..............................................................205
Table 52. DC Characteristics...............................................................................................................206
Table 53. AC Characteristics ...............................................................................................................207
Table 54. USART Timing Characteristics in SYNC. or SPI Mode Operations ....................................208
Table 55. SPI Characteristics ..............................................................................................................211
Table 56. I2C Characteristics ..............................................................................................................212
Table 57. Data Retention Voltage in Stop Mode .................................................................................213
Table 58. Internal Flash Rom Characteristics .....................................................................................214
Table 59. Input / Output Capacitance..................................................................................................214
Table 60. Main Clock Oscillator Characteristics..................................................................................215
Table 61. Sub Clock Oscillator Characteristics ...................................................................................216
Table 62. Main Oscillation Stabilization Characteristics......................................................................217
Table 63. Sub Oscillation Stabilization Characteristics .......................................................................217
Table 64. Pins for Flash Programming ................................................................................................230
Table 65. OCD Features .....................................................................................................................232
Table 66. A96G166/A96A166/A96S166 Device Ordering Information ...............................................237
Table 67. Instruction Table ..................................................................................................................239

1. Description A96G166/A96A166/A96S166 User’s manual
12
1Description
A96G166/A96A166/A96S166 is an advanced CMOS 8-bit microcontroller with 16Kbytes of FLASH.
This is a powerful microcontroller which provides a highly flexible and cost-effective solution to many
embedded control applications.
1.1 Device overview
In this section, features of A96G166/A96A166/A96S166 and peripheral counts are introduced.
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts
Peripherals
Description
Core
CPU
8-bit CISC core (M8051, 2 clocks per cycle)
Interrupt
Up to 21 peripheral interrupts supported.
EINT0 to 4, EINT5, EINT6, EINT7 to A, EINT10, EINT11,
EINT12 (7)
Timer (0/1/2) (3)
WDT (1)
BIT (1)
WT (1)
USART *Rx/Tx (4)
I2C (1)
ADC (1)
CRC (1)
LVI (1)
Memory
ROM (FLASH)
capacity
16 Kbytes FLASH with self-read and write capability
In-system programming (ISP)
Endurance: 30,000times
IRAM
256Bytes
XRAM
512Bytes
Programmable pulse generation
Pulse generation (by T0/T1/T2)
16-bit Complement PWM (Dead time control)
Buzzer
8-bit ×1-ch
Minimum instruction execution
time
125ns (@ 16MHz main clock)
61us (@ 32.768kHz sub clock)
Power down mode
STOP mode
IDLE mode

A96G166/A96A166/A96S166 User’s manual 1. Description
13
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (continued)
Peripherals
Description
General Purpose I/O (GPIO)
Normal I/O: Max 30 ports
High sink current port: LED 8 x COM
Reset
Power on
reset
Reset release level: 1.32V
Low
voltage
reset
16 levels detect
1.61/1.68/1.77/1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/3.21/
3.56/3.73/3.91/4.25V
Low voltage indicator
13 levels detect
1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/3.21/3.56/3.73/
3.91/4.25V
Watch Timer (WT)
3.91ms/0.25s/0.5s/1s/1min interval at 32.768kHz
Timer/counter
Basic interval timer (BIT) 8-bit x 1-ch.
Watchdog timer (WDT) 8-bit x 1-ch.
8-bit x 1-ch (T0), 16-bit x 2-ch (T1/T2)
Communication
function
USART
(UART+SPI)
8-bit USART x 2-ch or 8-bit SPI x 2-ch
Receiver timer out (RTO)
0% error baud rate
I2C
8-bit I2C x 1-ch
12-bit A/D converter
15 input channels
Oscillator type
4MHz to 12MHz crystal or ceramic for main clock
32.768kHz Crystal for sub clock
Internal RC oscillator
HSI 32MHz ±1.5% (TA= 0℃to +50℃)
HSI 32MHz ±2.0% (TA= -10℃to +70℃)
HSI 32MHz ±2.5% (TA= -40℃to +85℃)
HSI 32MHz ±5.0% (TA=-40℃to +105℃)
LSI 128kHz ±20% (TA= -40℃to +85℃)
LSI 128kHz ±30% (TA= -40℃to +105℃)
Operating voltage and
frequency
1.8V to 5.5V @ 32.768kHz with crystal
2.2V to 5.5V @ 4MHz to 10MHz with crystal
2.4V to 5.5V @ 4MHz to 12MHz with crystal
1.8V to 5.5V @ 0.5MHz to 16.0MHz with internal RC
Operating temperature
-40℃to +85℃, -40℃to +105℃
Package
Pb-free packages
32 LQFP, 28 SOP, 24 QFN
20 TSSOP/SOP, 16 SOPN

1. Description A96G166/A96A166/A96S166 User’s manual
14
1.2 A96G166/A96A166/A96S166 block diagram
In this section, A96G166/A96A166/A96S166 device with peripherals are described in a block diagram.
XRAM
512B
IRAM
256B
Flash
16KB
ISP
In-system programming
Power control
Power on Reset
CRC Reset
Low voltage Reset
Low voltage indicator
Power down mode
Clock generator
32MHz, Internal RC OSC
128kHz Internal RC OSC
12MHz, Crystal OSC
32.768kHz, Crystal OSC
UART
2 channels, 8-bit
SPI
2 channels, 8-bit
I2C
1 channels, 8-bit
CORE
M8051
General purpose I/O
30 ports normal I/O
Watchdog timer
1 channel, 8-bit
128kHz, internal RC OSC
Basic interval timer
1 channel, 8-bit
Timer / Counter
1 channel, 8-bit
2 channels, 16-bit
ADC
15 Input channels, 12-bit
PWM
1-ch 8-bit (T0)
1-ch 16-bit (T2)
PPG (T1)
Buzzer
1 channels, 8-bit
Figure 1. A96G166/A96A166/A96S166 Block Diagram

A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description
15
2Pinouts and pin description
In this chapter, A96G166/A96A166/A96S166 device pinouts and pin descriptions are introduced.
2.1 Pinouts
A96G166AE
(16SOPN)
1
4
3
2
VSS
6
5
VDD
7
8
16
13
14
15
11
12
10
9
P37/XOUT
P32/(T0O)/(PWM0O)/RESETB
P36/XIN
P26/EC0
P25/SCL/(RXD1)
P24/SDA/(TXD1)
P22/EINT9/XCK1/LED6
P00/AN0/DSDA
P01/AN1/DSCL
P06/AN6/EINT4/(T2O)/(PWM2O)
P12/AN9/EINT11/T1O/PWM1O/LED0
P13/AN10/EINT12/T2O/PWM2O/LED1
P14/AN11/RXD0
P15/AN12/TXD0
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P02-P05, P10-P11, P16-P17, P20-P21, P23, P30-P31 and P33-P35 pins should be selected as a
push-pull output or an input with pull-up resistor by software control when the 16-pin package is used.
Figure 2. A96G166 16SOPN Pin Assignment

2. Pinouts and pin description A96G166/A96A166/A96S166 User’s manual
16
A96G166FR
(20TSSOP)
A96G166FD
(20SOP)
1
4
3
2
VSS
6
5
VDD
7
10
9
8
20
17
18
19
15
16
14
11
12
13
P37/XOUT
P35/EINT10/T0O/PWM0O
P36/XIN
P32/(T0O)/(PWM0O)/RESETB
P31/(EC0)/RXD1/(SCL)
P30/(EC2)/TXD1/(SDA)
P25/SCL/(RXD1)
P24/SDA/(TXD1)
P22/EINT9/XCK1/LED6
P00/AN0/DSDA
P01/AN1/DSCL
P02/AN2/EINT0
P03/AN3/EINT1/(T1O)/(PWM1O)
P10/AN7/EINT5/PWM1OB
P11/AN8/EINT6/EC1/BUZO
P12/AN9/EINT11/T1O/PWM1O/LED0
P13/AN10/EINT12/T2O/PWM2O/LED1
P21/EINT8/SS1/LED5
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P04-P06, P14-P17, P20, P23, P26 and P33-P34 pins should be selected as a push-pull
output or an input with pull-up resistor by software control when the 20-pin package is used.
Figure 3. A96G166 20TSSOP/20SOP Pin Assignment
A96A166FD
(20SOP)
1
4
3
2
VSS
6
5
VDD
7
10
9
8
20
17
18
19
15
16
14
11
12
13
P37/XOUT
P35/EINT10/T0O/PWM0O
P36/XIN
P32/(T0O)/(PWM0O)/RESETB
P31/(EC0)/RXD1/(SCL)
P30/(EC2)/TXD1/(SDA)
P25/SCL/(RXD1)
P24/SDA/(TXD1)
P15/AN12/TXD0
P00/AN0/DSDA
P01/AN1/DSCL
P02/AN2/EINT0
P03/AN3/EINT1/(T1O)/(PWM1O)
P10/AN7/EINT5/PWM1OB
P11/AN8/EINT6/EC1/BUZO
P12/AN9/EINT11/T1O/PWM1O/LED0
P13/AN10/EINT12/T2O/PWM2O/LED1
P14/AN11/RXD0
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P04-P06, P16-P17, P20-P23, P26 and P33-P34 pins should be selected as a push-pull output or
an input with pull-up resistor by software control when the 20-pin package is used.
Figure 4 A96A166 20SOP Pin Assignment

A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description
17
A96S166FR
(20TSSOP)
1
4
3
2
VDD
6
5
VSS
7
10
9
8
20
17
18
19
15
16
14
11
12
13
P37/XOUT
P35/RESETB/EINT10/T0O/PWM0O
P36/XIN
P32/(T0O)/(PWM0O)
P31/(EC0)/RXD1/(SCL)
P30/(EC2)/TXD1/(SDA)
P25/SCL/(RXD1)
P24/SDA/(TXD1)
P22/EINT9/XCK1/LED6
P00/AN0/DSDA
P01/AN1/DSCL
P02/AN2/EINT0
P03/AN3/EINT1/(T1O)/(PWM1O)
P10/AN7/EINT5/PWM1OB
P11/AN8/EINT6/EC1/BUZO
P12/AN9/EINT11/T1O/PWM1O/LED0
P13/AN10/EINT12/T2O/PWM2O/LED1
P21/EINT8/SS1/LED5
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P04-P06, P14-P17, P20, P23, P26 and P33-P34 pins should be selected as a push-pull output or
an input with pull-up resistor by software control when the 20-pin package is used.
Figure 5. A96S166 20TSSOP Pin Assignment

2. Pinouts and pin description A96G166/A96A166/A96S166 User’s manual
18
A96G166LU
(24-QFN)
1
12
2
3
4
5
6
7
8
9
10
13
14
11
18
17
16
15
24
23
22
21
20
19
P36/XIN
P35/EINT10/T0O/PWM0O
P32/RESETB/(T0O)/(PWM0O)
P31/(EC0)/RXD1/(SCL)
P25/SCL/(RXD1)
P24/SDA/(TXD1)
P14/AN11/RXD0
P03/AN3/EINT1/(T1O)/(PWM1O)
P10/AN7/EINT5/PWM1OB
P11/AN8/EINT6/EC1/BUZO
VSS
VDD
P37/XOUT
P30/(EC2)/TXD1/(SDA)
P23/EINTA/LED7
P16/AN13/XCK0/LED2
P15/AN12/TXD0
P12/AN9/EINT11/T1O/PWM1O/LED0
P13/AN10/EINT12/T2O/PWM2O/LED1
P34/SXIN
P33/SXOUT
P00/AN0/DSDA
P01/AN1/DSCL
P02/AN2/EINT0
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P04-P06, P17, P20-P22 and P26 pins should be selected as a push-pull output or an input with
pull-up resistor by software control when the 24-pin package is used.
Figure 6. A96G166 20 QFN Pin Assignment

A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description
19
A96G166GD
(28-SOP)
1
2
13
14
8
9
10
11
12
3
4
5
6
7
16
15
21
20
19
18
17
26
25
24
23
22
28
27
P20/EINT7/LED4
VDD
P36/XIN
P35/EINT10/T0O/PWM0O
P34/SXIN
P33/SXOUT
VSS
P37/XOUT
P32/RESETB/(T0O)/(PWM0O)
P31/(EC0)/RXD1/(SCL)
P30/(EC2)/TXD1/(SDA)
P24/SDA/(TXD1)
P23/EINTA/LED7
P22/EINT9/XCK1/LED6
P21/EINT8/SS1/LED5
P25/SCL(RXD1)
P17/AN14/EC2/SS0/LED3
P01/AN1/DSCL
P00/AN0/DSDA
P03/AN3/EINT1/(T1O)/(PWM1O)
P02/AN2/EINT0
P16/AN13/XCK0/LED2
P15/AN12/TXD0
P11/AN8/EINT6/EC1/BUZO
P10/AN7/EINT5/PWM1OB
P13/AN10/EINT12/T2O/PWM2O/LED1
P12/AN9/EINT11/T1O/PWM1O/LED0
P14/AN11/RXD0
NOTES:
1. The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
2. The P04-P06 and P26 pins should be selected as a push-pull output or an input with pull-up resistor
by software control when the 28-pin package is used.
Figure 7. A96G166 28SOP Pin Assignment
A96G166KN
(32-LQFP)
P33/SXOUT
P32/RESETB/(T0O)/(PWM0O)
P31/(EC0)/RXD1/(SCL)
P25/SCL/(RXD1)
P26/EC0
P30/(EC2)/TXD1/(SDA)
P35/EINT10/T0O/PWM0O
P34/SXIN
NOTE: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.
Figure 8. A96G166 32 LQFP Pin Assignment

2. Pinouts and pin description A96G166/A96A166/A96S166 User’s manual
20
2.2 Pin description
Table 2. Normal Pin Description
Pin no.
PIN name
I/O(1)
Description
Remark
32
LQFP
28
SOP
24
QFN
20
TSSOP
20
SOP
16
SOPN
28
27
20
19(19)
19
15
P00*
IOUS
Port 0 bit 0 Input/output
AN0
IA
ADC input ch-0
DSDA
IOU
OCD debugger data
input/output
Pull-up
27
26
19
18(18)
18
14
P01*
IOUS
Port 0 bit 1 Input/output
AN1
IA
ADC input ch-1
DSCL
IOU
OCD debugger clock
Pull-up
26
25
18
17(17)
17
-
P02*
IOUS
Port 0 bit 2 Input/output
AN2
IA
ADC input ch-2
EINT0
I
External interrupt input ch-0
25
24
17
16(16)
16
-
P03*
IOUS
Port 0 bit 3 Input/output
AN3
IA
ADC input ch-3
EINT1
I
External interrupt input ch-1
T1O
O
Timer 1 interval output
PWM1O
O
Timer 1 PWM output
24
-
-
-
-
-
P04*
IOUS
Port 0 bit 4 Input/output
AN4
IA
ADC input ch-4
EINT2
I
External interrupt input ch-2
23
-
-
-
-
-
P05*
IOUS
Port 0 bit 5 Input/output
AN5
IA
ADC input ch-5
EINT3
I
External interrupt input ch-3
22
-
-
-
-
13
P06*
IOUS
Port 0 bit 6 Input/output
AN6
IA
ADC input ch-6
EINT4
I
External interrupt input ch-4
T2O
O
Timer 2 interval output
PWM2O
O
Timer 2 PWM output
21
23
16
15(15)
15
-
P10*
IOUS
Port 1 bit 0 Input/output
AN7
IA
ADC input ch-7
EINT5
I
External interrupt input ch-5
PWM1OB
IO
Timer 1 PWM complementary
output
20
22
15
14(14)
14
-
P11*
IOUS
Port 1 bit 1 Input/output
AN8
IA
ADC input ch-8
EINT6
I
External interrupt input ch-6
EC1
I
Timer 1(Event Capture) input
BUZO
O
Buzzer output
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