
vii Table of Contents
Figure 5.6:Offset Calibration Failed ............................ 41
Figure 5.7:The Start-up Window of Offset Calibration ...
41
Figure 5.8:The Adjustment Process of Gain Calibration .
42
Figure 5.9:Gain Calibration Succeeded ....................... 42
Figure 5.10:Gain Calibration Failed ............................ 43
Figure 5.11:Calibration Procedure Completed ............ 43
Appendix A Specifications ................................................. 46
A.1 General: ........................................................................... 46
A.2 Analog Input.................................................................... 47
Appendix B Block Diagram............................................... 50
Appendix C Register Structure & Format....................... 52
C.1 Overview ........................................................................ 52
C.2 Register Format ............................................................... 52
Table C.1:PCIE-1744 register format (Part 1) ............. 53
Table C.2:PCIE-1744 register format (Part 2) ............. 54
Table C.3:PCIE-1744 register format (Part 3) ............. 55
Table C.4:PCIE-1744 register format (Part 4) ............. 57
C.3 A/D Single Value Acquisition......................................... 57
Table C.5:Register for Single Value Acquisition ........ 57
C.4 AI Range Control- Write/Read BASE+8........................ 59
Table C.6:Register for Analog Input Range Control ... 59
C.5 A/D Converter Enable- Write/Read BASE+A................ 59
Table C.7:Register for A/D Converter Enable ............. 59
C.6 Clock Source and Divider- Write/Read BASE+C .......... 60
Table C.8:Register for Clock Source and Divider ....... 60
C.7 Trigger Mode and Source- Write/Read BASE+E........... 61
Table C.9:Register for Trigger Mode and Source ....... 61
C.8 FIFO Control- Write BASE+10,12 ................................. 62
Table C.10:Register for FIFO Control ......................... 62
C.9 FIFO Status- Read BASE+10,12 .................................... 63
Table C.11: Register for FIFO Status .......................... 63
C.10 FIFO for Programmable Flag - Write/Read
BASE+14,16,18,1A64
Table C.12:Register for FIFO Programmable Flag ..... 64
C.11 DMA Counter - Write/Read BASE+1C, Write BASE+1E.
65
Table C.13:Register for DMA Counter ....................... 65
C.12 Interrupt Control/Flag- Write/Read BASE+20 ............... 66
Table C.14:Register for Interrupt Control/Flag ........... 66
C.12.1 Interrupt Control Register ............................................ 66
C.12.2 Interrupt Flag ............................................................... 66
C.13 Clear Interrupt- Write BASE+22 .................................... 67
Table C.15:Register for Clear Interrupt ....................... 67
C.14 Analog Trigger Threshold Voltage-Write/Read BASE+24
68
Table C.16:Register for Analog Trigger Threshold Volt-
age 68