Aim AXC-FDX-2 User manual

V01.00 Rev. A
September
2017
AXC-FDX-2
10/100/1000Mbit
AFDX / ARINC664
Test and Simulation
XMC Interface Module
Hardware
Manual

AXC-FDX-2 Hardware Manual
i
AXC-FDX-2
10/100/1000Mbit
AFDX/ARINC664
Test and Simulation
XMC Interface Module
V01.00 Rev. A
September 2017
AIM No.
60-15A40-16-0100-A
Hardware
Manual

AXC-FDX-2 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
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D-79111 Freiburg / Germany
Phone [phone]
Fax [phone]
[email protected]
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone [phone]
Fax [phone]
[email protected]
AIM GmbH –Munich Sales Office
Terofalstr. 23a
D-80689 München / Germany
Phone [phone]
Fax [phone]
[email protected]
AIM USA LLC
Seven Neshaminy Interplex
Suite 211 Trevose, PA 19053
Phone [phone]
Fax [phone]
[email protected]
© AIM GmbH 2017
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted
by implication in connection therewith. Specifications are subject to change without
notice.

AXC-FDX-2 Hardware Manual
iii
DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
01.00 Rev A
13.09.2017
Marco Maier
First Release

AXC-FDX-2 Hardware Manual
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AXC-FDX-2 Hardware Manual
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TABLE OF CONTENTS
Section Title Page
1Introduction ............................................................................................................1
1.1 General........................................................................................................................................1
1.2 How This Manual is Organized.................................................................................................2
1.3 Applicable Documents ..............................................................................................................2
1.3.1 Industry Documents.................................................................................................................2
1.3.2 Product Specific Documents....................................................................................................2
2Instalation ...............................................................................................................3
2.1 Preparation and Precaution for Installation ............................................................................3
2.2 Installation Instructions.............................................................................................................3
2.3 Connecting to Other Devices....................................................................................................4
2.3.1 AFDX Connection....................................................................................................................5
2.3.2 Trigger, Discrete and IRIG Connector.....................................................................................5
2.3.3 AXC-FDX-2 Rear I/O Interface................................................................................................7
3Structure of the AXC-FDX-2...................................................................................9
3.1 System on Chip (SoC) .............................................................................................................11
3.1.1 Ethernet MAC Features.........................................................................................................11
3.1.2 PCI-Express Bus and DMA Engine.......................................................................................11
3.1.3 IRIG- and Time Code Section................................................................................................12
3.1.3.1 IRIG-B Synchronization Unit.........................................................................................12
3.1.3.2 Timecode Encoder/Decoder .........................................................................................12
3.1.4 Application Specific Processor ..............................................................................................13
3.1.5 BIU Processor........................................................................................................................13
3.1.6 Memory Interface...................................................................................................................13
3.2 Gigabit Ethernet Phyter...........................................................................................................13
3.3 External Trigger Inputs and Outputs .....................................................................................14
3.4 User programmable Discrete I/O............................................................................................14
4Technical Data......................................................................................................17
5NOTES...................................................................................................................21
5.1 Acronyms..................................................................................................................................21
6Certificate of Volatility..........................................................................................23

AXC-FDX-2 Hardware Manual
vi
LIST OF FIGURES
Figure Title Page
Figure 2-1: Installing the AXC-FDX-2 on a XMC carrier module......................................4
Figure 2-2: Front panel View of AXC-FDX-2....................................................................4
Figure 2-3: Pinout DSUB.................................................................................................5
Figure 3-1: AXC-FDX-2 Block Diagram.........................................................................10
Figure 3-2: GPI/O AXC-FDX-2 circuitry.........................................................................15
Figure 3-3: Discrete Protection with external resistor....................................................16
LIST OF TABLES
Table Title Page
Table 2-1 Pin Assignment for AFDX................................................................................5
Table 2-2 Trigger, Discrete and IRIG Connector Pinout..................................................5
Table 2-3 PMC P14 Rear I/O Pin Assignment.................................................................7
Table 3-1 Time Tag Format...........................................................................................12

1. Introduction
AXC-FDX-2 Hardware Manual
1
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the AXC-FDX-2 XMC Card.
The document covers the hardware installation, the board connections, the technical
data and a general description of the hardware architecture. For programming
information please refer to the according documents listed in the 'Applicable
Documents' section.
The AXC-FDX-2 module is a member of AIM's family of advanced XMC-Bus modules
for analysing, simulating, monitoring and testing of avionic Databus Systems.
The AXC-FDX-2 module is used to simulate, monitor and inject protocol errors of AFDX
based network systems as well as common Ethernet networks with a data rate of
10/100/1000 Mbit/s. The implemented MAC features comprise two independent
transmitters and two independent receivers, each capable of transmitting or receiving
data at line rate concurrently. The transmitters feature multiple error injections and
timing possibilities with several start modes like start on IFG timing, start on absolute
timing, start on trigger events or grouping of frames to packets with packet group wait
timing. The receivers feature multiple error detection, time tagging of each received
frame with 100ns resolution, inter frame gap measurement with up to 40ns resolution
(1000Mbit: 8ns) and statistic features. Redundant operation of both ports is also
implemented with additional features like frame skew between both ports.
The hardware architecture provides ample resources (i.e. processing capability and up
to 3GByte of DDR3 memory) to guarantee, that all specified interface functions are
available concurrently and to full performance specifications.
The advanced architecture uses a SoC with integrated Dual-Core RISC processors,
tightly coupled to a large programmable logic. Core 1 of the Dual-Core processors is
running a Linux Operating system, supporting the Target Software application for high-
level protocol simulation and analysis. For fulfilling the real-time requirements of avionic
type networks, Core 2 is running a dedicated application for controlling the low-level
real-time functionality implemented within the programmable logic.
A freewheeling IRIG-B Time code Encoder/Decoder is implemented to satisfy the
requirements of 'multi-channel time tag synchronization' on the system level. The IRIG-
B compatible amplitude modulated sinewave output allows the synchronization of any
external module implementing IRIG-B time stamping.

1. Introduction
AXC-FDX-2 Hardware Manual
2
1.2 How This Manual is Organized
This AXC-FDX-2 Hardware Manual is comprised of following sections.
Section 1 –Introduction - contains an overview of this manual.
Section 2 - Installation - describes the steps required to install the AXC-FDX-2
device, and connect the device to other external interfaces including the
AFDX Network, IRIG-B, and triggers.
Section 3 - Structure of the AXC-FDX-2 - describes the physical hardware
interfaces of the AXC-FDX-2 using a block diagram and a description of
each main component
Section 4 - Technical Data - describes the technical specification of the
AXC-FDX-2
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent
that they are referenced herein. In the event of conflict between the documents
referenced and the contents of this document, the contents of this document shall have
precedence.
1.3.1 Industry Documents
ARINC 664 - Aircraft Data Network - Part 7: Avionics Full Duplex Switched Ethernet
(AFDX) Network
PCI Express BUS Specification; PCI-SIG, Revision 2.0
Draft Standard for XMC, VITA 42.0
Draft Standard for CMC, P1386 / Draft 2.4, January 12, 2001
Layer Standard for XMC PCI Express Protocol (VITA 42.3-2006)
1.3.2 Product Specific Documents
AIM - Reference Manual AXC-FDX-2 Application Interface Library
Detailed description of the programming interface between the Host Carrier board and
the on-board driver software.

2. Instalation
AXC-FDX-2 Hardware Manual
3
2 INSTALATION
2.1 Preparation and Precaution for Installation
The AXC-FDX-2 features full XMC Plug and Play capability, therefore, there are no
jumpers or switches on the board that require modification by the user in order to
interface to the XMC bus.
It is recommended to use a wrist strap for any installations. If there is no wrist wrap
available, then touch a metal plate on your system to ground yourself and discharge any
static electricity during the installation work.
2.2 Installation Instructions
The following instructions tell how to install the AXC-FDX-2 module in your system.
Please follow the instructions carefully, to avoid any damage on the device.
To Install the AXC-FDX-2
1. Switch off your system and all peripheral devices.
2. Unplug the power cord from the wall outlet. (Inserting or removing
modules with power applied may result in damage to module devices).
3. Touch a metal plate on your system to ground yourself and discharge any
static electricity.
4. Remove the carrier board from the system slot.
5. Replace the XMC Slot filler panel from the host front panel.
6. Place the AXC-FDX-2 mezzanine module on top of the carrier board, with
the XMC connectors on the AXC-FDX-2 aligned with the corresponding
connectors on the carrier board (see Figure 2-1).
Take care for correct size of the Bezel with ESD-gasket on ESD surface in
host front panel, and the correct size of the voltage keying pins.
7. Then connect the XMC connectors smoothly.
8. Align the standoffs on the AXC-FDX-2 module with the carrier board.
Install the screws through the holes in the carrier board and the spacers.
Tighten the screws.
9. Install the complete board into its proper card slot. Ensure the module is
seated properly in the backplane connectors. Take care not to damage or
bend connector pins. Secure the board.
10. Replace the cover of your system.
11. Connect the system to the power source. Turn on the power to your
system.

2. Instalation
AXC-FDX-2 Hardware Manual
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2.3 Connecting to Other Devices
The external interfaces of the AXC-FDX-2 consist of two RJ45 Ethernet connectors,
Trigger In/Out signal, Discrete IO signals, Ground as well as IRIG In/Out interface for
multi-channel time tag synchronization.
Figure 2-2: Front panel View of AXC-FDX-2
Figure 2-1: Installing the AXC-FDX-2 on a
XMC carrier module

2. Instalation
AXC-FDX-2 Hardware Manual
5
2.3.1 AFDX Connection
The AFDX connection is done via a standard RJ45 Ethernet connector located on the
Front panel of the AXC-FDX-2 module.
2.3.2 Trigger, Discrete and IRIG Connector
For multi-channel time tag synchronization an input for the on-board IRIG-Decoder and
an output for inter-board synchronization is available. The output format is an AIM
specific IRIG coded signal.
The connector also provides four Trigger input/output signals, which can be used with
dedicated applications. Additional up to 4 users definable Discrete I/Os are placed on
the connector.
This connector is implemented by a 3 row 15pin, female HD-SUB Connector. Technical
Details about the Trigger and Discrete lines can be found later in this document.
Pin No.
Signal Description
10/100Mbit
Signal Description
1000Mbit
1
TX+
D1+
2
TX-
D1-
3
Rx+
D2+
4
N.C.
D3+
5
N.C.
D3-
6
Rx-
D2-
7
N.C.
D4+
8
N.C.
D4-
Table 2-1 Pin Assignment for AFDX
Pin No.
Signal
1
IRIG Input
2
IRIG Output
3
Discrete I/O 1
4
Discrete I/O 2
5
GND
6
Discrete I/O 3
7
Trigger Input 1
8
Trigger Output 1
9
Trigger Input 2
10
Trigger Output 2
11
Trigger Input 3
12
Trigger Output 3
13
Trigger Input 4
14
Trigger Output 4
15
Discrete I/O 4
Table 2-2 Trigger, Discrete and IRIG Connector Pinout
Figure 2-3: Pinout DSUB

2. Instalation
AXC-FDX-2 Hardware Manual
6
The IRIG-IN and IRIG-OUT signals shall be connected depending on the time tag
method used as shown below.
1. Single AIM-Module no external IRIG-B source
No connection required
2. Multiple AIM-Modules with no common synchronization requirement
No connection required
3. Single or multiple AIM-Module(s) with external IRIG-B source
Connect external IRIG-B source to IRIG-IN and GND of all modules
4. Multiple AIM-Modules with no external IRIG-B source internally
synchronized.
Connect the IRIG-OUT signal and the GND of the module you have
chosen a as the time master to all IRIG-IN signals (including the time
master).

2. Instalation
AXC-FDX-2 Hardware Manual
7
2.3.3 AXC-FDX-2 Rear I/O Interface
Instead of using the front panel interface, the P14 PMC Rear I/O connector can be used
to access Trigger lines, Discrete I/O and the PXI Trigger Interface.
Please Note: Reserved pins may be already assigned for board maintenance
functionality, and therefore it is prohibited to connect them. Reserved pins must be left
unconnected. Otherwise the board could take serious damage.
PMC Connector P14
Pin
Signal
Signal
Pin
1
Reserved
Reserved
2
3
Reserved
Reserved
4
5
Reserved
Reserved
6
7
Reserved
Reserved
8
9
Signal-GND
Signal-GND
10
11
Signal-GND
Signal-GND
12
13
Reserved
Reserved
14
15
Signal-GND
Reserved
16
17
Signal-GND
Reserved
18
19
Reserved
Reserved
20
21
IRIG OUT
Reserved
22
23
IRIG IN
Reserved
24
25
Discrete IO1
Discrete IO3
26
27
Discrete IO2
Discrete IO4
28
29
Trigger In 1
Trigger In 3
30
31
Trigger Out 1
Trigger Out 3
32
33
Trigger In 2
Trigger In 4
34
35
Trigger Out 2
Trigger Out 4
36
37
Reserved
Reserved
38
39
Reserved
Reserved
40
41
PXI Trigger OE 4
Reserved
42
43
PXI Trigger OE 3
PXI GA 0
44
45
PXI Trigger OE 2
PXI GA 1
46
47
PXI Trigger OE 1
PXI GA 2
48
49
PXI STAR
PXI GA 3
50
51
PXI Clock 10MHz
PXI GA 4
52
53
Reserved
Reserved
54
55
Reserved
Reserved
56
57
Reserved
Reserved
58
59
Reserved
Reserved
60
61
Reserved
Reserved
62
63
Reserved
Reserved
64
Table 2-3 PMC P14 Rear I/O Pin Assignment

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3. Structure of the AXC-FDX-2
AXC-FDX-2 Hardware Manual
9
3 STRUCTURE OF THE AXC-FDX-2
The structure of the AXC-FDX-2 board is shown in the block diagram on the next page.
The AXC-FDX-2 comprises the following main sections:
System on a Chip design with
- Ethernet MAC
- PCIe 2.0 Endpoint with DMA Engine
- IRIG-B Synchronisation Unit
- ASP Processor Core with Embedded Linux operating system
- BIU Processor
- Memory Interface
Physical IO-Interface
- Gigabit Ethernet PHY
Trigger IN / OUT
Discrete IO
QSPI Boot flash
I2C EEPROM

3. Structure of the AXC-FDX-2
AXC-FDX-2 Hardware Manual
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Gigabit
Ethernet PHY
Gigabit
Ethernet PHY
RJ45
Transformer
RJ45
Transformer
Host XMC connector
PCIe Endpoint
1 GB
Processor
RAM
PS Dual-
Core
PCIe 2.0 x1
Z015
Quartz &
Clock Buffer
IRIG
Maintenance
Connector
DMA
Data
Handler
NAND / QSPI
Boot Flash
Discretes
Trigger
IRIG
NOVRAM
2 GB
RX RAM
(optional)
ETH
MAC
ETH
MAC
Figure 3-1: AXC-FDX-2 Block Diagram

3. Structure of the AXC-FDX-2
AXC-FDX-2 Hardware Manual
11
3.1 System on Chip (SoC)
The main part of the design is implemented within a SoC of the latest generation. This
SoC contains a Dual-Core RISC Processor running at up to 800 MHz, dedicated
hardware interfaces like DDR3 RAM controller, a PCIe 2.0 Endpoint and several
programmable interfaces for communication and memory attachment.
Additionally, a large programmable logic is directly attached to the Processing System
within this SoC, so fast access from the processor to the programmable logic is
guaranteed.
3.1.1 Ethernet MAC Features
The Programmable Logic contains two fully independent AFDX- specific MAC´s. Each
can receive and transmit fully compliant AFDX frames.
The decoder in each MAC receives, analyses and stores data with a data rate of up to
1000 MBit per second. The gap between two frames is measured with a resolution of
8ns at 1000Mbit/s, 40ns at 100 MBit/s and 400ns at 10 MBit/s. Minimum possible gap
time is 48 ns in 1000Mbit operation mode, 480ns for 100Mbit and 4,8us for 10Mbit.
Each received message is checked for errors in the MAC header and the IP header and
for errors on the physical bus.
The transmitter operates fully independent from the receiver. The transmitter is capable
of generating data independent from the BIU Processor, time tag insertion as payload
and error generation. Additionally, each frame can be started on several events like
inter frame spacing, trigger events, absolute time or on packet group wait timing.
Redundant operation of receiver and transmitter is also supported with additional
features like individual frame skew between the two ports.
3.1.2 PCI-Express Bus and DMA Engine
The FPGA architecture of AIM´s family of PCI Express based modules includes as Host
Interface a 1-lane PCIe 2.0 endpoint that provide 500 Mbyte/s upstream and
downstream bandwidth, concurrently. This State-of-the-Art Interface is commonly used
in modern PC Systems and provides enough performance to reach the necessary
bandwidth for the two 1GBit Ethernet Interfaces.
The FPGA logic includes independent DMA units for each Transmitter and Receiver.
The DMA engine will transfer TX data from Host memory to On-Board memory and
Receiver data from On-Board memory to Host memory. This is done fully independent
from any processor interaction to ensure maximum performance.

3. Structure of the AXC-FDX-2
AXC-FDX-2 Hardware Manual
12
3.1.3 IRIG- and Time Code Section
The main functions of the Time Code Processor (TCP) are:
a. IRIG-B compatible Time Code Decoder function
b. Time Code Encoder –IRIG-B compatible Time Encoder function
3.1.3.1 IRIG-B Synchronization Unit
The supported IRIG Time Code Format is B122.
B Bit Rate =100Hz, Bit Time = 10ms,
Bits/Frame =100, Frame Time = 1000mS, Frame Rate = 1Hz
1 Modulation type=Sine wave Carrier, amplitude modulated
2 Carrier Frequency = 1kHz (1ms resolution)
2 BCD coded
The time code information can be used for time-tagging and multi-channel
synchronization.
3.1.3.2 Timecode Encoder/Decoder
On the AXC-FDX-2 a freewheeling IRIG function is implemented. If no external IRIG
signal is detected, the IRIG Decoder switches automatically to the freewheeling
operation mode. If an external IRIG-B signal is detected in freewheeling mode, the Time
Tag is automatically synchronized to this external IRIG-B signal.
The time tag on the board is generated in the format shown below.
Time Element
Number of bits
DAYS of year
9
HOURS of Day
5
MINUTES of Hour
6
SECONDS of Minute
6
MICROSECONDS
of Second
20
100ns of Microsecond
4
Summary
50 (7 Bytes, stored in two 32bit words)
Table 3-1 Time Tag Format