Alinco DR-135 User manual

DR-135 / DR-435MkII
Service Manual
CONTENTS
SPECIFICATIONS
General..................................................................... 2
Transmitter ................................................................ 2
Receiver ................................................................... 2
CIRCUIT DESCRIPTION
1) Receiver System DR-135 ..................................... 3, 4
2) Transmitter System DR-135 ...................................... 5
3) PLL Synthesizer Circuit DR-135 ........................... 5, 6
4) Receiver System DR-435 ..................................... 6, 7
5) Transmitter System DR-435 ...................................... 8
6) PLL Synthesizer Circuit DR-435 ........................... 8, 9
7) CPU and Peripheral Circuit ................................. 9, 10
8) Power Supply Circuit............................................... 10
9) M38267M8L272GP (XA0851)........................... 11~13
SEMICONDUCTOR DATA
1) M5218AFP (XA0068).............................................. 14
2) NJM7808FA (XA0102) ............................................ 14
3) TC4S66F (XA0115) ................................................ 14
4) BU4052BF (XA0236) .............................................. 15
5) TA75S01F (XA0332) ............................................... 15
6) TC4W53FU (XA0348)............................................. 15
7) TA31136FN (XA0404)............................................. 16
8) LA4425A (XA0410)................................................. 16
9) M67746 (XA0412) .................................................. 17
10) M57788M (XA0077A) ............................................. 18
11) NJM2902V (XA0596).............................................. 19
12) 24LC32AT (XA0604) ............................................... 19
13) S-80845ALMP (XA0620) ........................................ 19
14) TK10931V (XA0666)......................................... 20, 21
15) L88MS05TLL (XA0675) .......................................... 22
16) M64076AGP (XA0915) ........................................... 23
17) Transistor, Diode and LED Outline Drawing ............ 24
18) LCD Connection (TTR3626UPFDHN) .................... 25
EXPLODED VIEW
1) Top and Front View ................................................. 26
2) Bottom View............................................................ 27
3) LCD Assembly........................................................ 28
PARTS LIST
CPU Unit .......................................................... 29, 30
MAIN Unit DR-135 ............................................ 30~33
MAIN Unit DR-435 ............................................ 33~36
VCO Unit DR-435 ................................................... 36
Mechanical Parts .............................................. 36, 37
Packing Parts.......................................................... 37
ACCESSORIES...................................................... 37
ACCESSORIES (SCREW SET).............................. 37
TNC (EJ41U) .......................................................... 38
TNC (EJ41U) Packing Parts ................................... 39
DR-135 ADJUSTMENT
1) Adjustment Spot .................................................... 40
2) VCO and RX Adjustment Specification ................... 41
3) Tx Adjustment Specification.................................... 41
4) Rx Test Specification............................................... 42
5) Tx Test Specification ............................................... 43
DR-435 ADJUSTMENT
1) Adjustment Spot .................................................... 44
2) VCO and RX Adjustment Specification ................... 45
3) Tx Adjustment Specification.................................... 46
4) Rx Test Specification............................................... 47
5) Tx Test Specification ............................................... 48
PC BOARD VIEW
1) CPU Unit Side A ..................................................... 49
2) CPU Unit Side B ..................................................... 49
3) MAIN Unit Side A DR-135 (UP0467A) .................... 50
4) MAIN Unit Side B DR-135 (UP0467A) .................... 50
5) MAIN Unit Side A DR-435 (UP0468A) .................... 51
6) MAIN Unit Side B DR-435 (UP0468A) .................... 51
7) TNC Unit Side A (UP0402) (option) ........................ 52
8) TNC Unit Side B (UP0402) (option) ........................ 52
SCHEMATIC DIAGRAM
1) CPU Unit DR-135 / DR-435 .................................... 53
2) MAIN Unit DR-135 .................................................. 54
3) MAIN Unit DR-435 .................................................. 55
4) TNC Unit (option).................................................... 56
BLOCK DIAGRAM
1) DR-135 ................................................................... 57
2) DR-435 ................................................................... 58
ALINCO,INC.

2
Frequency coverage DR-135 DR-435
T MkΙΙ 118.000 ~ 135.995MHz (AM RX)
136.000 ~ 173.995MHz (RX)
144.000 ~ 147.995MHz (TX)
350.000 ~ 511.995MHz (RX)
430.000 ~ 449.995MHz (TX)
E MkΙΙ 144.000 ~ 145.995MHz (RX,TX)
Operating mode FM 16K0F3E (Wide mode) 8K50F3E (Narrow mode)
Frequency resolution 5, 8.33, 10, 12.5, 15, 20, 25, 30, 50 kHz
Number of memory
Channels 100
Antenna impedance 50Ωunbalanced
Power requirement 13.8V DC ±15% (11.7 ~ 15.8V)
Ground method Negative ground
Current drain Receive 0.6A (max.) 0.4A (Squelched)
Transmit 11.0 A max. 10.0 A max
Operating temperature -10˚C ~ 60˚C
Frequency stability ±2.5 ppm
Dimensions 142 (w)×40 (h)×174 (d) mm
(142×40×188mm for projection included)
Weight Approx.
1.0Kg
Output power Hi 50W 35W
Mid 10W 10W
Low Approx.4W Approx.5W
Modulation system Variable reactance frequency modulation
Maximum Frequency deviation ±5kHz (Wide mode) ±2.5kHz (Narrow mode)
Spurious emission -60dB
Adjacent channel power -60dB
Noise and hum ratio -40dB (Wide mode) -34dB (Narrow mode)
Microphone impedance 2kΩ
Sensitivity -16dBu for 12dB SINAD
Receiver circuit Double conversion super-heterodyne
Intermediate frequency 1st 21.7MHz 2nd 450kHz 1st 30.85MHz 2nd 455kHz
Squelch sensitivity -18dBu
Adjacent channel selectivity -65dB (Wide mode) -55dB (Narrow mode)
Inter-modulation rejection ratio 60dB
Spurious and image rejection
ratio 70dB
Audio output power 2.0W (8Ω,10 %THD)
! NOTE : All specifications are subject to change without notice or obligation.
SPECIFICATIONS
General
Transmitter
Receiver

3
CIRCUIT DESCRIPTION
1) Receiver System DR-135
The receiver system is a double super-heterodyne system with a 21.7MHz first IF and a 450kHz second IF.
1. Front End The received signal at any frequency in the 136.000MHz to 173.995MHz range
is passed through the low-pass filter (L116, L115, L114, L113, C204, C203,
C202, C216 and C215) and tuning circuit (L105, L104 and D105, D104), and
amplified by the RF amplifier (Q107). The signal from Q107 is then passed
through the tuning circuit (L103, L102, and variable capacitor D103, D102)
and converted into 21.7MHz by the mixer (Q106). The tuning circuit, which
consistsofL105,L104,variablecapacitorD105andD104,L103,L102,variable
capacitor D103 and D102, is controlled by the tracking voltage from the VCO.
ThelocalsignalfromtheVCO is passed throughthebuffer(Q145),andsupplied
to the source of the mixer (Q106). The radio uses the lower side of the super-
heterodyne system.
2. IF Circuit The mixer mixes the received signal with the local signal to obtain the sum of
and difference between them. The crystal filter (XF102, XF101) selects 21.7
MHz frequency from the results and eliminates the signal of the unwanted
frequencies.ThefirstIFamplifier (Q105) thenamplifiesthesignalof the selected
frequency.
3. Demodulator Circuit After the signal is amplified by the first IF amplifier (Q105), it is input to pin24
of the demodulator IC (IC108). The second local signal of 21.25MHz (shared
with PLL IC reference oscillation), which is oscillated the external oscillator
X102 (VCTCXO), is input through pin 1 of IC108. Then, these two signals are
mixed by the internal mixer in IC108 and the result is converted into the second
IF signal with a frequency of 450kHz. The second IF signal is output from pin
3ofIC108tothe ceramic filter (FL102orFL101),wheretheunwanted frequency
band of that signal is eliminated, and the resulting signal is sent back to the
IC108 through pin 5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC 108, and output as an audio
signal through pin 12.

4
4. Audio Circuit The audio signal from pin 12 of IC 108 is amplified by the audio amplifier
(IC104:A, IC120), and switched by the signal switch IC (IC111) and then input
it to the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the de-emphasis
circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the
AF amplifier (IC104:D). The signal is then input to volume (VR1). The adjusted
signal is sent to the audio power amplifier (IC117) through the pin 1 to drive
the speaker.
5. Squelch Circuit The detected output which is outputted from pin 12 of IC108 is inputted to pin
19 of IC108 after it was been amplified IC104:A, IC120 and it is outputted from
pin 20 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the IC, then the signal is rectified by
the internal diode in IC108 to convert into DC component. The adjusted voltage
level at VR101 is delivered to the comparator of the CPU.The voltage is led to
pin 2 of CPU and compared with the setting voltage. The squelch will open if
the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes "L" level, AF control
signal is begin controlled and sounds is outputted from speaker.
6. AIR Band Reception (T only)
When the frequency is within 118.000 ~ 135.995MHz, Q110 automatically
turns on, pin 14 of IC 108 becomes "H" level and the condition becomes in AM
detection mode.
The receiver signal passed through the duplexer is let to the antenna switch
(D107, D101). After passing through the band-pass filter, the signal is amplified
by RF amplifier Q112. Secondly the signal is mixed with the signal from the
first local oscillator in the first-mixer Q106, then converted into the first IF. Its
unwanted signal is let to pin 24 of IC106. Then converted into the second IF.
And is demodulated by AM decoder of IC106, and is output from pin 13 as the
AF signal.
7. WIDE/NARROW Switching Circuit
The second IF 450kHz signal which passes through filter FL101 (wide) and
FL102 (narrow) during narrow, changes its width using the width control
switching IC103 and IC102.

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2) Transmitter System DR-135
1. Modulator Circuit The audio signal is converted to an electrical signal by the microphone, and
input it to the microphone amplifier (Q6). Amplified signal which passes through
mic-mute control IC109 is adjusted to an appropriate mic-volume by means of
mic-gain adjust VR106.
IC114:A and B consists of two operational amplifiers; one amplifier (pin 1, 2
and 3) is composed of pre-emphasis and IDC circuit and the other (pin 5, 6
and 7) is composed of a splatter filter. The maximum frequency deviation is
obtained by VR107. And input to the signal switch (IC113) (9600 bps packet
signal input switch) and input to the cathode of the variable capacitor of the
VCO, to change the electric capacity in the oscillation circuit. This produces
the frequency modulation.
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the drive amplifier
(Q145)andyoungeramplifier(Q115,Q144),andinputtothefinalpowermodule
(IC110). The signal is then amplified by the final power module (IC110) and
led to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116,
C215, C216, C202, C203 and C204), where unwanted high harmonic waves
are reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit Part of the transmission power from the low-pass filter is detected by D111
and D112, converted to DC. The detection voltage is passed through the APC
circuit (Q118, Q117, Q116), then it controls the APC voltage supplied to the
youngeramplifierQ115 and the final power module IC110 to fix the transmission
power.
3) PLL Synthesizer Circuit DR-135
1. PLL The dividing ratio is obtained by sending data from CPU (IC1) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC116). The oscillated signal from
the VCO is amplified by the buffer (Q134 and Q135) and input to pin 15 of
IC116. Each programmable divider in IC116 divides the frequency of the input
signal by N according to the frequency data, to generate a comparison
frequency of 5 or 6.25 kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by dividing
the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data
from the CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5, 10,
15,20,25, 30 and 50 kHz are used. When it is 6.25 kHz,the12.5kHzchannelstep
is used.

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3. Phase Comparator Circuit
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase
comparator in the IC116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained
by the internal divider in IC116.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference
frequency and the VCO output frequency, the charge pump output (pin 13) of
IC116 generates a pulse signal, which is converted DC voltage by the PLL
loop filter and input to the input to the variable capacitor of the VCO unit for
oscillation frequency control.
5. VCO Circuit A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency.
The frequency control voltage determine in the CPU (IC1) and PLL circuit is input
to the variable capacitor (D122 and D123). This change the oscillation frequency,
which is amplified by the VCO buffer (Q134) and output from the VCO area.
6. VCO Shift Circuit During transmission or the AIR band Reception (118 ~ 136 MHz), the VCO
shift circuit turns ON Q138, change control the capacitance of L123 and safely
oscillates the VCO by means of H signal from pin 16 of IC116.
4) Receiver System DR-435
The receiver system is a double super-heterodyne system with a 30.85MHz first IF and a 455kHz second IF.
1. Front End The received signal at any frequency in the 430.000MHz to 449.995MHz range
is passed through the low-pass filter ( L115, L114, L116, C204, C203, C202,
C216 and C215) and amplified by the RF amplifier (Q107). The signal from
Q107 is then passed through the BPF circuit (L103, L102) and converted into
30.85MHzbythemixer(Q106).Thelocalsignal fromtheVCOis passedthrough
the buffer (Q503, Q504), and supplied to the source of the mixer (Q106). The
radio uses the lower side of the super-heterodyne system.
2. IF Circuit The mixer mixes the received signal with the local signal to obtain the sum of
and difference between them. The crystal filter (XF101) selects 30.85 MHz
frequency from the results and eliminates the signal of the unwanted
frequencies.ThefirstIFamplifier (Q105) thenamplifiesthesignalof the selected
frequency.

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3. Demodulation CircuitAfter the signal is amplified by the first IF amplifier (Q105), it is input to pin16
of the demodulator IC (IC108). The second local signal of 30.395MHz (Crystal
oscillator) is input through pin 1 of IC108. Then, these two signals are mixed
by the internal mixer in IC108 and the result is converted into the second IF
signal with a frequency of 455kHz. The second IF signal is output from pin 3 of
IC108 to the ceramic filter (FL101 or FL102), where the unwanted frequency
band of that signal is eliminated, and the resulting signal is sent back to the
IC108 through pin 5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC 108, and output as an audio
signal through pin 9.
4. Audio Circuit The audio signal from pin 9 of IC 108 is amplified by the audio amplifier
(IC104:A), and switched by the signal switch IC (IC111) and then input it to the
de-emphasis circuit.
And is compensated to the audio frequency characteristics in the de-emphasis
circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the
AF amplifier (IC104:D). The signal is then input to volume (VR1). The adjusted
signal is sent to the audio power amplifier (IC117) through the pin 1 to drive
the speaker.
5. Squelch Circuit The detected output which is outputted from pin 9 of IC108 is inputted to pin 8
of IC108 after it was been amplified IC104:A and it is outputted from pin 7 after
the noise component was been eliminated from the composed band pass
filter in the built in amplifier of the IC, then the signal is rectified by the internal
diode in IC108 to convert into DC component. The adjusted voltage level at
VR101 is delivered to the comparator of the CPU.The voltage is led to pin 2 of
CPU and compared with the setting voltage. The squelch will open if the input
voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes "L" level, AF control
signal is begin controlled and sounds is outputted from speaker.
6. WIDE/NARROW Switching circuit
The second IF 455kHz signal which passes through filter FL101 (wide) and
FL102 (narrow) during narrow, changes its width using the width control
switching IC103 and IC102.

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5) Transmitter System DR-435
1. Modulator Circuit The audio signal is converted to an electrical signal by the microphone, and
input it to the microphone amplifier (Q6). Amplified signal which passes through
mic-mute control IC109 is adjusted to an appropriate mic-volume by means of
mic-gain adjust VR106.
IC114:A and B consists of two operational amplifiers; one amplifier (pin 1, 2
and 3) is composed of pre-emphasis and IDC circuit and the other (pin 5, 6
and 7) is composed of a splatter filter. The maximum frequency deviation is
obtained by VR107. And input to the signal switch (IC113) (9600 bps packet
signal input switch) and input to the cathode of the variable capacitor of the
VCO, to change the electric capacity in the oscillation circuit. This produces
the frequency modulation.
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the drive amplifier
(Q131,Q125)andyoungeramplifier(Q115),andinputtothefinalpowermodule
(IC110). The signal is then amplified by the final power module (IC110) and
led to the antenna switch (D110) and low-pass filter (L1163, L114, L115, C215,
C216, C202, C203 and C204), where unwanted high harmonic waves are
reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit Part of the transmission power from the low-pass filter is detected by D111
and D112, converted to DC. The detection voltage is passed through the APC
circuit (Q118, Q117, Q116), then it controls the APC voltage supplied to the
youngeramplifierQ115 and the final power module IC110tofixthetransmission
power.
6) PLL Synthesizer Circuit DR-435
1. PLL The dividing ratio is obtained by sending data from CPU (IC1) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC501). The oscillated signal from
the VCO is amplified by the buffer (Q503 and Q501) and input to pin 15 of
IC501. Each programmable divider in IC501 divides the frequency of the input
signal by N according to the frequency data, to generate a comparison
frequency of 5 or 6.25 kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by
dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according
to the data from the CPU (IC1). When the resulting frequency is 5 kHz, channel
step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5
kHz channel step is used.

9
3. Phase Comparator Circuit
The PLL (IC501) uses the reference frequency, 5 or 6.25 kHz. The phase
comparator in the IC501 compares the phase of the frequency from the VCO
with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the
internal divider in IC501.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference
frequency and the VCO output frequency, the charge pump output (pin 13) of
IC501 generates a pulse signal, which is converted DC voltage by the PLL
loop filter and input to the input to the variable capacitor of the VCO unit for
oscillation frequency control.
5. VCO Circuit A Colpitts oscillation circuit driven by Q502 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and PLL
circuit is input to the variable capacitor (D502 and D503). This change the
oscillation frequency, which is amplified by the VCO buffer (Q503, Q504) and
output from the VCO unit.
7) CPU and Peripheral Circuits
1. LCD Display Circuit The CPU turns ON the LCD via segment and common terminals with 1/4 the
duty and 1/3 the bias, at the frame frequency is 64 Hz.
2. Dimmer Circuit The dimmer circuit makes the output of pin 13 of CPU (IC1) into "H" level at
set mode, so that Q9 and Q3 will turn ON to make the lamp control resistor
R84 short and make its illumination bright. But on the other hand, if the dimmer
circuit makes pin 13 into "L" level, Q9 and Q3 will turn OFF, R84's illumination
will become dimmer as its hang on voltage falls down in the working LED
(D11, D2, D5, D3 and D6).
3. Reset and Backup When the power from the DC cable increases from Circuits 0 V to 2.5 V or
more, "H" level reset signal is output from the reset IC (IC4) to pin 33 of the
CPU (IC1), causing the CPU to reset. The reset signal , however, waits at 100,
and dose not enter the CPU until the CPU clock (X1) has stabilized.
4. S(Signal) Meter Circuit
The DC potential of IF IC is input to pin 1 of the CPU (IC1), converted from an
analog to a digital signal, and displayed as the S-meter signal on the LCD.

10
5. DTMF Encoder The CPU (IC1) is equipped with an internal DTMF encoder. The DTMF signal
is output from pin 10, through R35, R34 and R261 (for level adjustment), and
then through the microphone amplifier (IC114:A), and is sent to the variable
capacitor of the VCO for modulation. At the same time, the monitoring tone
passes through the AF circuit and is output from the speaker.
6. Tone Encoder The CPU (IC1) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor (D122
and D123) of the VCO for modulation.
7. DCS Encoder The CPU (IC1) is equipped with an internal DCS code encoder. The code
(023 to 754) is output from pin 9 of CPU to the variable capacitor (D124) of
the PLL reference oscillator. When DCS is ON, DCS MUTE circuit (Q126-
ON, Q133-ON, Q132-OFF) works. The modulation activates in X102 side
only.
8. CTCSS, DCS DecoderThe voice band of the AF output signal from pin 1 of IC104:A is cut by sharp
active filter IC104:B and C (VCVS) and amplified, then led to pin 4 of CPU.
The input signal is compared with the programmed tone frequency code in
the CPU. The squelch will open when they match. During DCS, Q108 is ON,
C156 is working and cut off frequency is lowered.
8) Power Supply Circuit
When power supply is ON, there is a "L" signal being inputted to pin 39 (PSW) of CPU which enables
the CPU to work.
Then, "H" signal is outputted from pin 41 (C5C) of CPU and drives ON the power supply switch
control Q8 and Q7 which turns the 5VS ON.
5VS turns ON the PLL IC (IC116), main power supply switch Q127 and Q122, AF POWER IC117
and the 8V of AVR (IC115).
During reception, pin 29 (R5) of CPU outputs "H" level, Q124 is ON, and the reception circuits
supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs "L" level which is reverse by
Q11 so that the output in Q128 will be "H" level, Q123 is ON, and the transmission circuit is supplied
by 8 V.
Or, in the case when the condition of PLL is UNLOCK, "H" level is outputted from pin 14 of PLL IC,
UNLOCK switch Q129 is ON, transmission switch Q128 is OFF which makes the transmission to
stop.
1. ACC External Power Supply Terminal
When optional power supply cord EDC-37 etc. is connected to the external
power supply terminal JK101, with ACC power supply ON, switch Q101 will
turn ON, 5 V of AVR IC101 pin 2 (STB) becomes "L" which makes C5V to turn
ON. With this, it can turn the power supply of the radio ON.

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9) M3826M8L272GP (XA0851)
CPU
Terminal Connection
(TOP VIEW)
272

12
No. Pin Name Function I/O PU Logic Description
1 P67/AN7 SMT I - A/D S-meter input
2 P66/AN6 SQL I - A/D Noise level input for squelch
3 P65/AN5 BAT I - A/D Battery voltage input
4 P64/AN4 TIN I - A/D CTCSS tone input/DSC code input
5 P63/SCLK22/AN3 BP1 I - A/D Band plan 1
6 P62/SCLK21/AN2 BP2 I - A/D Band plan 2
7 P61/SOUT2/AN1 DCSW O - Activ high DCS signal mute
8 P60/SIN2/AN0 RE2 I - Activ low Rotary encoder input
9 P57/ADT/DA2 TOUT O - D/A CTCSS tone output/DCS tone output
10 P56/DA1 DOUT O - D/A DTMF output
11 P55/CNTR1 SCL O - Pulse Serial clock for EEPROM
12 P54/CNTR0 TBST O - Pulse Tone burst output
13 P53/RTP1 BP4 I - - Band plan 4
14 P52/RTP0 MUTE I/O - Activ low Microphone mute/Security alarm SW
15 P51/PWM3 CLK O - Pulse Serial clock output for PLL,scramble
16 P50/PWM DATA I/O - Pulse
17 P47/SROY1 TSTB I/O - Activ low/Pulse
18 P46/SCLK1 STB O - Pulse Strobe for PLL IC
19 P45/TXD UTX O - Pulse UART data transmission output
20 P44/RXD RTX I - Pulse UART data reception output
21 P43/ /TOUT BEEP I/O - Pulse/Activ low Beep tone/Band plan 3
22 P42I/NT2 SEC I - Activ high Security voltage input
23 P41/INT1 RE1 I - Activ low Rotary encoder input
24 P40 DSQ I - Activ high Digital squelch input
25 P77 PTT I - Activ low PTT input
26 P7 SSTB O - Pulse/Activ low Strobe signal to scramble IC/Security mode
27 P75 W/N O - Activ low Wide Narrow SW
28 P74 T5 O - Activ low TX power ON/OFF output
29 P73 R5 O - Activ high RX power ON/OFF output
30 P72 SQC O - Activ low SQL ON/OFF
31 P71 C/S O - Activ low Digital scramble ON/OFF
32 P70/INTO BU I - Activ low Backup signal detection input
33 RESET RESET I - Activ low Reset input
34 Xcin Xcin - - - -
35 Xcout Xcout - - - -
36 Xin Xin - - - Main clock input
37 Xout Xout - - - Main clock output
38 Vss GND - - - CPU GND
39 P27 PSW I - Avtiv low Power switch input
40 P26 SDA O - Pulse Serial data for EEPROM
41 P25 C5C O - Activ high C5V power ON/OFF output
42 P24 AIR O - Activ high Air band SW / Tx middle power
43 P23 LOW O - Activ high Tx low power
44 P22 EXP O - Activ high Trunking data SW
45 P21 SW6 I Activ low Key sw6 (SQL)
46 P20 SW5 I Activ low Key sw5 (CALL)
47 P17 SW4 I Activ low Key sw4 (TSQ)
48 P16 SW3 I Activ low Key sw3 (MHz)
49 P15/SEG39 SW2 I Activ low Key sw2 (V/M)
50 P14/SEG38 SW1 I Activ low Key sw1 (FUNC)
51 P13/SEG37 DOWN I Activ low Mic down input
52 P12/SEG36 DUD I - - Digital unit detect
53 P11/SEG35 SCR I Active low Scramble IC ready signal/Packet PTT
54 P10/SEG34 UP I Active low Mic down input
55 P07/SEG33 S33 O - - LCD segment signal
Serial data output for PLL scramble/PLL unlock signal input
Trunking board detection / Strobe signal to trunking board

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No. Pin Name Function I/O PU Logic Description
56 P06/SEG32 S32 O - -
57 P05/SEG31 S31 O - -
58 P04/SEG30 S30 O - -
59 P03/SEG29 S29 O - -
60 P02/SEG28 S28 O - -
61 P01/SEG27 S27 O - -
62 P00/SEG26 S26 O - -
63 P37/SEG25 S25 O - -
64 P36/SEG24 S24 O - -
65 P35/SEG23 S23 O - -
66 P34/SEG22 S22 O - -
67 P33/SEG21 S21 O - -
68 P32/SEG20 S20 O - -
69 P31/SEG19 S19 O - -
70 P30/SEG18 S18 O - -
71 SEG17 S17 O - -
72 SEG16 S16 O - -
73 SEG15 S15 O - -
74 SEG14 S14 O - -
75 SEG13 S13 O - -
76 SEG12 S12 O - -
77 SEG11 S11 O - -
78 SEG10 S10 O - -
79 SEG9 S9 O - -
80 SEG8 S8 O - -
81 SEG7 S7 O - -
82 SEG6 S6 O - -
83 SEG5 S5 O - -
84 SEG4 S4 O - -
85 SEG3 S3 O - -
86 SEG2 S2 O - -
87 SEG1 S1 O - -
88 SEG0 S0 O - -
LCD segment signal
89 Vcc VDD - - - CPU power terminal
90 Vref Vref - - - AD converter power supply
91 Avss Avss - - - AD converter GND
92 COM3 COM3 O - - LCD COM3 output
93 COM2 COM2 O - - LCD COM2 output
94 COM1 COM1 O - - LCD COM1 output
95 COM0 COM0 O - - LCD COM0 output
96 VL3 VL3 - - -
97 VL2 VL2 - - - LCD power supply
98 C2 I - - - -
99 C1 C1 - - - -
100 VL1 VL1 I - A/D LCD power supply

14
SEMICONDUCTOR DATA
1) M5218FP (XA0068)
Power Supply Plus
Output 2
Inverting Input 2
Non Inverting Input 2
8
7
6
5
Output 1
Inverting Input 1
Non Inverting Input 1
Power supply Minus
1
2
3
4
Dual Low Noise Operational Amplifiers
2) NJM7808FA (XA0102)
1. OUTPUT
2. COMMON
3. INPUT
Voltage Regulator
123
3) TC4S66F (XA0115)
Bilateral Switch

15
4) BU4052BF (XA0236)
Analog Multiplexer/De-multiplexer
5) TA75S01F (XA0332)
54
132
S A
54
132
Vcc
IN(+) IN(-)V
EE
OUT
+
-
Printing
(top view) Pin Assignment (top view)
Single Operational Amplifer
6) TC4W53FU (XA0348)
Control input ON channel
INH
L
L
H
A
L
H
*
ch0
ch1
NONE
* Don't Care
FunctionTable
Multiplexer/De-multiplexer
COMMON
INH
VEE
VSS
VDD
ch0
ch1
A

16
7) TA31136FN (XA0404)
Narrow Band FM IF IC
8) LA4425A (XA0410)
4
+
+
+
12345
Input
1000µF
2.2µF
1000µF
13.2V
Vcc
SP
1
2
5
34Ω
Vcc=13.2V RL=4 Po =5W Gain= 45dB
LA4425
5W Audio Power Amplifier
Test Circuit

17
9) M67746 (XA0412)
PIN:
P
in : RF INPUT
V
CC1 : 1st. DC SUPPLY
V
CC2 : 2nd. DC SUPPLY
P
O : RF OUTPUT
GND: FIN
BLOCK DIAGRAM
1
2
3
4
5
Symbol Parameter Test conditions Limits
Min Max Unit
f
P
O
η T
2f O
ρ in
Frequency range
Output power
Total efficiency
2nd. harmonic
Input VSWR V
CC1 =V CC2 =15.2V
P
O =60W (P in :controlled), Z G =50Ω
Load VSWR=8:1 (All phase)
144 148
50 -30
No degradation or
destroy
MHz
W
%
dBc
-
Note. Above parameters, ratings, limits and test conditions are subject to change.
ELECTRICAL CHARACTERISTICS (Tc=25˚C unless otherwise noted)
Symbol Parameter Conditions Ratings Unit
ABSOLUTE MAXIMUM RATINGS (Tc=25˚C unless otherwise noted)
Note. Above parameters are guaranteed independently.
VV CC Supply voltage A20I
CC Total current mW600P
in (max) Input power W70P
O (max) Output power ˚C-30 to +110T
C (OP) Operation case temperature ˚C-40 to +110T
stg Storage temperature
Z
G =Z L =50Ω
Z G =Z L =50Ω17
5
4
2 3
1
Load VSWR tolerance-
Z
G =Z L =50Ω, V CC1 ≤12.5V
V
CC1 =V CC2 =12.5V, P in =300mW
Z
G =Z L =50Ω
3f O 3rd. harmonic -30 dBc
-
3
60
Z G =Z L =50Ω, V CC1 ≤12.5V
Z
G =Z L =50Ω, V CC1 ≤12.5V
OUTLINE DRAWING
66±0.5
60±0.5
51.5±0.5
2-R2±0.5
16.5±1
H2
Dimensions in mm
12±1
1 2 3 4 5
7.25±0.8
3±0.3
43.5±1
55.5±1
φ 0.82±0.15
21±0.5
4±0.3
10±0.5
(9.8)
1.5+0.8
-0
21.5±0.5 22.5±0.514±1
2.3±0.3 3.1±0.4
7.5+0.8
-0
144~148MHZ 60W RF Power Module

18
10) M57788M (XA0077A)
4
30~450MHz 40W RF Power Module

19
11) NJM2902V (XA0596)
1. A OUTPUT 8. C OUTPUT
2. A−INPUT 9. C−INPUT
3. A+INPUT 10. C + INPUT
4.V+11. GND
5. B + INPUT 12. D + INPUT
6. B−INPUT 13. D−INPUT
7. B OUTPUT 14. D OUTPUT
Quad Operational Amplifiers
12) 24LC32A (XA0604)
A0
A1
A2
Vss SDA
SCL
WP
Vcc Name Function
Vss Ground
A0..A2 User Configurable Chip Selects
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
Vcc +2.5V~6.0V Power Supply
EEPROM
13) S-80845ALMP (XA0620)
Voltage Detector

20
14) TK10931V (XA0666)
TEST CIRCUIT
~
51 10.7 MHz
VCC
0.01 µF
+
10 µF 51 k
+
1 µF
+
1 µF
270 k
1 k +10 µF
20 k 20 k
10
k
0.1 µF
10
k
0.1 µF
VCC 8.2 k
0.01 µF
10 k
0.01 µF
7BRE-7437Z
0.1 µF
30 k
10 pF
0.1 µF
0.1 µF
10.245 MHz
33 pF
120 pF
CFU455F
0.1 µF 0.1 µF
+
VCC
0.01 µF 10 µF
30 k
~
OSC MIXER
COMP
ECT
+
-
AMP
Vref
AGC AM DET
RSSI
Narrow Band AM/FM IF IC