AMD XILINX VPK180 User manual

VPK180 Evaluaon Board
User Guide
UG1582 (v1.0) February 21, 2023
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Overview.......................................................................................................................................4
Navigating Content by Design Process.................................................................................... 5
Additional Resources.................................................................................................................. 5
Block Diagram..............................................................................................................................6
Board Features............................................................................................................................ 7
Board Specifications................................................................................................................. 10
Chapter 2: Board Setup and Configuration....................................................12
Standard ESD Measures........................................................................................................... 12
Board Component Location.....................................................................................................12
Default Jumper and Switch Settings....................................................................................... 18
Versal ACAP Configuration.......................................................................................................21
Chapter 3: Board Component Descriptions................................................... 23
Overview.....................................................................................................................................23
Component Descriptions......................................................................................................... 23
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 71
Overview.....................................................................................................................................71
Appendix B: Xilinx Design Constraints............................................................. 72
Overview.....................................................................................................................................72
Appendix C: Regulatory and Compliance Information........................... 73
CE Information...........................................................................................................................73
Compliance Markings............................................................................................................... 74
Appendix D: Additional Resources and Legal Notices.............................75
Xilinx Resources.........................................................................................................................75
Documentation Navigator and Design Hubs.........................................................................75
References..................................................................................................................................76
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Revision History.........................................................................................................................77
Please Read: Important Legal Notices................................................................................... 77
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Chapter 1
Introduction
Overview
The VPK180 evaluaon board features the Xilinx® Versal® ACAP XCVP1802 device. The
VPK180 board enables the demonstraon, evaluaon, and development of the applicaons listed
here, as well as other customer applicaons. Many features found on the VPK180 board are
subsets of exisng Versal ACAP boards (e.g., the VCK190 and VMK180 boards).
• Fiber opc
•Communicaons
• Data center compute acceleraon
• Aerospace and defense
• Test and measurement
The VPK180 evaluaon board is equipped with many of the common board-level features
needed for design development, including:
• OSFP opcal transceiver support
• QSFP-DD opcal transceiver support
• SFP-DD opcal transceiver support
• LPDDR4 component memory
• USB
• Ethernet networking interface
• One FMC+ expansion port
Models of Boards
The following table lists the models for the VPK180 evaluaon board. See the VPK180
Evaluaon Board product page for details
Chapter 1: Introduction
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Table 1: Models of VPK180 Evaluation Boards
Kit Description
EK-VPK180-G Xilinx Versal ACAP VPK180 evaluation kit
EK-VPK180-G-J Xilinx Versal ACAP VPK180 evaluation kit, Japan specific
Versal ACAP Kit Numbering
The Versal ACAP kit numbering is illustrated in the following gure.
Figure 1: Kit Numbering
EK - VP
Kit
Type
Options
EK –Evaluation Kit
CK –Characterization Kit
K 180 - G - J
ROHS
Indicator
Regional
Identifier
Silicon indicator
K = kit
Ensures there is no
confusion with silicon P/Ns
Family and series
(e.g., Versal ACAP
and Core)
Examples
VPK120
VCK190
Options
G –ROHS
Compliant
Options
J –Japan
OEM –OEM kit
Product Number
X26520-111822
Navigating Content by Design Process
Xilinx® documentaon is organized around a set of standard design processes to help you nd
relevant content for your current development task. All Versal® ACAP design process Design
Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This
document covers the following design processes:
•Board System Design: Designing a PCB through schemacs and board layout. Also involves
power, thermal, and signal integrity consideraons. For more informaon, see Versal ACAP
Design Process Documentaon Board System Design.
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VPK180 evaluaon board.
Chapter 1: Introduction
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Block Diagram
A block diagram of the VPK180 evaluaon board is shown in the following gure.
Figure 2: Evaluation Board Block Diagram
GTYP
GTYP
GTM
GTM
GTM
GTM
GTM
PS/
PMC
2x LPDDR4
(1x32)
2x QSPI
GPIO 3.3V
SFP/QSFP/
OSFP Ctrl
FMC+
(XPIO)
2x LPDDR4
(1x32)
USB 2.0 ULPI
SD 3.0
UART/I2C
GEM 2x LPDDR4
(1x32) EMIO
Mictor
1588 CLK SMAs
SysC
GPIO
Lvl
Shftrs
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
QSFPDD_3
56G capable
SFPDD_2
56G/112G capable
SFPDD_1
56G/112G capable
QSFPDD_1
112G capable
QSFPDD_2
56G capable
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
QSFPDD_4
56G capable
SFPDD_4
56G/112G capable
SFPDD_3
56G/112G capable
OSFP
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
GTM
QSFPDD_5
112G capable
QSFPDD_6
112G capable
Power Enables
SLR Crossing
SLR Crossing
SLR Crossing
124
123
122
121
118
117
116
115
112
111
110
109
206
205
204
203
202
201
200
212
211
210
209
208
207
218
217
216
215
214
213
224
223
222
221
220
219
HSDP
USB Type-C
HSDP
SYSCTLR GTH
1588 SMA
Versal XCVP1802
LSVC4072
XPIO
GTYP
GTYP
GTYP
GTYP
GTYP
106
105
104
103
102
Lvl
Shftrs
X26519-110222
Chapter 1: Introduction
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Board Features
The VPK180 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• XCVP1802, LSVC4072 package
• Form factor: see Board Specicaons
• Onboard conguraon from:
○USB-to-JTAG bridge
○JTAG pod 2 mm 2x7 at cable connector
○microSD card (PS MIO I/F)
○Quad SPI (QSPI)/eMMC (system controller I/F)
○Dual QSPI
• Clocks
○ACAP bank 702/5/8 Si570 LPDDR4_CLK1/2/3 (DIMM) 200 MHz
○ACAP bank 503 Si570 REF_CLK 33.3333 MHz
○ACAP bank 503 RTC Xtal 32.768 kHz
○IEEE-1588 eCPRI 8A34001 clocks (various)
○ACAP bank GTY102/4 (REFCLK0) HSDP dedicated clocks
○ACAP bank GTY200/1 (REFCLK0) FMC provided
○ACAP banks GTM109, GTM110, GTM111, GTM112, GTM115, GTM116, GTM117,
GTM118 RC21008A 156.25 MHz
○ACAP banks GTM208, GTM209, GTM210, GTM211, GTM214, GTM215, GTM216,
GTM217 RC21008A 156.25 MHz
• Three LPDDR4 interfaces (2x32-bit 4 GB components each)
○XPIO triplet 1 (banks 700, 701, 702)
○XPIO triplet 2 (banks 703, 704, 705)
○XPIO triplet 3 (banks 706, 707, 708)
• PL FMCP HSPC (FMC+) connecvity
○FMCP1 HSPC full LA[00:33] bus
Chapter 1: Introduction
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• PL GPIO connecons
○PL UART1 to FTDI
○PL GPIO DIP switch (4-posion)
○PL GPIO LEDs (four)
○PL GPIO pushbuons (two)
○PL trace connector (J332)
○PL SYSCTLR_GPIO[0:15]
○PL 8A34001_GPIO[0:7, 10:15]
• 28 PL GTYP transceivers (7 quads)
○Not used (18, bank GTYP102, GTYP103, GTYP104, GTYP105, GTYP106)
○System controller HSDP (1, banks GTYP104)
○USB-C HSDP (1, banks GTYP102)
○FMCP1 HSPC DP (8, banks GTYP200, GTYP201)
• 140 PL GTM transceivers (35 quads)
○Not used (74, bank GTM109, GTM110, GTM115, GTM116, GTM121, GTM122, GTM123,
GTM124, GTM202, GTM203, GTM204, GTM205, GTM206, GTM207, GTM212,
GTM213, GTM214, GTM215, GTM216, GTM217, GTM218, GTM219, GTM220,
GTM221, GTM222, GTM223, GTM224)
○QSFPDD1 (8, banks GTM208, GTM209, GTM210, GTM211)
○QSFPDD2 (8, banks GTM208, GTM209, GTM210, GTM211)
Note: QSFPDD1 and QSFPDD2 are interleaved.
○QSFPDD3 (8, banks GTM111, GTM112)
○QSFPDD4 (8, banks GTM117, GTM118)
○QSFPDD5 (8, banks GTM121, GTM122, GTM123, GTM124)
○QSFPDD6 (8, banks GTM221, GTM222, GTM223, GTM224)
○OSFP (8, banks GTM214, GTM215, GTM216, GTM217)
○SFPDD1 (2, bank GTM109)
○SFPDD2 (2, bank GTM110)
○SFPDD3 (2, bank GTM115)
○SFPDD4 (2, bank GTM116)
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○User SMA connectors (1, bank GTM219)
○8A34001 CLK (1, bank GTM219)
• PS PMC MIO connecvity
○PS MIO[0:12]: boot conguraon QSPI
- DC QSPI support
○PS MIO[13:25]: USB2.0
○PS MIO[26:36, 51]: SD1 I/F
○PS MIO[37]: ZU4_TRIGGER
○PS MIO[38]: Not connected
○PS MIO[39:41]: SYSMON_I2C
○PS MIO[42:43]: UART0 to FTDI
○PS MIO[44:47]: I2C1, I2C0
○PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
○PS MIO[49] and LPD MIO[13,15:16,20]: power enable
○PS MIO[50] and LPD MIO[18:19]: Not connected
○PS LPD MIO [21:22]: oponal fan interface
○LPD MIO[23]: VADJ_FMC power rail
• Security: PSBATT buon baery backup
• SYSMON header
•Operaonal switches (power on/o, PROG_B, boot mode DIP switch)
•Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
○See Power and Status LEDs
• Power management
• System controller (XCZU4EG)
The VPK180 evaluaon board provides a rapid prototyping plaorm using the
XCVP1802-2MSELSVC4072 device. See the Versal Architecture and Product Data Sheet: Overview
(DS950) for a feature set overview, descripon, and ordering informaon.
Chapter 1: Introduction
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Board Specifications
Dimensions
Height: 12.360 inches (31.394 cm)
Length: 11.504 inches (29.22016 cm)
Thickness: 131.5 mil ±10% (3.3401 ±10%)
Note: A 3D model of this board is not available.
See the VPK180 Evaluaon Board website for the XDC lisng and board schemacs.
Environmental
Note: The operang temperature range is not fully tested across the specied temperature range. It is for
general guidelines only. Customers should use the VPK180 evaluaon board for evaluaon purposes only
in a normal lab environment and should not operate beyond room temperature.
•Temperature:
Operang: 0°C to +45°C
Storage: –25°C to +60°C
•Humidity: 5% to 95% non-condensing
Operating Voltage
+12 VDC
Mechanical
The VPK180 evaluaon board includes a mechanical sener to help ensure success with the
board under normal lab condions and use. While it is recommended to not remove this sener,
it is understood that it might be necessary to remove it for connued evaluaon.
The mechanical sener screw torque is 4.5 in-lbs. When aaching or removing the mechanical
sener, ensure proper ESD precauons are taken. See Standard ESD Measures for suggesons
on best pracces.
• Removing the Sener
With power and other cabling unplugged, carefully unscrew the eleven 4-40 screws in any
order. Care needs to be taken with the cooling soluon as the board is manipulated due to
potenal excessive forces.
•Aaching the Sener
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With power and other cabling unplugged, carefully align the PCBA stando holes to the sheet
metal tray (sener) standos. Next, it is suggested to insert two screws in opposite corners
of the board/tray combinaon. Loosely ghten the screws to aid in alignment. Add the
remaining seven screws and loosely ghten. Finally, in a le to right or right to le paern,
ghten all nine screws to 4.5 in-lbs.
Note: The tray will only t one direcon with the transceiver connectors having cutouts below. See Board
Component Descripons for more informaon.
Chapter 1: Introduction
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Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in
total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
•Aach a wrist strap to an unpainted metal surface of your hardware to prevent electrostac
discharge from damaging your hardware.
• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for
stac control. It does not increase or decrease your risk of receiving electric shock when you
are using or working on electrical equipment.
• If you do not have a wrist strap, before you remove the product from ESD packaging and
installing or replacing hardware, touch an unpainted metal surface of the system for a
minimum of ve seconds.
• Do not remove the device from the anstac bag unl you are ready to install the device in
the system.
• With the device sll in its anstac bag, touch it to the metal frame of the system.
• Grasp cards and boards by the edges. Avoid touching the components and gold connectors on
the adapter.
• If you need to lay the device down while it is out of the anstac bag, lay it on the anstac
bag. Before you pick it up again, touch the anstac bag and the metal frame of the system at
the same me.
• Handle the devices carefully to prevent permanent damage.
Board Component Location
The following gure shows the VPK180 board component locaons. Each numbered component
shown in the gure is keyed to the table in Board Component Descripons.
Chapter 2: Board Setup and Configuration
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IMPORTANT! The following gure is for visual reference only and might not reect the current revision of
the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be a
reference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic VPK180 version of interest for such details.
Chapter 2: Board Setup and Configuration
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Figure 3: Evaluation Board Component Locations
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
1
2
3
4
5
6
7
8
10
9
9
11
11
12
12
13
14
14
14
15
15
15
16
17
18
19
19
20
20
21
21
22
23
24
25
26
28
2930
31
32
33
34
34
35
35
36
37
38
39 40
41
41
43 42
44
45
46
47
48
49 50
51
52 53
54
55
X27290-101422
Chapter 2: Board Setup and Configuration
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Board Component Descriptions
The following table idenes the components and references the respecve schemac
(038-05088-01) page numbers.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the VPK180 board power
connector J16. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-pin
connector into J16 damages the VPK180 board and voids the board warranty.
Table 2: Board Component Locations
Callout
No. Ref. Des. Feature Notes Schematic Page
1 U1 Versal® ACAP XCVP1802-2MSELSVC4072
The heatsink is not shown in Figure 31
3-23
2 U25, U26 LPDDR4 16 GBIT comp.
memory (B700-B702 IF)
Micron MT53D512M32D2DS-046
IC SDRAM LPDDR4 512Mx32 2133 MHz
3,39,40
3 U150, U151 LPDDR4 16 GBIT comp.
memory (B703-B705 IF)
Micron MT53D512M32D2DS-046
IC SDRAM LPDDR4 512Mx32 2133 MHz
4,42,41
4 U246, U247 LPDDR4 16 GBIT comp.
memory (B706-B708 IF)
Micron MT53D512M32D2DS-046
IC SDRAM LPDDR4 512Mx32 2133 MHz
5,43,44
5 J11 SYSMON header Sullins PBC06DAAN
Conn. hdr. vert. 12 pos. 2x6 2.54 mm pitch
20
6 J36 ACAP JTAG 2 mm 2x7 flat-cable
connector
Molex 0878321420
Conn. hdr. male vert. 14 pos 2x7 2 mm
35
7 J332 Mictor-38 Arm® trace
connector
TE connectivity AMP connectors
2-5767004-2
Conn. hdr. MICTOR 38 pos. 2x19 0.635 mm
38
8 J310 8A34001 I2C 2 mm 2x9 flat-
cable connector
Molex 0878321820
Conn. hdr. male vert. 18 pos. 2x9 2 mm
111
9 J369, U20 USB-UART bridge, USB Type-C
connector (USB2.0)
Amphenol 12401598E4#2A
FTDI FT4232HL-REEL
36
10 J308, U99 USB 2.0 type-A connector, USB
ULPI transceiver
Wurth 629104190121, USB 2.0 type-A
Microchip USB3320C USB 2.0 Xcvr
53
11 J302, U104 SD card socket, Versal ACAP SD
3.0 level translator circuit
Molex 5025700893
Micro SD card cage
51
12 U33, U35 I2C bus switches Texas Instruments TCA9548APWR
IC switch bus 1-In 8-Outs I2C 400 kHz
Bottom of board
55,56
13 U233 I2C bus expander Texas Instruments TCA6416APWR
IC exp. GPIO 16-bit I2C 400 kHz
Bottom of board
55
14 J1, J2, J354,
J355, J358, J359
QSFP-DD 112G connector Molex 2147334000
QSFP-DD 112G connector and cage
57-59
15 J350, J352, J385,
J387
SFP-DD 56G connector Molex 2047301000
SFP-DD 56G connector and cage
63,64
Chapter 2: Board Setup and Configuration
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Table 2: Board Component Locations (cont'd)
Callout
No. Ref. Des. Feature Notes Schematic Page
16 J307 GEM0 SGMII Ethernet PHY,
0x01, RJ45 w/mag
Halo HFJ11-1G01E-L12RL
RJ-45 Gigabit connector
52
17 J51 FMCP1 Samtec ASP-184329-01
560 pos. connector 14x40 1.27 mm
46-50
18 Various ACAP power management
system (VCCINT, VCC_SOC)
Infineon regulators 67-73,75
19 U160, U293 VCC_PMC/PSFP/VCCO_MIO/
VCCAUX/VCC1V5/UTIL_3V3
regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
76,77
20 U167, U294 VCCRAM_VCCINT/
LPDMGTYAVCC/MGTVCCAUX/
MGTAVCC regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
78,79
21 U175, U296 VCCAUX/UTIL_2V5/
VCC_PSLP_CPM5/
LPMGTYVCCAUX regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
80,81
22 U295 UTIL_1V8/VCCAUX_PMC/
LPDMGTYAVTT regulator
Infineon IRPS5401MTRPBF
IC PMU 5-Ch step-down DC/DC
82
23 U259 LPDMGTYAVTT regulator Infineon IR38060MTRPBF
IC REG BUCK ADJ 6A
85
24 U185 VADJ_FMC regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
86
25 U187 VCC1V1_LP4 regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
87
26 U189 MGTYAVTT regulator Infineon IR38164MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
88
28 U191 UTIL_5V0 regulator Infineon IR3889MTRPBFAUMA1
IC V. reg. step-down DC/DC sync
89
29 J325 PMBus 3-pin header Sullins PBC03SAAN
Conn. hdr. vert. 3 pos. 1x3 2.54 mm
55
30 Various Power good LEDs (see Power
and Status LEDs for more
details)
Various; see the Bill of Materials 91
31 J16 Power connector, 2x3, for AC-
DC power adapter
Molex 0039301060
Conn. ddr. RA 6 pos. 2x3 4.2 mm
66
32 JP1, JP2, JP3, JP4 Power connector, 2x4, for ATX
PCIe power
Astron 6652208-T0003T-H
Conn. hdr. male RA 8 pos. 2x4 4.2 mm
66
33 J233 Fan header (keyed 4-pin) Molex 0470533000
Keyed fan header 4 pos. 0.100" vert.
66
34 U298, U299 MGT clock generators Renesas RC21008A065GND#BB0 61,62
35 J370, J371 RC21008A_GTCLK1/2 header Molex 0878321820 61,62
36 U11, U12 ACAP U1 QSPI Micron MT25QU01GBBB8E12-0SIT
IC flash NOR SPI 1 Gb
45
37 U32 ACAP U1 REF CLK, 33.33 MHz,
1.8V CMOS, 0x5D
Skyworks/Silicon Labs 570JAC000900DGR
Osc. XO 10-280 MHz
Bottom of board
54
Chapter 2: Board Setup and Configuration
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Table 2: Board Component Locations (cont'd)
Callout
No. Ref. Des. Feature Notes Schematic Page
38 U248 LPDDR4 CLK1, 200 MHz, 3.3V
LVDS, 0x60
Skyworks/Silicon Labs 570BAB000299DGR
Osc. XO 10-810 MHz
Bottom of board
3
39 U3 LPDDR4 CLK2, 200 MHz, 3.3V
LVDS, 0x60
Skyworks/Silicon Labs 570BAB000299DGR
Osc. XO 10-810 MHz
Bottom of board
4
40 U4 LPDDR4 CLK3, 200 MHz, 3.3V
LVDS, 0x60
Skyworks/Silicon Labs 570BAB000299DGR
Osc. XO 10-810 MHz
Bottom of board
5
41 J373, J374, J375,
J376, J393, J394,
J395, J396
ACAP GTM female vertical 12.4
GHz SMT screw connector
Rosenberger 32K10K-400L5
Conn. rcpt. SMA vert. 50R 12.4 GHz
11
42 DS1 Done LED (Active-High-Z and
pulled High)
Lumex SML-LX0603GW-TR
LED green
22
43 DS2 Error out LED (Active-High-Z
and pulled High)
Lumex SML-LX0603IW-TR
LED red
22
44 DS3, DS4, DS5,
DS6
User LEDS Lumex SML-LX0603GW-TR
LED green
65
45 U251, U252,
U257
IEEE-1588 eCPRI input clock
multiplexer
Renesas 8P34S1204NLGI8IC buffer Clk 2 to 4
1.8-2.5V 10 mA 1.5 GHz LVDS
113
46 U219 IEEE-1588 eCPRI CLK, various,
3.3V, 0x58
IDT 8A34001E-000AJG8
IC synch. man. unit 8-Ch 24 LVCMOS
Bottom of board
111,112
47 J328, J329, J338 IEEE-1588 eCPRI 8A34001 CLK
in SMA
Rosenberger 32K10K-400L5
Conn. rcpt. SMA vert. 50R 12.4 GHz
111
48 J330, J331, J339 IEEE-1588 eCPRI 8A34001 CLK
out SMA
Rosenberger 32K10K-400L5
Conn. rcpt. SMA vert. 50R 12.4 GHz
111
49 U125 XCZU4EG system controller Xilinx® XCZU4EG-2SFVC784E
FPGA MPSoC Zynq UltraScale+
93-101
50 U319 SYSCTLR clocks 33.33 MHz and
26 MHz USB and 156.25 MHz
HSDP REFCLK 0x6A
Skyworks/Silicon Labs Si5332FD10259-GM1
Low jitter clock generator with 6 outputs
108
51 U132 System controller LPDDR4 16
GBIT comp. memory
Micron MT53D512M32D2DS-046 WT:D
IC SDRAM LPDDR4 16 Gb 512Mx32 2133
MHz
105
52 J349 System controller SGMII
Ethernet, RJ45 w/magnetics
Halo HFJ11-1G01E-L12RL
RJ-45 Gigabit connector
103
53 J7, U19 System controller USB 3.0 type-
B connector , USB ULPI
transceiver
Wurth 692622030100, USB 3.0 type-B
Microchip USB3320C USB 2.0 Xcvr Bottom of
board
107
54 DS34 System controller done LED
(active-High)
Lumex SML-LX0603GW-TR
LED green
97
55 J362 OSFP 112G connector TE connectivity 2344064-4
OSFP 112G connector and cage
60
Notes:
1. The VPK180 evaluation board includes a heatsink with a thermal resistance of 0.38°C/W.
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Default Jumper and Switch Settings
The following gure shows the VPK180 board jumper header and switch locaons. Each
numbered component shown in the gure is keyed to the applicable table in this secon. Both
tables reference the respecve schemac page numbers.
Figure 4: Board Jumper Header and Switch Locations
1
2 3
4
5
8
7
9
10
11
12 13
15
17
18
20
16
14
21
6
19
X27291-101322
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Jumpers
The following table lists the default jumper sengs.
Table 3: Default Jumper Settings
Callout
Number Ref. Des. Function Default Schematic Page
1 J11 SYSMON VREFP SEL
1-2: External VREF
2-3: Disable external VREF
1-2 20
2 J26 POR_B supervisor SENSE input
1-2: VCCO_MIO ramp-up sense (1.8V)
2-3: VCCAUX_PMC ramp-up sense (1.5V)
1-2 23
3 J326 POR_B enable header
1-2: SYSCTLR can drive POR_B
3-4: PC4 can drive POR_B
5-6: FTDI can drive POR_B
Open: POR_B source not connected
1-2, 3-4 jumpered
5-6 open
23
4 J34 VCC Fuse programming enable
1-2: Fuse programming enabled
2-3: Fuse programming disabled
2-3 25
4 J37 JTAG source enable
1-2: JTAG sources disabled
2-3: JTAG sources enabled
2-3 35
5 J300 USB shield GND
1-2: USB connector DC grounded
2-3: USB connector no DC grounded
1-2 53
6 J301 SD REF
1-2: 3.3V REF
2-3: GND REF
1-2 51
7 J203 SYSCTLR POR_B supervisor enable
1-2: SYSCTLR POR_B supervisor enabled
Open: SYSCTLR POR_B supervisor disabled
1-2 97
8 J347 Fan type
1-2: System controller PWM
2-3: Versal ACAP MIO PWM
2-3 66
8 J348 TACH type
1-2: System controller TACH
2-3: Versal ACAP MIO TACH
2-3 66
9 J345 LPDMGTYAVTT enable select
Installed: Versal ACAP control
Not installed: enabled by UTIL_5V0_PGOOD
Open 90
10 J12 SYSMON VREF selection
Default VREF = 1.024V
1-2 20
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Switches
The following table lists the default switch sengs.
Table 4: Default Switch Settings
Callout
Number Ref. Des. Function Default Schematic Page
11 SW1 U1 mode 4-pole DIP switch
Switch OFF = 1 = high; ON = 0 = low
Mode = SW1[1:4] = Mode[0:3]
SD = ON,OFF,OFF,OFF = 0111
QSPI32 = ON,OFF,ON,ON = 0100
JTAG = ON,ON,ON,ON = 0000
ON, ON, ON, ON 22
12 SW2 VPK180 power-on reset (POR_B) Open 23
13 SW3 SYSCTLR JTAG source selection
Switch OFF = 1 = high; ON = 0 = low
SYSCTLR JTAG SOURCE SEL = SW3[1:2] = SEL[0:1]
PL JTAG = ON,ON = 00
FTDI JTAG = OFF,ON = 10
Trace Mictor38 JTAG = ON,OFF = 01
OFF, ON 35
14 SW4, SW5 User pushbutton inputs
Note: Pushbutton switch default = open = logic low
(not pressed).
Open 65
15 SW6 User GPIO DIP
Switch OFF = 0 = low; ON = 1 = high
OFF, OFF, OFF, OFF 65
16 SW11 SYSCTLR mode 4-pole DIP switch
Switch OFF = 1 = high; ON = 0 = low
Mode = SW1[1:4] = Mode[0:3]
QSPI32 = ON,OFF,ON,ON = 0100
eMMC = ON,OFF,OFF,ON = 0110
JTAG = ON,ON,ON,ON = 0000
ON, OFF, ON, ON 97
17 SW12 System controller power-on reset (SYSCTL_POR_B) Open 97
18 SW13 Main power OFF 66
19 SW14 User USB reset Open 53
20 SW15 User GEM reset Open 52
21 SW16 System controller FWUEN pushbutton
(SYSCTLR_MIO12_FWUEN_C2M_B)
See BEAM wiki for more information
Open 96
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