Amd Sr5650 Product guide

AMD SR5650 Databook

Technical Reference Manual

Rev 2.00

P/N: 47062_sr5650_ds_pub

Trademarks

AMD, the AMD Arrow logo, AMD PowerNow!, AMD Virtualization, AMD-V, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.

Microsoft, Windows, and Windows Server are registered trademarks of Microsoft Corporation.

PCI Express and PCIe are registered trademarks of PCI-SIG.

Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Disclaimer

The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with

respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time

without notice. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except as set

forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products

including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications

intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe

property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.

Proprietary Table of Contents-1

Table of Contents

Chapter 1: Overview

1.1 Introducing the SR5650 ......................................................................................................................................................1-1

1.2 SR5650 Features .................................................................................................................................................................1-1

1.2.1 CPU Interface .......................................................................................................................................................1-1

1.2.2 PCI Express® Interface ........................................................................................................................................1-1

1.2.3 A-Link Express II Interface..................................................................................................................................1-1

1.2.4 Multiple Processor Support ..................................................................................................................................1-2

1.2.5 Multiple Northbridge Support ..............................................................................................................................1-2

1.2.6 Power Management Features ...............................................................................................................................1-2

1.2.7 PC Design Guide Compliance..............................................................................................................................1-2

1.2.8 Test Capability Features .......................................................................................................................................1-2

1.2.9 Packaging .............................................................................................................................................................1-2

1.3 Software Features................................................................................................................................................................1-2

1.4 Device ID ............................................................................................................................................................................1-3

1.5 Branding Diagrams .............................................................................................................................................................1-3

1.6 Conventions and Notations .................................................................................................................................................1-4

1.6.1 Pin Names.............................................................................................................................................................1-4

1.6.2 Pin Types ..............................................................................................................................................................1-4

1.6.3 Numeric Representation .......................................................................................................................................1-4

1.6.4 Hyperlinks ............................................................................................................................................................1-4

1.6.5 Acronyms and Abbreviations ...............................................................................................................................1-4

Chapter 2: Functional Descriptions

2.1 HyperTransport™ Interface ................................................................................................................................................2-1

2.1.1 Overview ..............................................................................................................................................................2-1

2.1.2 HyperTransport™ Flow Control Buffers .............................................................................................................2-3

2.2 IOMMU ..............................................................................................................................................................................2-4

2.3 Multiple Northbridge Support.............................................................................................................................................2-4

2.4 Interrupt Handling...............................................................................................................................................................2-4

2.4.1 Legacy INTx Handling.........................................................................................................................................2-4

2.4.2 Non-SB IOAPIC Support .....................................................................................................................................2-4

2.4.3 Integrated IOAPIC Support..................................................................................................................................2-5

2.4.4 MSI Interrupt Handling and MSI to HT Interrupt Conversion ............................................................................2-5

2.4.5 Internally Generated Interrupts.............................................................................................................................2-5

2.4.6 IOMMU Interrupt Remapping .............................................................................................................................2-5

2.4.7 Interrupt Routing Architecture .............................................................................................................................2-5

2.5 RAS Features ......................................................................................................................................................................2-7

2.5.1 Parity Protection ...................................................................................................................................................2-7

2.5.2 SERR_FATAL# and NON_FATAL_CORR# Pins .............................................................................................2-7

2.5.3 NMI# and SYNCFLOODIN# ..............................................................................................................................2-8

2.5.4 Suggested Platform Level RAS Sideband Signal Connections............................................................................2-8

2.5.5 Error Reporting and Logging ...............................................................................................................................2-9

2.5.6 Interrupt Generation on Errors ........................................................................................................................... 2-11

2.5.7 Poisoned Data Support ....................................................................................................................................... 2-11

2.5.8 PCIe® Link Disable State .................................................................................................................................. 2-11

Table of Contents-2 Proprietary

2.5.9 HT Syncflood Based on PCIe® Error ............................................................................................................... 2-12

2.6 PCI Express® .................................................................................................................................................................. 2-12

2.6.1 PCIe® Ports ....................................................................................................................................................... 2-12

2.6.2 PCIe® Reset Signals.......................................................................................................................................... 2-12

2.7 External Clock Chip ......................................................................................................................................................... 2-12

Chapter 3: Pin Descriptions and Strap Options

3.1 Pin Assignment Top View ................................................................................................................................................. 3-2

3.2 SR5650 Interface Block Diagram ...................................................................................................................................... 3-4

3.3 CPU HyperTransport™ Interface ...................................................................................................................................... 3-4

3.4 PCI Express® Interfaces .................................................................................................................................................... 3-5

3.4.1 PCI Express® Interface for General Purpose External Devices ......................................................................... 3-5

3.4.2 A-Link Express II Interface to Southbridge ........................................................................................................ 3-5

3.4.3 Miscellaneous PCI Express® Signals ................................................................................................................. 3-6

3.5 Clock Interface ................................................................................................................................................................... 3-6

3.6 Power Management Pins.................................................................................................................................................... 3-6

3.7 Miscellaneous Pins ............................................................................................................................................................. 3-7

3.8 Power Pins.......................................................................................................................................................................... 3-7

3.9 Ground Pins........................................................................................................................................................................ 3-9

3.10 Strapping Options........................................................................................................................................................... 3-10

Chapter 4: Timing Specifications

4.1 HyperTransport™ Bus Timing .......................................................................................................................................... 4-1

4.2 PCI Express® Differential Clock AC Specifications......................................................................................................... 4-1

4.3 HyperTransport™ Reference Clock Timing Parameters ................................................................................................... 4-1

4.4 OSCIN Reference Clock Timing Parameters..................................................................................................................... 4-2

4.5 Power Rail Sequence.......................................................................................................................................................... 4-2

4.5.1 Power Up ............................................................................................................................................................. 4-3

4.5.2 Power Down ........................................................................................................................................................ 4-4

Chapter 5: Electrical Characteristics and Physical Data

5.1 Electrical Characteristics.................................................................................................................................................... 5-1

5.1.1 Maximum and Minimum Ratings........................................................................................................................ 5-1

5.1.2 DC Characteristics............................................................................................................................................... 5-1

5.2 SR5650 Thermal Characteristics........................................................................................................................................ 5-2

5.2.1 SR5650 Thermal Limits ...................................................................................................................................... 5-2

5.2.2 Thermal Diode Characteristics ............................................................................................................................ 5-3

5.3 Package Information .......................................................................................................................................................... 5-4

5.3.1 Pressure Specification.......................................................................................................................................... 5-5

5.3.2 Board Solder Reflow Process Recommendations ............................................................................................... 5-6

Chapter 6: Power Management and ACPI

6.1 ACPI Power Management Implementation ....................................................................................................................... 6-1

Chapter 7: Testability

7.1 Test Capability Features..................................................................................................................................................... 7-1

7.2 Test Interface...................................................................................................................................................................... 7-1

7.3 XOR Tree ........................................................................................................................................................................... 7-1

Proprietary Table of Contents-3

7.3.1 Brief Description of an XOR Tree .......................................................................................................................7-1

7.3.2 Description of the XOR Tree for the SR5650 ......................................................................................................7-2

7.3.3 XOR Tree Activation ...........................................................................................................................................7-2

7.3.4 XOR Tree for the SR5650....................................................................................................................................7-3

7.4 VOH/VOL Test...................................................................................................................................................................7-4

7.4.1 Brief Description of a VOH/VOL Tree................................................................................................................7-4

7.4.2 VOH/VOL Tree Activation ..................................................................................................................................7-5

7.4.3 VOH/VOL pin list ................................................................................................................................................7-6

Appendix A: Pin Listings

7.5 SR5650 Pin Listing Sorted by Ball Reference................................................................................................................... A-2

A.1 SR5650 Pin Listing Sorted by Pin Name .......................................................................................................................... A-9

Appendix B: Revision History

Table of Contents-4 Proprietary

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Proprietary List of Figures-1

List of Figures

Figure 1-1: SR5650 Branding Diagram for A21 Production ASIC (Eutectic Part) ....................................................................... 1-3

Figure 1-2: SR5650 Branding Diagram for A21 Production ASIC (Lead Free Part) .................................................................... 1-3

Figure 2-1: SR5650 Internal Blocks and Interfaces ....................................................................................................................... 2-1

Figure 2-2: HyperTransport™ Interface Block Diagram ............................................................................................................... 2-2

Figure 2-3: SR5650 HyperTransport™ Interface Signals .............................................................................................................. 2-3

Figure 2-4: Interrupt Routing Paths in Legacy Mode .................................................................................................................... 2-6

Figure 2-5: Interrupt Routing Paths in Legacy Mode with Integrated IOAPIC ............................................................................. 2-6

Figure 2-6: Interrupt Routing Path in MSI Mode .......................................................................................................................... 2-7

Figure 2-7: Suggested Platform Level RAS Sideband Signal Connections ................................................................................... 2-9

Figure 3-1: SR5650 Interface Block Diagram ............................................................................................................................... 3-4

Figure 4-1: SR5650 Power Rail Power Up Sequence .................................................................................................................... 4-3

Figure 5-2: SR5650 692-Pin FCBGA Package Outline ................................................................................................................. 5-4

Figure 5-3: SR5650 Ball Arrangement (Bottom View) ................................................................................................................. 5-5

Figure 5-4: RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile .............................................................. 5-7

Figure 7-1: XOR Tree .................................................................................................................................................................... 7-2

Figure 7-2: Sample of a Generic VOH/VOL Tree ......................................................................................................................... 7-5

List of Figures-2 Proprietary

This page is left blank intentionally.

Proprietary List of Tables-1

List of Tables

Table 1-1: Device IDs for the SR5690/5670/5650 Chipset Family ................................................................................................1-3

Table 1-2: Pin Type Codes ..............................................................................................................................................................1-4

Table 1-3: Acronyms and Abbreviations ........................................................................................................................................1-4

Table 2-1: SR5650 HyperTransport™ Flow Control Buffers .........................................................................................................2-3

Table 2-2: Types of Errors Detectable by the SR5650 AER Implementation ..............................................................................2-10

Table 2-3: Types of HyperTransport™ Errors Supported by the SR5650 ....................................................................................2-11

Table 2-4: Possible Configurations for the PCI Express® General Purpose Links ......................................................................2-12

Table 3-1: HyperTransport™ Interface ...........................................................................................................................................3-4

Table 3-2: PCI Express® Interface for General Purpose External Devices ....................................................................................3-5

Table 3-3: 1 x 4 Lane A-Link Express II Interface for Southbridge ...............................................................................................3-5

Table 3-4: Miscellaneous PCI Express® Signals ............................................................................................................................3-6

Table 3-5: Clock Interface ...............................................................................................................................................................3-6

Table 3-6: Power Management Pins ...............................................................................................................................................3-6

Table 3-7: Miscellaneous Pins ........................................................................................................................................................3-7

Table 3-8: Power Pins .....................................................................................................................................................................3-7

Table 3-9: Ground Pins ...................................................................................................................................................................3-9

Table 3-10: Strap Definitions for the SR5650 ..............................................................................................................................3-10

Table 3-11: Strap Definition for STRAP_PCIE_GPP_CFG .........................................................................................................3-10

Table 4-1: Timing Requirements for PCIe® Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz) ...............4-1

Table 4-2: Timing Requirements for HyperTransport™ Reference Clock (100MHz) ...................................................................4-1

Table 4-3: Timing Requirements for OSCIN Reference Clock (14.3181818MHz) .......................................................................4-2

Table 4-4: Power Rail Groupings for the SR5650 ..........................................................................................................................4-2

Table 4-5: SR5650 Power Rail Power-up Sequence .......................................................................................................................4-3

Table 5-1: Power Rail Maximum and Minimum Voltage Ratings .................................................................................................5-1

Table 5-2: Power Rail Current Ratings ...........................................................................................................................................5-1

Table 5-1: DC Characteristics for PCIe® Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz) ....................5-1

Table 5-3: DC Characteristics for 1.8V GPIO Pads ........................................................................................................................5-2

Table 5-4: DC Characteristics for the HyperTransport™ 100MHz Differential Clock (HT_REFCLK) .......................................5-2

Table 5-5: SR5650 Thermal Limits ................................................................................................................................................5-2

Table 5-6: SR5650 692-Pin FCBGA Package Physical Dimensions .............................................................................................5-4

Table 5-7: Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder ......................................................................5-6

Table 6-1: ACPI States Supported by the SR5650 .........................................................................................................................6-1

Table 7-1: Pins on the Test Interface ..............................................................................................................................................7-1

Table 7-2: Example of an XOR Tree ..............................................................................................................................................7-2

Table 7-3: SR5650 XOR Tree .........................................................................................................................................................7-3

Table 7-4: Truth Table for the VOH/VOL Tree Outputs ................................................................................................................7-5

Table 7-5: SR5650 VOH/VOL Tree ...............................................................................................................................................7-6