Analog Devices AD1887 User manual

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no res onsibility is assumed by Analog Devices for its
use, nor for any infringements of atents or other rights of third arties that
may result from its use. No license is granted by im lication or otherwise
under any atent or atent rights of Analog Devices.
a
AD1887
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U. .A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001
AC’97 SoundMAX
®
Codec
ENHANCED FEATURE
Full Duplex Variable ample Rates from 7040 Hz to
48 kHz with 1 Hz Resolution
oftware-Enabled VREFOUT Output for Microphones and
External Power Amp
plit Power upplies (3.3 V Digital/5 V Analog)
Mobile Low-Power Mixer Mode
Extended 6-Bit Headphone Volume Control
Digital Audio Mixer Mode
AC’97 2.1 FEATURE
Variable ample Rate Audio
AC’97 FEATURE
AC’97 2.2 Compliant
Greater than 90 dB Dynamic Range
Integrated tereo Headphone Amplifier
Multibit ⌺-⌬ Converter Architecture for Improved /N
Ratio Greater than 90 dB
16-Bit tereo Full-Duplex Codec
Two Analog Line-Level tereo Inputs for:
LINE-IN and CD
Mono MIC Input with Built-In Programmable Preamp
High-Quality CD Input with Ground ense
Power Management upport
48-Terminal TQFP Package
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
SELECTOR
XTL_OUT XTL_IN
VREF
SAMPLE
RATE
GENERATORS
SELECTOR
PGA
PGA
16-BIT
⌺-⌬A/D
CONVERTER
16-BIT
⌺-⌬A/D
CONVERTER
16-BIT
⌺-⌬A/D
CONVERTER
GA
M
MIC
PREAMP
M
GA
M
GA
M
GA
M
GA
M
GA
GA
M
16-BIT
⌺-⌬A/D
CONVERTER
M
M
GA
M
HP
GA
M
HP
CHIP SELECT
AD1887
SDATA_IN
SDATA_OUT
BIT_CLK
SYNC
RESET
VREFOUT
ID0 ID1
MIC
LINE_IN
CD
HP_OUT_L
HP_OUT_R
G = GAIN
A = ATTENUATE
M = MUTE
AC
LINK
SoundMAX is a registered trademark of Analog Devices, Inc.

REV. 0
–2–
AD1887–SPECIFICATIONS
ANALOG INPUT
Parameter Min Typ Max Unit
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, CD 1Vrms
2.83 V p-p
MIC with 20 dB Gain 0.1 V rms
0.283 V p-p
MIC with 0 dB Gain 1Vrms
2.83 V p-p
Input Impedance
* 20 kΩ
Input Capacitance * 5 7.5 pF
HEADPHONE OUT VOLUME
Parameter Min Typ Max Unit
Step Size (+6 dB to –88.5 dB); HP_OUT_R, HP_OUT_L 1.5 dB
Output Attenuation Range Span * –94.5 dB
Mute Attenuation of 0 dB Fundamental * 80 dB
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter Min Typ Max Unit
Step Size (0 dB to 22.5 dB) 1.5 dB
PGA Gain Range Span 22.5 dB
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Parameter Min Typ Max Unit
Signal-to-Noise Ratio (SNR)
CD to HP_OUT 90 dB
Other to HP_OUT 90 dB
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
MIC, LINE_IN, CD, DAC 1.5 dB
Input Gain/Attenuation Range:
MIC, LINE_IN, CD, DAC –46.5 dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter Min Typ Max Unit
Pass Band 0 0.4 ×
f
S
Hz
Pass-Band Ripple ±0.09 dB
Transition Band 0.4 ×
f
S
0.6 × f
S
Hz
Stop Band 0.6 ×
f
S
∞Hz
Stop-Band Rejection –74 dB
Group Delay 12/
f
S
sec
Group Delay Variation over Pass Band 0.0 µs
*Guaranteed but not tested.
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature 25°C
Digital Supply (V
DD
) 3.3 V
Analog Supply (V
CC
) 5.0 V
Sample Rate (
f
S
) 48 kHz
Input Signal 1008 Hz
Analog Output Pass Band 20 Hz to 20 kHz
V
IH
2.0 V
V
IL
0.8 V
V
IH
(CS0, CS1) 4.0 V
V
IL
1.0 V
DAC Test Conditions
Calibrated
–3 dB Attenuation Relative to Full Scale
Input 0 dB
32 ΩOutput Load (HP_OUT)
ADC Test Conditions
Calibrated
0 dB Gain
Input –3.0 dB Relative to Full Scale

REV. 0
AD1887
–3–
ANALOG-TO-DIGITAL CONVERTERS
Parameter Min Typ Max Unit
Resolution 16 Bits
Total Harmonic Distortion (THD) –84 dB
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted) 84 87 dB
Signal-to-Intermodulation Distortion
* (CCIF Method) 85 dB
ADC Crosstalk
*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –100 –90 dB
LINE_IN to Other –90 –85 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB
ADC Offset Error ±5mV
DIGITAL-TO-ANALOG CONVERTERS
Parameter Min Typ Max Unit
Resolution 16 Bits
Total Harmonic Distortion (THD) HP_OUT –75 dB
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted) 85 90 dB
Signal-to-Intermodulation Distortion
* (CCIF Method) –100 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.7 dB
DAC Crosstalk
* (Input L, Zero R, Measure R_OUT; Input R, Zero L, –80 dB
Measure L_OUT)
Total Audible Out-of-Band Energy (Measured from 0.6 × f
S
to 20 kHz) * –40 dB
ANALOG OUTPUT
Parameter Min Typ Max Unit
Full-Scale Output Voltage; HP_OUT 1 V rms
2.83 V p-p
Output Impedance
* 800 Ω
External Load Impedance
* 32 Ω
Output Capacitance
* 15 pF
External Load Capacitance 100 pF
V
REF
2.05 2.25 2.45 V
V
REF_OUT
2.25 V
V
REF_OUT
Current Drive 5mA
Mute Click (Muted Output Minus Unmuted Midscale DAC Output) ±5mV
STATIC DIGITAL SPECIFICATIONS
Parameter Min Typ Max Unit
High-Level Input Voltage (V
IH
): Digital Inputs 0.65 ×DV
DD
V
Low-Level Input Voltage (V
IL
)0.35 ×DV
DD
V
High-Level Output Voltage (V
OH
), I
OH
= 2 mA 0.9 ×DV
DD
V
Low-Level Output Voltage (V
OL
), I
OL
= 2 mA 0.1 ×DV
DD
V
Input Leakage Current –10 +10 µA
Output Leakage Current –10 +10 µA
POWER SUPPLY
Parameter Min Typ Max Unit
Power Supply Range—Analog (AV
DD
) 4.75 5.25 V
Power Supply Range—Digital (DV
DD
) 3.15 3.45 V
Power Dissipation—5 V/3.3 V 253 mW
Analog Supply Current—5 V (AV
DD
)36mA
Digital Supply Current—3.3 V (DV
DD
)22mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)
* 40 dB
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
*Guaranteed but not tested.

REV. 0
–4–
AD1887–SPECIFICATIONS
CLOCK SPECIFICATIONS*
Parameter Min Typ Max Unit
Input Clock Frequency 24.576 MHz
Recommended Clock Duty Cycle 40 50 60 %
POWER-DOWN STATES
Parameter Set Bits DV
DD
Typ AV
DD
Typ Unit
ADC PR0 15.82 30.0 mA
DAC PR1 15.08 26.3 mA
ADC + DAC PR1, PR0 3.79 19.9 mA
ADC + DAC + Mixer (Analog CD On) LPMIX, PR1, PR0 3.85 18.1 mA
Mixer PR2 17.65 17.4 mA
ADC + Mixer PR2, PR0 15.70 11.1 mA
DAC + Mixer PR2, PR1 15.07 8.3 mA
ADC + DAC + Mixer PR2, PR1, PR0 3.80 2.1 mA
Analog CD Only (AC-Link On) LPMIX, PR5, PR1, PR0 3.85 18.1 mA
Analog CD Only (AC-Link Off) LPMIX, PR1, PR0, PR4, PR5 0.06 18.1 mA
Standby PR5, PR4, PR3, PR2, PR1, PR0 0.06 0 mA
Headphone Standby PR6 17.66 26.1 mA
*Guaranteed but not tested.
Specifications subject to change without notice.
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter Symbol Min Typ Max Unit
RESET Active Low Pulsewidth t
RST_LOW
1.0 µs
RESET Inactive to BIT_CLK Startup Delay t
RST2CLK
162.8 ns
SYNC Active High Pulsewidth t
SYNC_HIGH
1.3 µs
SYNC Low Pulsewidth t
SYNC_LOW
19.5 µs
SYNC Inactive to BIT_CLK Startup Delay t
SYNC2CLK
162.8 ns
BIT_CLK Frequency 12.288 MHz
BIT_CLK Period t
CLK_PERIOD
81.4 ns
BIT_CLK Output Jitter*750 ps
BIT_CLK High Pulsewidth t
CLK_HIGH
32.56 42 48.84 ns
BIT_CLK Low Pulsewidth t
CLK_LOW
32.56 38 48.84 ns
SYNC Frequency 48.0 kHz
SYNC Period t
SYNC_PERIOD
20.8 µs
Setup to Falling Edge of BIT_CLK t
SETUP
5 2.5 ns
Hold from Falling Edge of BIT_CLK t
HOLD
5ns
BIT_CLK Rise Time t
RISECLK
246 ns
BIT_CLK Fall Time t
FALLCLK
246 ns
SYNC Rise Time t
RISESYNC
246 ns
SYNC Fall Time t
FALLSYNC
246 ns
SDATA_IN Rise Time t
RISEDIN
246 ns
SDATA_IN Fall Time t
FALLDIN
246 ns
SDATA_OUT Rise Time t
RISEDOUT
246 ns
SDATA_OUT Fall Time t
FALLDOUT
246 ns
End of Slot 2 to BIT_CLK, SDATA_IN Low t
S2_PDOWN
0 1.0 µs
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) t
SETUP2RST
15 ns
Rising Edge of RESET to HI-Z Delay t
OFF
25 ns
Propagation Delay 15 ns
RESET Rise Time 50 ns
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 15 ns
*Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.

REV. 0
AD1887
–5–
RESET
BIT_CLK
tRST2CLK
tRST_LOW
Figure 1. Cold Reset
SYNC
BIT_CLK
tSYNC_HIGH tRST2CLK
Figure 2. Warm Reset
t
CLK_HIGH
BIT_CLK
t
CLK_LOW
SYNC
t
SYNC_HIGH
tSYNC_LOW
t
SYNC_PERIOD
t
CLK_PERIOD
Figure 3. Clock Timing
BIT_CLK
SYNC
tHOLD
SDATA_OUT
tSETUP
Figure 4. Data Setu and Hold
BIT_CLK
SYNC
SDATA_IN
t
RISECLK
t
RISESYNC
t
RISEDIN
t
RISEDOUT
t
FALLCLK
t
FALLSYNC
t
FALLDIN
t
FALLDOUT
SDATA_OUT
Figure 5. Signal Rise and Fall Time
BIT_CLK
SDATA_OUT
SYNC
SDATA_IN
SLOT 1 SLOT 2
WRITE
TO 0x26
DATA
PR4
DON’T
CARE
t
S2_PDOWN
NOTE: BIT_CLK NOT TO SCALE
Figure 6. AC Link Low Power Mode Timing
RESET
SDATA_OUT
HI-Z
tSETUP2RST
tOFF
SDATA_IN, BIT_CLK
Figure 7. ATE Test Mode

REV. 0
AD1887
–6–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1887 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
Parameter Min Max Unit
Power Supplies
Digital (DV
DD
) –0.3 +3.6 V
Analog (AV
CC
) –0.3 +6.0 V
Input Current (Except Supply Pins) ±10.0 mA
Analog Input Voltage (Signal Pins) –0.3 AV
DD
+ 0.3 V
Digital Input Voltage (Signal Pins) –0.3 DV
DD
+ 0.3 V
Ambient Temperature (Operating) 0 70 °C
Storage Temperature –65 +150 °C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD1887JST 0°C to 70°C Thin-Quad Flatpack ST-48
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
T
AMB
= T
CASE
– (P
D
×θ
CA
)
T
CASE
= Case Temperature in °C
P
D
= Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Package ␪
JA
␪
JC
␪
CA
TQFP 76.2°C/W 17°C/W 59.2°C/W
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC
NC
NC
NC
FILT_L
FILT_R
AFILT2
DV
DD1
XTL_IN
XTL_OUT
DV
SS1
SDATA_OUT
BIT_CLK
DV
SS2
NC = NO CONNECT
SDATA_IN
DV
DD2
SYNC
RESET
AFILT1
V
REFOUT
V
REF
AV
SS1
AD1887
NC AV
DD1
NC NC ID1 ID0 AV
SS3
AV
DD3
NC HP_OUT_R AV
SS2
HP_OUT_L AV
DD2
NC
NC NC NC NC NC
CD_L
CD_GND_REF
CD_R
MIC_IN
NC
LINE_IN_L
LINE_IN_R

REV. 0
AD1887
–7–
PIN FUNCTION DESCRIPTIONS
Digital I/O
Pin Name TQFP I/O Description
XTL_IN 2 I Crystal (or Clock) Input, 24.576 MHz
XTL_OUT 3 O Crystal Output
SDATA_OUT 5 I AC-Link Serial Data Output, AD1887 Input Stream
BIT_CLK 6 O/I AC-Link Bit Clock 12288 MHz Serial Data Clock Daisy Chain Output Clock
SDATA_IN 8 O AC-Link Serial Data Input AD1887 Output Stream
SYNC 10 I AC-Link Frame Sync
RESET 11 I AC-Link Reset AD1887 Master H/W Reset
Chip Selects
Pin Name TQFP Type Description
ID0 45 I Chip Select Input 0 (Active Low)
ID1 46 I Chip Select Input 1 (Active Low)
Analog I/O
These signals connect the AD1887 component to analog sources and sinks, including microphones and speakers
Pin Name TQFP I/O Description
CD_L 18 I CD Audio Left Channel
CD_GND_REF 19 I CD Audio Analog Ground Reference for Differential CD Input
CD_ R 20 I CD Audio Right Channel
MIC 21 I Microphone Input
LINE_IN_L 23 I Line in Left Channel
LINE_IN_R 24 I Line in Right Channel
HP_OUT_L 39 O Headphones Out Left Channel
HP_OUT_R 41 O Headphones Out Right Channel
Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages
Pin Name TQFP I/O Description
V
REF
27 O Voltage Reference Filter
V
REFOUT
28 O Voltage Reference Output 5 mA Drive (Intended for Mic Bias)
AFILT1 29 O Antialiasing Filter Capacitor—ADC Right Channel
AFLIT2 30 O Antialiasing Filter Capacitor—ADC Left Channel
FILT_R 31 O AC-Coupling Filter Capacitor—ADC Right Channel
FILT_L 32 O AC-Coupling Filter Capacitor—ADC Left Channel
Power and Ground Signals
Pin Name TQFP Type Description
DV
DD
1 1 I Digital V
DD
33 V
DV
SS
1 4 I Digital GND
DV
SS
2 7 I Digital GND
DV
DD
2 9 I Digital V
DD
33 V
AV
DD
1 25 I Analog V
DD
50 V
AV
SS
1 26 I Analog GND
AV
DD
2 38 I Analog V
DD
50 V
AV
SS
2 40 I Analog GND
AV
DD
3 43 I Analog V
DD
50 V
AV
SS
3 44 I Analog GND

REV. 0
AD1887
–8–
No Connects
Pin Name TQFP Type Description
NC 12 No Connect
NC 13 No Connect
NC 14 No Connect
NC 15 No Connect
NC 16 No Connect
NC 17 No Connect
NC 22 No Connect
NC 33 No Connect
NC 34 No Connect
NC 35 No Connect
NC 36 No Connect
NC 37 No Connect
NC 42 No Connect
NC 47 No Connect
NC 48 No Connect
Indexed Control Registers
Reg
Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0010h
04h Headphones Volume HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 X X RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
08h Reserved X X X X XXXX XXXX X X XX X
00Eh Mic Volume MCM X X X XXXX XM30XMCV4MCV3MCV2 MCV1 MCV0 8008h
10h Line-In Volume LM X X LLV4 LLV3 LLV2 LLV1 LLV0 X X X RLV4 RLV3 RLV2 RLV1 RLV0 8808h
12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 X X X RCV4 RCV3 RCV2 RCV1 RCV0 8808h
18h PCM Out Vol OM X X LOV4 LOV3 LOV2 LOV1 LOV0 X X X ROV4 ROV3 ROV2 ROV1 ROV0 8808h
1Ah Record Select X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h
1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 X X X X RIM3 RIM2 RIM1 RIM0 8000h
20h General-Purpose X X X X XXXX LPBK X X X X X X X 0000h
26h Power-Down Ctrl/Stat X X PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh
28h Ext’d Audio ID ID1 ID0 X X XXXX XXXX X X XVRA0005h
2Ah Ext’d Audio Stat/Ctrl X X X X XXXX XXXX X X XVRA0000h
2Ch/ PCM DAC Rate (SR1) SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
(7Ah)*
32h/ PCM ADC Rate (SR0) SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
(78h)*
74h Serial Configuration SLOT16 REGM2 REGM1 REGM0 XXXX XXXX X X XX 7000h
76h Misc Control Bits DACZ LPMIX X DAM DMS DLSR X ALSR MOD SRX10 SRX8 X X DRSR X ARSR 0404h
EN D7 D7
7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h
7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5362h
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*Indicates Aliased register for AD1819, AD1819A backward compatibility.

REV. 0
AD1887
–9–
Reset (Index 00h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h00h00 h00 h00h00teseRteseR teseR teseRteseRXX
X
XX4ES4ES 4ES 4ES4ES3ES3ES 3ES 3ES3ES2ES2ES 2ES 2ES2ES1ES1ES 1ES 1ES1ES0ES0ES 0ES 0ES0ES9DI9DI 9DI 9DI9DI8DI8DI 8DI 8DI8DI7DI7DI 7DI 7DI7DI6DI6DI 6DI 6DI6DI5DI5DI 5DI 5DI5DI4DI4DI 4DI 4DI4DI3DI3DI 3DI 3DI3DI2DI2DI 2DI 2DI2DI1DI1DI 1DI 1DI1DI0DI0DI 0DI 0DI0DIh0100h0100 h0100 h0100h0100
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1887 based on the following:
Bit = 1 Function AD1887 *
ID0 Dedicated Mic PCM in Channel 0
ID1 Modem Line Codec Support 0
ID2 Bass and Treble Control 0
ID3 Simulated Stereo (Mono to Stereo) 0
ID4 Headphone Out Support 1
ID5 Loudness (Bass Boost) Support 0
ID6 18-Bit DAC Resolution 0
ID7 20-Bit DAC Resolution 0
ID8 18-Bit ADC Resolution 0
ID9 20-Bit ADC Resolution 0
*The AD1887 contains none of the optional features identified by these bits.
SE[4:0] Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Headphones Volume Registers (Index 04h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h40h40 h40 h40h40 senohpdaeHsenohpdaeH senohpdaeH senohpdaeHsenohpdaeH
emuloVemuloV emuloV emuloVemuloV MPHMPH MPH MPHMPHXX
X
XX5VHL5VHL 5VHL 5VHL5VHL4VHL4VHL 4VHL 4VHL4VHL3VHL3VHL 3VHL 3VHL3VHL2VHL2VHL 2VHL 2VHL2VHL1VHL1VHL 1VHL 1VHL1VHL0VHL0VHL 0VHL 0VHL0VHLXX
X
XXXX
X
XX5VHR5VHR 5VHR 5VHR5VHR4VHR4VHR 4VHR 4VHR4VHR3VHR3VHR 3VHR 3VHR3VHR2VHR2VHR 2VHR 2VHR2VHR1VHR1VHR 1VHR 1VHR1VHR0VHR0VHR 0VHR 0VHR0VHRh0008h0008 h0008 h0008h0008
RHV[5:0] Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from +6 dB to a maximum attenuation of –88.5 dB.
LHV[5:0] Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from +6 dB to a maximum attenuation of –88.5 dB.
HPM Headphones Volume Mute. When this bit is set to “1,” the channel is muted.
HPM xHV5 . . . xHV0 Function
0 00 0000 6 dB Gain
0 01 1111 –40.5 dB Attenuation
0 11 1111 –88.5 dB Attenuation
1 xx xxxx –∞dB Attenuation

REV. 0
AD1887
–10–
Mic Volume (Index 0Eh)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hE0hE0 hE0 hE0hE0 CIMCIM CIM CIMCIM
emuloVemuloV emuloV emuloVemuloV MCMMCM MCM MCMMCMXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XX03M03M 03M 03M03MXX
X
XX4VCM4VCM 4VCM 4VCM4VCM3VCM3VCM 3VCM 3VCM3VCM2VCM2VCM 2VCM 2VCM2VCM1VCM1VCM 1VCM 1VCM1VCM0VCM0VCM 0VCM 0VCM0VCMh8008h8008 h8008 h8008h8008
MCV[4:0] Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M30 Mic Boost Gain: Amplifies the Mic input. 0 = 0 dB, 1 = 30 dB
MCM Mic Mute. When this bit is set to “1,” the channel is muted.
Line In Volume (Index 10h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D 9D9D8D8D8D 8D8D7D7D7D 7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h01h01 h01 h01h01 nIeniLnIeniL nIeniL nIeniLnIeniL
emuloVemuloV emuloV emuloVemuloV MLMLMLMLMLXX
X
XXXX
X
XX4VLL4VLL 4VLL 4VLL4VLL3VLL3VLL 3VLL 3VLL3VLL2VLL2VLL 2VLL 2VLL2VLL1VLL1VLL 1VLL 1VLL1VLL0VLL0VLL 0VLL 0VLL0VLLXX
X
XXXX
X
XXXX
X
XX4VLR4VLR 4VLR 4VLR4VLR3VLR3VLR 3VLR 3VLR3VLR2VLR2VLR 2VLR 2VLR2VLR1VLR1VLR 1VLR 1VLR1VLR0VLR0VLR 0VLR 0VLR0VLRh8088h8088 h8088 h8088h8088
RLV[4:0] Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LLV[4:0] Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LM Line In Mute. When this bit is set to “1,” the channel is muted.
CD Volume (Index 12h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D 3D3D2D2D2D 2D2D1D1D1D 1D1D0D0D0D 0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h21h21 h21 h21h21 DCDCDCDCDC
emuloVemuloV emuloV emuloVemuloV MVCMVC MVC MVCMVCXX
X
XXXX
X
XX4VCL4VCL 4VCL 4VCL4VCL3VCL3VCL 3VCL 3VCL3VCL2VCL2VCL 2VCL 2VCL2VCL1VCL1VCL 1VCL 1VCL1VCL0VCL0VCL 0VCL 0VCL0VCLXX
X
XXXX
X
XXXX
X
XX4VCR4VCR 4VCR 4VCR4VCR3VCR3VCR 3VCR 3VCR3VCR2VCR2VCR 2VCR 2VCR2VCR1VCR1VCR 1VCR 1VCR1VCR0VCR0VCR 0VCR 0VCR0VCRh8088h8088 h8088 h8088h8088
RCV[4:0] Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LCV[4:0] Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CVM CD Volume Mute. When this bit is set to “1,” the channel is muted.

REV. 0
AD1887
–11–
PCM Out Volume (Index 18h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D 9D9D8D8D8D 8D8D7D7D7D7D7D6D6D6D 6D6D5D5D5D 5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D 2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h81h81 h81 h81h81 tuOMCPtuOMCP tuOMCP tuOMCPtuOMCP
emuloVemuloV emuloV emuloVemuloV MOMOMOMOMOXX
X
XXXX
X
XX4VOL4VOL 4VOL 4VOL4VOL3VOL3VOL 3VOL 3VOL3VOL2VOL2VOL 2VOL 2VOL2VOL1VOL1VOL 1VOL 1VOL1VOL0VOL0VOL 0VOL 0VOL0VOLXX
X
XXXX
X
XXXX
X
XX4VOR4VOR 4VOR 4VOR4VOR3VOR3VOR 3VOR 3VOR3VOR2VOR2VOR 2VOR 2VOR2VOR1VOR1VOR 1VOR 1VOR1VOR0VOR0VOR 0VOR 0VOR0VORh8088h8088 h8088 h8088h8088
ROV[4:0] Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LOV[4:0] Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OM PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.
Volume Table (Index 0Ch to 18h)
Mute x4 . . . x0 Function
0 00000 +12 dB Gain
0 01000 0 dB Gain
0 11111 –34.5 dB Gain
1 xxxxx –∞dB Gain
Record Select Control Register (Index 1Ah)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hA1hA1 hA1 hA1hA1tceleSdroceRtceleSdroceR tceleSdroceR tceleSdroceRtceleSdroceRXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XX2SL2SL 2SL 2SL2SL1SL1SL 1SL 1SL1SL0SL0SL 0SL 0SL0SLXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XX2SR2SR 2SR 2SR2SR1SR1SR 1SR 1SR1SR0SR0SR 0SR 0SR0SRh0000h0000 h0000 h0000h0000
RS[2:0] Right Record Select
LS[2:0] Left Record Select
Used to select the record source independently for right and left. See table for legend.
The default value is 0000h, which corresponds to Mic in.
Record Gain (Index 1Ch)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D 5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hC1hC1 hC1 hC1hC1niaGdroceRniaGdroceR niaGdroceR niaGdroceRniaGdroceRMIMIMIMIMIXX
X
XXXX
X
XXXX
X
XX3MIL3MIL 3MIL 3MIL3MIL2MIL2MIL 2MIL 2MIL2MIL1MIL1MIL 1MIL 1MIL1MIL0MIL0MIL 0MIL 0MIL0MILXX
X
XXXX
X
XXXX
X
XXXX
X
XX3MIR3MIR 3MIR 3MIR3MIR2MIR2MIR 2MIR 2MIR2MIR1MIR1MIR 1MIR 1MIR1MIR0MIR0MIR 0MIR 0MIR0MIRh0008h0008 h0008 h0008h0008
RIM[3:0] Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB.
LIM[3:0] Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB.
IM Input Mute
0 = Unmuted
1 = Muted or –∞dB Gain
IM xIM3 . . . xIM0 Function
0 1111 22.5 dB Gain
0 0000 0 dB Gain
1 xxxxx –∞dB Gain
RS2 . . . RS0 Right Record Source
0 MIC
1 CD_L
4 LINE_IN_R
5 Stereo Mix (R)
6 Mono Mix
LS2 . . . LS0 Left Record Source
0 MIC
1 CD_L
4 LINE_IN_L
5 Stereo Mix (L)
6 Mono Mix

REV. 0
AD1887
–12–
General Purpose Register (Index 20h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D 8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D 4D4D3D3D3D3D3D2D2D2D 2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h02h02 h02 h02h02esopruPlareneGesopruPlareneG esopruPlareneG esopruPlareneGesopruPlareneGXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXKBPLKBPL KBPL KBPLKBPLXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXh0000h0000 h0000 h0000h0000
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default
value is 0000h, which is all off.
LPBK Loopback Control. ADC/DAC digital loopback mode.
Subsection Ready Register (Index 26h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h62h62 h62 h62h62tatS/lrtnCnwoD-rewoPtatS/lrtnCnwoD-rewoP tatS/lrtnCnwoD-rewoP tatS/lrtnCnwoD-rewoPtatS/lrtnCnwoD-rewoPXX
X
XX6RP6RP 6RP 6RP6RP5RP5RP 5RP 5RP5RP4RP4RP 4RP 4RP4RP3RP3RP 3RP 3RP3RP2RP2RP 2RP 2RP2RP1RP1RP 1RP 1RP1RP0RP0RP 0RP 0RP0RPXX
X
XXXX
X
XXXX
X
XXXX
X
XXFERFER FER FERFERLNALNA LNA LNALNACADCAD CAD CADCADCDACDA CDA CDACDAANANANANAN
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the
AD1887 subsections. If the bit is a one, that subsection is “ready.” Ready is defined as the subsection able to perform in its nomi-
nal state.
ADC ADC section ready to transmit data.
DAC DAC section ready to accept data.
ANL Analog gainuators, attenuators, and mixers ready.
REF Voltage References, V
REF
and V
REFOUT
up to nominal level.
PR[5:0] AD1887 Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be
powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until
the reference is up.
PR0 – Powered-Down ADC
PR1 – Powered-Down DAC
PR2 – Powered-Down Analog Mixer
PR3 – Powered-Down V
REF
and V
REFOUT
PR4 – Powered-Down AC-Link
PR5 – Powered-Down Internal Clock
PR6 – Powered-Down Headphone
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can
be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are
both set.
In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in
the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect or disable PR5.
Power-Down State PR6 PR5 PR4 PR3 PR2 PR1 PR0
ADC Power-Down 0000001
DACs Power-Down 0000010
ADC and DAC Power-Down 0000011
Mixer Power-Down 0000100
ADC + Mixer Power-Down 0000101
DAC + Mixer Power-Down 0000110
ADC + DAC + Mixer Power-Down 0000111
Standby 1111111

REV. 0
AD1887
–13–
Extended Audio ID Register (Index 28h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h82h82 h82 h82h82DIoiduAdednetxEDIoiduAdednetxE DIoiduAdednetxE DIoiduAdednetxEDIoiduAdednetxE1DI1DI 1DI 1DI1DI0DI0DI 0DI 0DI0DIXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXARVARV ARV ARVARVh1000h1000 h1000 h1000h1000
Note: The Extended Audio ID is a read only register.
VRA Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio.
ID[1:0] ID1, ID0 is a 2-bit field which indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
Extended Audio Status and Control Register (Index 2Ah)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hA2hA2 hA2 hA2hA2lrtC/tatSoiduAd'txElrtC/tatSoiduAd'txE lrtC/tatSoiduAd'txE lrtC/tatSoiduAd'txElrtC/tatSoiduAd'txEXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXARVARV ARV ARVARVh0000h0000 h0000 h0000h0000
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio mode (sample rate control registers and
SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D 4D4D3D3D3D3D3D2D2D2D 2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
)hA7(/hC2)hA7(/hC2 )hA7(/hC2 )hA7(/hC2)hA7(/hC2etaRCADMCPetaRCADMCP etaRCADMCP etaRCADMCPetaRCADMCP51RS51RS 51RS 51RS51RS41RS41RS 41RS 41RS41RS31RS31RS 31RS 31RS31RS21RS21RS 21RS 21RS21RS11RS11RS 11RS 11RS11RS01RS01RS 01RS 01RS01RS9RS9RS 9RS 9RS9RS8RS8RS 8RS 8RS8RS7RS7RS 7RS 7RS7RS6RS6RS 6RS 6RS6RS5RS5RS 5RS 5RS5RS4RS4RS 4RS 4RS4RS3RS3RS 3RS 3RS3RS2RS2RS 2RS 2RS2RS1RS1RS 1RS 1RS1RS0RS0RS 0RS 0RS0RSh08BBh08BB h08BB h08BBh08BB
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0] Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when
read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
)h87(/h23)h87(/h23 )h87(/h23 )h87(/h23)h87(/h23etaRCDAMCPetaRCDAMCP etaRCDAMCP etaRCDAMCPetaRCDAMCP51RS51RS 51RS 51RS51RS41RS41RS 41RS 41RS41RS31RS31RS 31RS 31RS31RS21RS21RS 21RS 21RS21RS11RS11RS 11RS 11RS11RS01RS01RS 01RS 01RS01RS9RS9RS 9RS 9RS9RS8RS8RS 8RS 8RS8RS7RS7RS 7RS 7RS7RS6RS6RS 6RS 6RS6RS5RS5RS 5RS 5RS5RS4RS4RS 4RS 4RS4RS3RS3RS 3RS 3RS3RS2RS2RS 2RS 2RS2RS1RS1RS 1RS 1RS1RS0RS0RS 0RS 0RS0RSh08BBh08BB h08BB h08BBh08BB
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0] Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when
read, otherwise the closest rate supported is returned.

REV. 0
AD1887
–14–
Serial Configuration (Index 74h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h47h47 h47 h47h47 laireSlaireS laireS laireSlaireS
noitarugifnoCnoitarugifnoC noitarugifnoC noitarugifnoCnoitarugifnoC 61TOLS61TOLS 61TOLS 61TOLS61TOLS2MGER2MGER 2MGER 2MGER2MGER1MGER1MGER 1MGER 1MGER1MGER0MGER0MGER 0MGER 0MGER0MGERXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXXX
X
XXh0007h0007 h0007 h0007h0007
Note: This register is not reset when the reset register (Register 00h) is written.
DHWR Disable Hardware Reset.
REGM0 Master Codec Register Mask.
REGM1 Slave 1 Codec Register Mask.
REGM2 Slave 2 Codec Register Mask.
SLOT16 Enable 16-bit slots.
If your system uses only a single AD1887, you can ignore the register mask bits.
SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
geRgeR geR geRgeR
muNmuN muN muNmuN
emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h67h67 h67 h67h67csiMcsiM csiM csiMcsiM
lortnoClortnoC lortnoC lortnoClortnoC
stiBstiB stiB stiBstiB
ZCADZCAD ZCAD ZCADZCADXIMPLXIMPL XIMPL XIMPLXIMPLXX
X
XXMADMAD MAD MADMADSMDSMD SMD SMDSMDRSLDRSLD RSLD RSLDRSLDXX
X
XXRSLARSLA RSLA RSLARSLADOMDOM DOM DOMDOM
NENENENENE
01XRS01XRS 01XRS 01XRS01XRS
7D7D7D7D7D
8XRS8XRS 8XRS 8XRS8XRS
7D7D7D7D7D
XX
X
XXXX
X
XXRSRDRSRD RSRD RSRDRSRDXX
X
XXRSRARSRA RSRA RSRARSRAh4040h4040 h4040 h4040h4040
ARSR ADC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DRSR DAC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
SRX8D7 Multiply SR1 rate by 8/7.
SRX10D7 Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.
MODEN Modem filter enable (left channel only). Change only when DACs are powered down.
ALSR ADC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DLSR DAC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DMS Digital Mono Select
0 = Mixer
1 = Left DAC + Right DAC
DAM Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.
LPMIX Low-Power Mixer
DACZ Zero-fill (vs. repeat) if DAC is starved for data.

REV. 0
AD1887
–15–
Sample Rate 0 (Index 78h)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
h87/)h23(h87/)h23( h87/)h23( h87/)h23(h87/)h23( elpmaSelpmaS elpmaS elpmaSelpmaS
0etaR0etaR 0etaR 0etaR0etaR 510RS510RS 510RS 510RS510RS410RS410RS 410RS 410RS410RS310RS310RS 310RS 310RS310RS210RS210RS 210RS 210RS210RS110RS110RS 110RS 110RS110RS010RS010RS 010RS 010RS010RS90RS90RS 90RS 90RS90RS80RS80RS 80RS 80RS80RS70RS70RS 70RS 70RS70RS60RS60RS 60RS 60RS60RS50RS50RS 50RS 50RS50RS40RS40RS 40RS 40RS40RS30RS20RS20RS 20RS 20RS20RS10RS10RS 10RS 10RS10RS00RS00RS 00RS 00RS00RSh08BBh08BB h08BB h08BBh08BB
Note: 32h is an alias for 78h. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR0[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hA7/)hC2(hA7/)hC2( hA7/)hC2( hA7/)hC2(hA7/)hC2( elpmaSelpmaS elpmaS elpmaSelpmaS
1etaR1etaR 1etaR 1etaR1etaR 511RS511RS 511RS 511RS511RS411RS411RS 411RS 411RS411RS311RS311RS 311RS 311RS311RS211RS211RS 211RS 211RS211RS111RS111RS 111RS 111RS111RS011RS011RS 011RS 011RS011RS91RS91RS 91RS 91RS91RS81RS81RS 81RS 81RS81RS71RS71RS 71RS 71RS71RS61RS61RS 61RS 61RS61RS51RS51RS 51RS 51RS51RS41RS41RS 41RS 41RS41RS31RS21RS21RS 21RS 21RS21RS11RS11RS 11RS 11RS11RS01RS01RS 01RS 01RS01RSh08BBh08BB h08BB h08BBh08BB
Note: 2Ch is an alias for 7Ah. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR1[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID Registers (Index 7Ch–7Eh)
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hC7hC7 hC7 hC7hC71DIrodneV1DIrodneV 1DIrodneV 1DIrodneV1DIrodneV7F7F7F7F7F6F6F6F6F6F5F5F5F5F5F4F4F4F4F4F3F3F3F3F3F2F2F2F2F2F1F1F1F1F1F0F0F0F0F0F7S7S7S7S7S6S6S6S6S6S5S5S5S5S5S4S4S4S4S4S3S3S3S3S3S2S2S2S2S2S1S1S1S1S1S0S0S0S0S0Sh4414h4414 h4414 h4414h4414
S[7:0] This register is ASCII encoded to ‘A.’
F[7:0] This register is ASCII encoded to ‘D.’
geRgeR geR geRgeR
muNmuN muN muNmuN emaNemaN emaN emaNemaN51D51D 51D 51D51D41D41D 41D 41D41D31D31D 31D 31D31D21D21D 21D 21D21D11D11D 11D 11D11D01D01D 01D 01D01D9D9D9D9D9D8D8D8D8D8D7D7D7D7D7D6D6D6D6D6D5D5D5D5D5D4D4D4D4D4D3D3D3D3D3D2D2D2D2D2D1D1D1D1D1D0D0D0D0D0DtluafeDtluafeD tluafeD tluafeDtluafeD
hE7hE7 hE7 hE7hE72DIrodneV2DIrodneV 2DIrodneV 2DIrodneV2DIrodneV7T7T7T7T7T6T6T6T6T6T5T5T5T5T5T4T4T4T4T4T3T3T3T3T3T2T2T2T2T2T1T1T1T1T1T0T0T0T0T0T7VER7VER 7VER 7VER7VERVERVER VER VERVER66
6
66VERVER VER VERVER55
5
55VERVER VER VERVER44
4
44VERVER VER VERVER33
3
33VERVER VER VERVER22
2
22VERVER VER VERVER11
1
11VERVER VER VERVER00
0
00h2635h2635 h2635 h2635h2635
T[7:0] This register is ASCII encoded to ‘S.’

REV. 0
–16–
C02497–.8–7/01(0)
PRINTED IN U.S.A.
AD1887
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP)
(ST-48)
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.019 (0.5)
BSC
0.276
(7.00)
BSC
SQ
0.011 (0.27)
0.006 (0.17)
0.354 (9.00) BSC SQ
0.063 (1.60)
MAX
0.030 (0.75)
0.018 (0.45)
0.008 (0.2)
0.004 (0.09)
0ⴗ
MIN
COPLANARITY
0.003 (0.08)
SEATING
PLANE
0.006 (0.15)
0.002
(
0.05
)
7ⴗ
0ⴗ
0.057 (1.45)
0.053 (1.35)