ARTERY AT32F435 Series Specification sheet

AT32F435 & AT32F437 Get Started Guide
2022.4.20 1 Ver 2.0.0
AN0128
Application Note
AT32F435 & AT32F437 Get Started Guide
Introduction
This application note is used to help users quickly develop projects using AT32F435xx/AT32F437xx,
where AT32F437 is designed with EMAC function.
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Product number
AT32F435xx
AT32F437xx

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Contents
Preliminary environment preparation.................................................................. 5
Set up AT32 development environment.................................................................... 5
Debug tools and development board...........................................................................5
Programming tools and software.................................................................................5
AT32 Keil and IAR development environment.............................................................6
AT32F403A/407 replacement process.........................................................................9
AT32F435 /AT32F437 enhanced functional configuration ........................................ 9
PLL clock settings ........................................................................................................9
How to use FPU (floating point unit)..........................................................................10
AT32F435 /AT32F437 zero-wait/non-zero wait Flash and embedded SRAM
configurations.........................................................................................................................10
Encryption (access protection, erase/program protection)........................................15
RecognizeAT32 in program and other IC methods...................................................18
AT32F435/AT32F437 advanced functions.................................................................19
FAQ about download and compilation process ............................................... 21
Enter Hard Fault Handler when starting program ................................................... 21
Errors in program downloading............................................................................... 21
Error: Flash Download failed–“Cortex-M4” ................................................................21
No Debug Unit Device found......................................................................................22
RDDI-DAP Error.........................................................................................................22
ISP interface gets stuck during download..................................................................22
AT32 download resuming...........................................................................................22
Security Library (sLib)......................................................................................... 23
Introduction.............................................................................................................23
Principles of application..........................................................................................23
Security library application...................................................................................... 23
Revision history................................................................................................... 24

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List of Tables
Table 1. Document revision history....................................................................................................24

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List of Figures
Figure 1. AT32F435 development board.............................................................................................5
Figure 2. Install ArteryTek.AT32F435_437_DFP.................................................................................6
Figure 3. Install Keil4_AT32MCU_AddOn...........................................................................................6
Figure 4. Pack Installer icon in Keil .....................................................................................................7
Figure 5. Keil Debug............................................................................................................................7
Figure 6. Keil Debug Settings..............................................................................................................7
Figure 7. Keil Utilities...........................................................................................................................7
Figure 8. Install IAR_AT32MCU_AddOn.............................................................................................8
Figure 9. IAR Debug............................................................................................................................8
Figure 10. IAR CMSIS-DAP.................................................................................................................8
Figure 11. PLL auto step-by-step system clock switch configuration..................................................9
Figure 12. ICP Programmer –User system data..............................................................................11
Figure 13. User system data - set SRAM size ..................................................................................12
Figure 14. ISP Programmer - Edit User system data........................................................................12
Figure 15. Define Extend_SRAM(void) to change SRAM size.........................................................13
Figure 16. Change SRAM size in Keil startup file .............................................................................14
Figure 17. Change SRAM size in IAR startup file .............................................................................14
Figure 18. ISP programmer –enable access protection...................................................................16
Figure 19. ISP programmer –disable access protection..................................................................16
Figure 20. ICP Programmer –enable erase/program protection......................................................17
Figure 21. ICP programmer –disable erase/program protection......................................................18
Figure 22. Read Cortex model...........................................................................................................18
Figure 23. Read PID and UID............................................................................................................19
Figure 24.AT-SURF-F437 development board.................................................................................20
Figure 25.Add code to enable FPU ..................................................................................................21
Figure 26. Error: Flash Download failed–“Cortex- 4” ........................................................................21

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Preliminary environment preparation
Download the development environment from Artery’s official website:
http://www.arterytek.com
Set up AT32 development environment
Debug tools and development board
The AT32F435 /AT32F437 development boards are designed with AT-Link-EZ, as shown in the left
red box of the figure below. The debug tool AT-Link-EZ can also be disassembled from the
development board and used separately with other circuit boards. It supports IDE online debugging,
online programming, USB-to-serial interface, and other functions.
Figure 1. AT32F435 development board
Programming tools and software
AT programming tools and software: AT-Link /AT-Link-Pro /AT-Link-ISO /AT-Link-EZ /J-Link,
ICP/ISP.
Third-party programming tools:
Xuanwei: https://xuanweikeji.taobao.com
MaxWiz: www.maxwiz.com.cn
ZLG: http://tools.zlg.cn/tools
Amomcu: http://www.amomcu.cn
For details about ICP, refer to UM_ICP_Programmer. Download the ICP tool from Artery's
official website and extract files.
File path: Artery_ICP_Programmer_Vx.x.xx\Document\UM_ICP_Programmer.
For details about ISP, refer to UM_ISP_Programmer. Download the ISP tool from Artery's
official website and extract files.
File path: Artery_ISP_Programmer_Vx.x.xx\Document\UM_ISP_Programmer.
For details aboutAT-Link, refer to UM0004_AT-Link_User_Manual. Download AT-Link-Family
from Artery's official website and extract files.

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File path: AT_Link_CH_ Vx.x.x \05_Documents\UM0004_AT-Link_User_Manual_ZH_Vx.x.x.
AT32 Keil and IAR development environment
①For Keil compiler system, keil4.74, keil5.23 or above is recommended.
Users need to download the pack from Artery's official website and then add the corresponding
AT32 MCU to Keil. For Keil_v5, extract files from Keil5_AT32MCU_AddOn and then install
ArteryTek.AT32F435_437_DFP. For Keil_v4, install Keil4_AT32MCU_AddOn. The Keil installation
path is identified automatically, by default. If it is not identified or incorrect, users need to manually
select the Keil installation path.
Figure 2. Install ArteryTek.AT32F435_437_DFP
Figure 3. Install Keil4_AT32MCU_AddOn
Users can also open Keil and click on the Pack Installer icon, then click “File” at the top left in the
Pack Installer interface and click “Import” to import the corresponding pack downloaded from
Artery's official website.

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Figure 4. Pack Installer icon in Keil
When using AT-Link in Keil, select CMSIS-DAP debugger in “Debug” option.
Figure 5. Keil Debug
Click Debug --> Settings to enter the Cortex-M Target Driver Setup interface as shown below.
1. Select AT-Link-CMSIS-DAP;
2. Select SW for Port, and check the SWJ box;
3. Confirm that the ARM SW-DP debug module is identified.
Figure 6. Keil Debug Settings
Click “Utilities”, uncheck the “Use Debug Driver” box (the red box marked 1), then select “CMSIS-
DAP Debugger” in “Settings” (the red box marked 2), and finally check the “Use Debug Driver” box
(note: users need to uncheck this box first and then check it).
Figure 7. Keil Utilities
②For IAR compiler system, IAR7.0, IAR6.1 or above is recommended.
Users need to download the pack from Artery's official website and then add the corresponding AT32

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MCU to IAR. When installing IAR_AT32MCU_AddOn, its installation path is identified automatically,
by default. If it is not identified or incorrect, users need to manually select the IAR installation path.
Figure 8. Install IAR_AT32MCU_AddOn
When using AT-Link in IAR, select CMSIS-DAP debugger in “Debugger”.
Figure 9. IAR Debug
Figure 10. IAR CMSIS-DAP
③BSP and PACK
For details about BSP and PACK, refer to AT32F435_437 firmware library BSP&Pack user guide.
Download BSP from Artery's official website and extract files.
File path: AT32F435_437_Firmware_Library_V2.x.x\document.

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AT32F403A/407 replacement process
Please download MG0018_Migrating from AT32F403A_407 to AT32F435_437 from Artery's
official website.
If the program still does not work properly, please refer to other related sections in this guide,
or contact the agent and Artery’s technical staff for support.
AT32F435 /AT32F437 enhanced functional configuration
PLL clock settings
PLL setting methods
The internal PLL of AT32F435 /AT32F437 has a maximum output frequency of 288 MHz. The PLL
clock configuration register (CRM_PLLCFG) is set according to the output frequency.
PLL output clock = PLL reference input clock × PLL frequency multiplication factor (PLL_NS)
PLL predivider factor (PLL_MS)× PLL post − divider factor (PLL_FR)
For example, when PLL=288 MHz (HEXT=8 MHz):
/*!< config pll clock */
crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2);
where, “HEXT” in the parameter “CRM_PLL_SOURCE_HEXT” means that HEXT clock is used as
an external clock; PLL_NS=72, PLL_MS=1, and “CRM_PLL_FR_2 (0x01, divided by 2) is the
PLL_FR value.
For details about clock configuration, download AN0084_AT32F435_437_CRM_Start_Guide from
Artery's official website. This document introduces the clock source configuration and modification
of AT32F435/437 series, and how to use the New Clock Configuration tool to quickly generate the
desired clock code and apply it to projects.
PLL auto step-by-step system clock switch
When the internal PLL clock of AT32F435 /AT32F437 series is above 108 MHz, it is recommended
to enable the auto step-by-step system clock switch.
The following is an example of PLL auto step-by-step system clock switch program when using
AT32F435 /AT32F437 BSP.
Figure 11. PLL auto step-by-step system clock switch configuration
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);

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/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
Note: If the auto step-by-step system clock switch is enabled, after the clock is switched, it must be disabled.
Flash clock division
Flash clock divider factor corresponds to the system clock frequency, as shown below.
System Clock Frequency
Flash Clock Division
<= 240 MHz
FLASH_CLOCK_DIV_2
>240 MHz
FLASH_CLOCK_DIV_3
Code implementation:
flash_clock_divider_set(FLASH_CLOCK_DIV_3); /* Flash divider: system clock divided by 3 */
How to use FPU (floating point unit)
Please refer to AN0037_How_to_use_FPU on Artery's official website. This application note
introduces how to use FPU on AT32 MCU and related configuration in Keil / IAR.
AT32F435 /AT32F437 zero-wait/non-zero wait Flash and
embedded SRAM configurations
The use of internal Flash memory and embedded SRAM is supported by user system data
configurations.
The embedded SRAM of AT32F435/ AT32F437 is 384 KB, by default. Users can enable a dynamic
switch between 128 KB (minimum) and 512 KB (maximum) by setting the EOPB0 bit. To enable
EOPB0, a power-down or RESET must occur.
The user system data area ofAT32F435/AT32F437 is as follows.
Address
Bit
Description
0x1FFF_C010
[7:0]
EOPB0[7:0]: Extended system option
Refer the table below for more details.
Note: This bit can be changed only when the security library is disabled.
[15:8]
nEOPB0[7:0]: Inverse code of EOPB0[7:0]
[31:16]
Reserved