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www.achronix.com
Bitporter User Guide
UG004 v1.1 – March 20, 2009

PAGE i www.achronix.com Bitporter User Guide
Copyright Info
Copyright © 2008–2009 Achronix Semiconductor Corporation. All rights reserved. Achronix,
Speedster, and picoPIPE are trademarks of Achronix Semiconductor Corporation. All other
trademarks are the property of their prospective owners. All specifications subject to change
without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any repre-
sentations or warranties as to the completeness or accuracy of such information and shall have
no liability for the use of the information contained herein. Achronix Semiconductor
Corporation reserves the right to make changes to this document and the information
contained herein at any time and without notice. All Achronix trademarks, registered
trademarks, disclaimers and patents are listed at http://www.achronix.com/legal.
Achronix Semiconductor Corporation
333 West San Carlos Street, Suite 1050
San Jose, CA, 95110
USA
Phone : 877.GHZ.FPGA (877.449.3742)
Fax : [phone]
E-mail : [email protected]

Bitporter User Guide www.achronix.com PAGE ii
Table of Contents
Preface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iv
About this Guide - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iv
Reference Documents - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iv
Conventions Used in this Guide - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iv
Chapter 1 – Configuration Overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1
Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1
JTAG Configuration using the Bitporter Pod - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2
Supported Operating Systems - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2
Minimum Hardware Requirements - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3
Board-Level Device Connections - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3
Chapter 2 – Software and Driver Install - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5
Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -5
Standalone STAPL Player and USB Driver Install - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5
Windows - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5
Linux - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8
Chapter 3 – Connecting the Bitporter Pod- - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9
Choosing a Connection Type — USB versus Ethernet - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
Connecting the Bitporter Pod - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
Connecting the Bitporter Pod via Ethernet (Windows and Linux) - - - - - - - - - - - - - - - - - - - - - 13
Disconnecting the Bitporter Pod - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14
Bitporter Connection Errors - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14
“Attempting to auto-detect Bitporter pods (USB pods and Ethernet pods on this sub net)...
found 0 pods.” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14
“PROGRAM ERROR: Bitporter driver library not found - unable to program device.” - - - - - - 14
“Port has not been opened” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
“Unable to retrieve pathname for USB device” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
“USB communication error” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
“USB communication timeout” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
“Unable to load hid.dll. One or more exported functions missing”- - - - - - - - - - - - - - - - - - - - - 15
“Can't open setupapi.dll: <reason>” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
“Can't open hid.dll: <reason>“ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15

PAGE iii www.achronix.com Bitporter User Guide
“USB read error. <reason>” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
“USB write error. <reason>” - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15
"No available Achronix Bitporter products with matching serial number found on USB port." 15
Ethernet Connection Errors: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16
"No available Achronix Bitporter products with matching serial number found on local
subnet." - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16
"No available Achronix Bitporter product found at supplied network address." - - - - - - - - - - - 16
"Network device is not an Achronix Bitporter pod."- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16
Verifying the Setup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16
Bitporter Connectivity Self Test- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16
Bitporter-to-Target-Device Connectivity Test- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17
Handling Multiple Pods Connected to the Same PC - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17
Chapter 4 – Using the Achronix STAPL Player - - - - - - - - - - - - - - - - - - - - - - - 19
Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 19
Command Syntax - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 19
Bitporter Pod Naming Conventions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20
Picking a STAPL Action (-a option) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20
Procedures - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 21
The Action read_idcode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 22
The Action program - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 22
The Action verify - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 23
The Action read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 23
The Action read_state - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 25
The Action erase - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27
Querying the Availability of Connected Pods (-q option) - - - - - - - - - - - - - - - - - - - - - - - - 28
Connecting to Specific Pods by Name (-p option) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29
Configuring the Bitporter Pod's IP address (-i Option) - - - - - - - - - - - - - - - - - - - - - - - - - - 30
Bitporter Pod MAC Addresses - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30
Checking the Bitporter Pod's Current Ethernet IP Configuration - - - - - - - - - - - - - - - - - - - - - - 30
Configuration the Pod for DHCP (Dynamic IP Address) - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31
Configuring the Pod to Use a Static IP Address - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32
Programming a Device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33
Revision History- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35

Bitporter User Guide www.achronix.com PAGE iv
Preface
About this Guide
This guide provides details about device programming within the Achronix CAD
Environment (ACE), starting with an existing bitstream through to downloading and device
configuration.
This guide consists of the following chapters:
Chapter 1 – “Configuration Overview” provides an overview of configuring Achronix
FPGAs.
Chapter 2 – “Software and Driver Install” details the installation of the Bitporter USB drivers
and the Achronix STAPL player.
Chapter 3 – “Connecting the Bitporter Pod” covers connecting the pod to a target device and
host PC.
Chapter 4 – “Using the Achronix STAPL Player” covers the syntax and usage of the STAPL
player.
Reference Documents
ACE User Guide (UG001)
ACE Installation and Licensing Guide (UG002)
ACE Quick Start Guide (UG003)
EIA/JEDEC Standard 71 (JESD71), Standard Test and Programming Language (STAPL)
Conventions Used in this Guide
Item Format Examples
Command-line entries Formatted with the Courier bold
font face.
$ Open top_level_name.log
File Names Formatted with the Courier font
face.
filename.ext
GUI buttons, menus
and radio buttons
Formatted with the Helvetica bold
font face.
Click OK to continue.
File →Open
Variables Formatted with italic emphasis. design_dir/output.log
Window and dialog
box headings and
sub-headings
Heading formatted in quotation
marks.
Under “Output Files,” select ...
Window and dialog
box names
Initial caps. From the Add Files dialog box, ...

Conventions Used in this Guide
PAGE v www.achronix.com Bitporter User Guide

Bitporter User Guide www.achronix.com PAGE 1
Chapter 1 – Configuration Overview
Introduction
Achronix Semiconductor delivers the world’s fastest commercially available FPGAs. Using CMOS
process technology and conventional SRAM-based device configuration, Speedster™ FPGAs are
capable of operating at 1.5 GHz of system throughput by using unique picoPIPE™ technology.
The embedded programming and configuration logic in the FPGA is designed to support a
variety of programming options. Figure 1-1 outlines the basic block diagram of the
programming and configuration logic, including additional logic to implement security
features. The configuration management unit controls the startup and shutdown sequence
from configuration mode to the user mode and back. The configuration management unit
includes the provisions for configuring the device with a secure bitstream using a 256-bit
Advanced Encryption Standard (AES) algorithm in Cipher Block Chaining (CBC) mode. The
device contains a small non-volatile memory for the storage of the required AES key.
This guide covers configuration via the JTAG port using the Achronix Bitporter pod.
Figure 1-1: Speedster Configuration Options
Configuration Logic
FPGA
User Logic
JTAG
USB
Bitporter
Pod
JTAG
Interface
External CPU
CPU Slave
Controller
Serial (SPI)
Flash
SPI Flash
Controller
Serial
Data
ug004_c01_01_v04
••
FPGA
Configuration
Management
Unit
SRAM Scan
Chain
AES
Decode
AES NV
Key
Storage
Mode and Status Pins
Ethernet

JTAG Configuration using the Bitporter Pod Configuration Overview
PAGE 2 www.achronix.com Bitporter User Guide
JTAG Configuration using the Bitporter Pod
The Bitporter pod (Figure 1-2) connects between a host PC via either a 10/100 Ethernet or
USB 2.0 connection and an EJTAG-compliant connector on the target system. When
connected, the Bitporter pod supports device configuration and debug, along with flash
memory programming.
Note: USB 1.0 and 1.1 are also supported, but discouraged for performance reasons.
The JTAG configuration flow is as follows:
• Generate a design_name.jam file from a placed-and-routed design within ACE.
• Connect the Bitporter pod to either the USB or Ethernet port of the host PC and to the
JTAG port of the target Speedster device.
•Play the STAPL file to the FPGA using acx_stapl_player.exe, executed from
the command line, or via the Download view within ACE (see “Playing a STAPL File”
in ACE User Guide (UG001) for details).
Supported Operating Systems
JTAG programming is currently supported under the following operating systems:
•Foracx_stapl_player with USB-connected Bitporter pods:
♦Red Hat Enterprise Linux Release 5, 32-bit
♦CentOS 5, 32-bit
♦Microsoft Windows XP Professional SP2 32-bit (other versions may work, but are
untested)
Figure 1-2: Bitporter Pod
ug004_c01_02_v01

Configuration Overview Minimum Hardware Requirements
Bitporter User Guide www.achronix.com PAGE 3
•Foracx_stapl_player with Ethernet-connected Bitporter pods:
♦Red Hat Enterprise Linux Release 5, 32-bit
♦Red Hat Enterprise Linux WS Release 4, 32-bit
♦CentOS 5, 32-bit
♦Microsoft Windows XP Professional SP2 32-bit (other versions may work, but are
untested)
Note: Other 32-bit versions of Linux may work, but are unsupported. No 64-bit operating systems are
supported at this time.
Minimum Hardware Requirements
• Pentium-class PC with a minimum of 128 MB of memory (512 MB for Windows Vista)
• Either a USB 2.0 port and/or an Ethernet connection for the Bitporter pod
Note: USB 1.0 and 1.1 may be used but USB 2.0 is strongly recommended for performance
reasons. In addition, a USB port connection is required to change the Ethernet configuration of a
Bitporter pod (Bitporter pods are configured for DHCP by default — if this configuration is
acceptable, no USB connection is needed).
Board-Level Device Connections
Figure 1-3 details the board-level electrical connections to the JTAG header, and Figure 1-4
provides the mechanical specifications.
Figure 1-3: JTAG Header Electrical Connections
ug004_c01_03_v02
1
TRST
TDI
TDO
TMS
TCK
NC
NC
FPGA
1 KΩ
10 KΩ 10 KΩ 10 KΩ
VDDO_JTAG VDDO_JTAG