Atmel AT43USB324 User manual

1
Features
•AVR®8-bit RISC Microcontroller with 83 ns Instruction Cycle Time
•USB Hub with One Attached and Two External Ports
•USB Keyboard Function with Three Endpoints
•16K Bytes of Program Memory, 512 Bytes SRAM
•32 x 8 General-purpose Working Registers
•34 Programmable I/O Port Pins
•Support for 18 x 8 Keyboard Matrix
•Keyboard Scan Inputs with Pull-up Resistors
•4 LED Driver Outputs
•One 8-bit Timer/Counter with Separate Prescaler
•External and Internal Interrupt Sources
•Programmable Watchdog Timer
•6 MHz Oscillator with On-chip PLL
•5V Operation with On-chip 3.3V Power Supply
•48-lead SSOP and 48-lead LQFP
Overview
The Atmel AT43USB324 is a compound USB device designed for use in multimedia
USB keyboards with an embedded hub. Internally, the AT43USB324 consists of a
USB hub and function interface, a hub repeater, and an AVR microcontroller. To the
USB host, the embedded function appears as an attached port of the hub with its own
device address and three endpoints. The third function endpoint makes the
AT43USB324 extremely suitable for keyboards supporting the Consumer Page as
described in the USB HID Usage tables. A typical application of the AT43USB324 is
shown in Figure 1 and block diagrams are shown in Figures 2 and 3.
The AT43USB324 interfaces to the USB host at the transaction layer while the micro-
controller firmware handles the USB protocol layers in addition to performing the
keyboard control functions. Except for LEDs, no other external components are
required for the keyboard function.
Pin Configurations
USB Multimedia
Keyboard
Controller
AT43USB324
Rev. 1941A–02/01
48-lead SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PD6
PD7
XTAL1
XTAL2
LFT
PE1
PE0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PC7
PD5
PD4
VCC
CEXT
VSS
TEST
RESET
DM0
DP0
DM2
DP2
DM3
DP3
PD3
PD2
PD1
PD0
PC0
PC1
PC2
PC3
PC4
PC5
PC6
48-lead LQFP
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TEST
VSS
CEXT
VCC
PD4
PD5
PD6
PD7
XTAL1
XTAL2
LFT
PE1
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PA0
PA1
PA2
PA3
PA4
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
PE0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5
RESET DM0 DP0 DM2 DP2 DM3 DP3 PD3 PD2 PD1 PD0 PC0
查询AT43USB324 供应商 捷多邦，专业PCB打样工厂，24小时加急出货

2AT43USB324
1941A–02/01
Figure 1. A Typical USB Hub/Keyboard Application
Figure 2. USB Block Diagram (1)
AT43USB324
XTAL1
XTAL2
LFT
RST
TEST
PWR3/PD3
PWR2/PD4
OVC3/PD2
OVC2/PD1
DP0
DM0
DP2
DM2
DP3
DM3
PA[0:7]
PB[0:7]
PE[0, 1]
PC[0:7]
PD[5:7]
PD0
CEXT
VCC
VSS
COL[0:7]
COL[8:15]
COL[16,17]
ROW[0:7]
LEDs
KEYBOARD
DATA
ADDRESS
CONTROL
AVR CPU 16K ROM
512 BYTES SRAM
PORT A
PORT B
PORT C
PORT D
PORT E
INT
UNIT
OSC
&
PLL
WDT
T/C0
USB BLOCK

3
AT43USB324
1941A–02/01
Figure 3. USB Block Diagram (2)
PORT 0
XCVR
HUB
REPEATER
SERIAL
INTERFACE
ENGINE
HUB
INTERFACE
UNIT
FUNCTION
INTERFACE
UNIT
AVR
MICROCONTROLLER
DATA
ADDRESS
CONTROL
PORT 2
XCVR
PORT 3
XCVR

4AT43USB324
1941A–02/01
Pin Assignment
Type: I = Input
O=Output
B = Bi-directional
U = USB IO
V = Power Supply, Ground
48-lead LQFP Pin Assignment
Pin # Signal Type Pin # Signal Type
1 TEST I 25 PA4/CL4 B
2 VSS V 26 PA3/CL3 B
3 CEXT V 27 PA2/CL2 B
4VCCV 28PA1/CL1B
5PD4B 29PA0/CL0B
6 PD5 B 30 PC7/RW7 B
7 PD6 B 31 PC6/RW6 B
8 PD7 B 32 PC5/RW5 B
9 XTAL1 I 33 PC4/RW4 B
10 XTAL2 O 34 PC3/RW3 B
11 LFT O 35 PC2/RW2 B
12 PE1/CL17 B 36 PC1/RW1 B
13 PE0/CL16 B 37 PC0/RW0 B
14 PB7/CL15 B 38 PD0 B
15 PB6/CL14 B 39 PD1 B
16 PB5/CL13 B 40 PD2 B
17 PB4/CL12 B 41 PD3 B
18 PB3/CL11 B 42 DP3 U
19 PB2/CL10 B 43 DM3 U
20 PB1/CL9 B 44 DP2 U
21 PB0/CL8 B 45 DM2 U
22 PA7/CL7 B 46 DP0 U
23 PA6/CL6 B 47 DM0 U
24 PA5/CL5 B 48 RESET I

5
AT43USB324
1941A–02/01
48-lead SSOP Pin Assignment
Pin # Signal Type Pin # Signal Type
1 PD6 B 25 PC6/RW6 B
2 PD7 B 26 PC5/RW5 B
3 XTAL1 I 27 PC4/RW4 B
4XTAL2O 28PC3/RW3 B
5LFTO 29PC2/RW2B
6 PE1/COL17 B 30 PC1/RW1 B
7 PE0/CL16 B 31 PC0/RW0 B
8 PB7/CL15 B 32 PD0 B
9 PB6/CL14 B 33 PD1 B
10 PB5/CL13 B 34 PD2 B
11 PB4/CL12 B 35 PD3 B
12 PB3/CL11 B 36 DP3 U
13 PB2/CL10 B 37 DM3 U
14 PB1/CL9 B 38 DP2 U
15 PB0/CL8 B 39 DM2 U
16 PA7/CL7 B 40 DP0 U
17 PA6/CL6 B 41 DM0 U
18 PA5/CL5 B 42 RESET I
19 PA4/CL4 B 43 TEST I
20 PA3/CL3 B 44 VSS V
21 PA2/CL2 B 45 CEXT V
22 PA1/CL1 B 46 VCC V
23 PA0/CL0 B 47 PD4 B
24 PC7/RW7 B 48 PD5 B

6AT43USB324
1941A–02/01
Signal Description
Signal Type Name and Functions
VCC V Power Supply –5V supply input
CEXT O External Capacitor –A high quality 0.47 µF must be connected to CEXT for proper
operation of the chip.
VSS V Ground
XTAL1 I Oscillator Input –Input to the inverting oscillator amplifier
XTAL2 O Oscillator Output –Output of the inverting oscillator amplifier
LFT I
PLL Filter –For proper operation of the PLL, this pin should be connected through
a 0.01 µF capacitor in parallel with a 100Ωresistor in series with a 0.22 µF
capacitor to ground (VSS). Both capacitors must be high quality ceramic
DP0 U
Upstream Plus USB I/O –This pin should be connected to CEXT1 through an
external 1.5 kΩpull-up resistor. DP0 and DM0 form the differential signal pin pairs
connected to the host controller or an upstream hub
DM0 U Upstream Minus USB I/O
DP[2,3] U
Port Plus USB I/O –Each of these pins should be connected to VSS through an
external 15 kΩresistor. The DP[2,3] and DM[2,3] are the differential signal-pin pairs
to connect downstream USB devices
DM[2,3] U Port Minus USB I/O –Each of these pins should be connected to VSS through an
external 15 kΩresistor
PA[0:7] B Port A[0:7] –Bi-directional 8-bit I/O port with controlled slew rate. These pins are
used as eight of the keyboard matrix column output strobes: PA[0:7] = COL[0:7]
PB[0:7] B
Port B[0:7] –Bi-directional 8-bit I/O port with controlled slew rate. These pins are
used as the eight of the keyboard matrix column output strobes: PB[0:7] =
COL[8:15]
PC[0:7] B Port C[0:7] –Bi-directional 8-bit I/O port with internal pull-ups. These pins are used
as keyboard matrix row input signals: PC[0:7] = ROW[0:7]
PD[0:7] B
Port D[0:7] –Bi-directional I/O ports. PD[4:7] have built-in series limiting resistors
and can be used to drive LEDs directly. An alternate function of PD2 is as INT0 and
PD3 is as INT1, the external interrupt pins
PE[0:1] B Port E[0:1] –Bi-directional I/O port with controlled slew rate which can be used as
two additional keyboard column output strobes: COL 16, 17
RESET IReset –A low on this pin for two machine cycles while the oscillator is running
resets the device
TEST I Test Pin –This pin should be tied to ground

7
AT43USB324
1941A–02/01
Multimedia
Keyboards
The hardware of the AT43USB324 supports a wide variety of USB keyboards with an
embedded hub. The exact configuration and function of the keyboard/hub is defined by
the firmware programmed into its masked ROM.
Oscillator and PLL All the clock signals required to run the AT43USB324 are derived from on-chip oscilla-
tor. To reduce EMI and power dissipation, the oscillator is designed to operate with a
6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data separa-
tor of the serial interface engine. In the suspended state, the oscillator circuitry is turned
off.
The oscillator of the AT43USB324 is of a special low drive type, designed to work with
most crystals without any external components. The crystal must be of the parallel reso-
nance type requiring a load capacitance of about 10 pF. If the crystal requires a higher
value capacitance, external capacitors can be added to the two terminals of the crystal
and ground to meet the required value. To assure quick startup, a crystal with a high Q,
or low ESR, should be used. To meet the USB hub frequency accuracy and stability
requirements for hubs, the crystal should have an accuracy and stability of better than
100 ppm. The use of a ceramic resonator in place of the crystal is not recommended
because a resonator would not have the necessary frequency accuracy and stability.
The clock can also be externally sourced. In this case, connect the clock source to the
XTAL1 pin, while leaving XTAL2 pin floating. The switching level at the XTAL1 pin can
be as low as 0.47V (see Electrical Specifications section on page 10) and a CMOS
device is required to drive this pin to maintain good noise margins at the low switching
level.
For proper operation of the PLL, an external RC filter consisting of a series RC network
of 100Ωand 0.22 µF in parallel with a 0.01 µF capacitor must be connected from the
LFT pin to VSS (see Figure 4). Use only high quality ceramic capacitors.
Figure 4. External RC Filter
I/O Pins The keyboard matrix strobe output pins, PA[0:7], PB[0:7] and PE[0,1] have controlled
slope drives. With a load of 100 pF, the output fall time ranges between 75 ns and
300 ns. The keyboard matrix strobe input pins, PC[0:7] have built-in pull-up resistors, 20
kΩnominal value, to the internal 3.3V power supply.
Y1
6.000 MHz
R1
100
C1
0.22 µF
C2
0.01 µF
XTAL1
XTAL2
LFT
U1
AT43USB324

8AT43USB324
1941A–02/01
The PD[4:7] have 5V tolerant open-drain outputs and each has a built-in series resistor
of 330Ωnominal value. These output pins are designed for driving a LED connected to
the 5V supply.
The remaining GP I/O pins of the AT43USB324 are bi-directional with CMOS inputs and
push-pull outputs.
Hub and Port Power
Management
The embedded hub in a keyboard will most likely be a bus-powered hub even though
the hardware of the AT43USB324 is designed to accommodate both types of hubs.
Management of the downstream port power is also defined by the firmware –per port or
global overcurrent sensing, individual or gang power switching. While the interface to
the external power supply monitoring and switching is achieved through the microcon-
troller’s I/O ports, the USB hardware of the AT43USB324 contains the circuitry to handle
all the possible combinations port power management tasks.
Overcurrent Sensing The AT43USB324 is capable of detecting an overcurrent in its downstream ports even
while it is in the suspend state. Overcurrent input flag for Port 2 is routed to PD1 and for
Port 3 to PD2.
1. Global Overcurrent Protection. In this mode, the Port Overcurrent Indicator
and Port Overcurrent Indicator Change should be set to 0’s. For the
AT43USB324, an external solid state switch, such as the Micrel MIC2025, is
required to switch power to both external USB ports. The FLG output of the
switch should be connected to either PD0 or PD1 of the microcontroller. When
an overcurrent occurs, FLG is asserted and the firmware should set the Hub
Overcurrent Indicator and Hub Overcurrent Indicator Change and switch off
power to the hub.
2. Individual Port Overcurrent Protection. The Hub Overcurrent Indicator and
Hub Overcurrent Indicator Change bits should be set to 0’s. One MIC2536 is
required for the two USB ports. One FLG output of the MIC2536 should be con-
nected to PD0 and the other to PD1 of the microcontroller. An overcurrent is
indicated by FLG being asserted. The firmware sets the corresponding port’s
Overcurrent Indicator and the Overcurrent Indicator Change bits and switches off
power to the port. At the next IN token from the host, the AT43USB324 reports
the status change.
Port Power Switching 1. Gang Power Switching. One of the microcontroller I/O port pins must be pro-
grammed as an output to control the external switch, PWR. Switch ON is
requested by the USB host through the SetPortFeature (PORT_POWER)
request. Switch OFF is executed upon receipt of a ClearPortFeature
(PORT_POWER) or upon detecting an overcurrent condition. The firmware
clears the Power Control Bit. Only if all BOTH of the Power Control Bits of Ports 2
AND 3 are cleared should the firmware de-assert the PWR pin.
2. Individual Power Switching. One microcontroller I/O port pin must be assigned
for each USB port to control the external switch, PWRx, where x = 2, 3. Each of
the Power Control Bits controls one PWRx.
Power Management
Circuit
Figure 5 shows a simplified diagram of a power management circuit of an
AT43USB324-based hub design with global overcurrent protection and ganged power
switching.

9
AT43USB324
1941A–02/01
Figure 5. Power Management Circuit Diagram
BUS_POWER
GND
GND
VCC
AT43USB324
PWR
OVC
CTL
FLG
PORT2_POWER
PORT2_GND
PORT3_POWER
PORT3_GND
SWITCH
IN OUT
U1
U2

10 AT43USB324
1941A–02/01
Electrical Specification
DC Characteristics
The values shown in this table are valid for TA= 0°C to 85°C, VCC = 4.4V to 5.25V, unless otherwise noted.
Absolute Maximum Ratings*
Operating Temperature.................................. -40°C to +125°C*NOTICE: Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time
may affect device reliability.
Storage Temperature ..................................... -65°C to +150°C
All Input/Output Voltage .........-0.3V to VCEXT + 0.3V, 4.6V max
Supply Voltage (VCC) .......................................... 4.4V to +5.5V
Power Supply
Symbol Parameter Min Max Unit
VCC 5V Power Supply 4.4 5.25 V
ICC 5V Supply Current 30 mA
ICCS Suspended Device Current 150 µA
USB Signals: DPx, DMx
Symbol Parameter Condition Min Max Unit
VIH Input Level High (Driven) 2.0 V
VIHZ Input Level High (Floating) 2.7 V
VIL Input Level Low 0.8 V
VDI Differential Input Sensitivity DPx and DMx 0.2 V
VCM Differential Common Mode Range 0.8 2.5 V
VOL1 Static Output Low RL of 1.5 kΩto 3.6V 0.3 V
VOH1 Static Output High RL of 15 kΩto GND 2.8 3.6 V
VCRS Output Signal Crossover 1.3 2.0 V
VIN Input Capacitance 20 pF

11
AT43USB324
1941A–02/01
Note: XTAL2 must not be used to drive other circuitry.
PA, PB, PC, PD, PE
Symbol Parameter Condition Min Max Unit
VOL2 Output Low Level, PA, PB, PE0,1 IOL = 4 mA 0.5 V
RPU PC Pull-up Resistor Current V = 0 90 280 µA
VIL3 Input Low Level, PC 0.3
VCEXT
V
VIH3 Input High Level, PC 0.7
VCEXT
V
VIL4 Input Low Level, PD[0:3] 0.3
VCEXT
V
VIH4 Input High Level, PD[0:3] 0.7
VCEXT
V
VOL4 Output Low Level, PD[0:3] IOL = 4 mA 0.3
VCEXT
V
VOH4 Output High Level, PD[0:3] IOH = 4 mA 0.7
VCEXT
V
C Input/Output Capacitance 1 MHz 10 pF
Oscillator Signals: XTAL1, XTAL2
Symbol Parameter Condition Min Max Unit
VLH XTAL1 Switching Level 0.47 1.20 V
VHL XTAL2 Switching Level 0.67 1.44 V
CX1 Input Capacitance, XTAL1 10 pF
CX2 Output Capacitance, XTAL2 10 pF
C12 XTAL1/2 Capacitance 5pF
tSU Start-up Time 6 MHz,
Fundamental 2ms
DL Drive Level 50 µW

12 AT43USB324
1941A–02/01
AC Characteristics
Note: 1. With external 27Ωseries resistor.
Note: 1. With 6.000 MHz, 100 ppm crystal.
DPx, DMx Driver Characteristics, Full Speed Operation
Symbol Parameter Condition Min Max Unit
tRRise Time CL = 50 pF 4 20 ns
tFFall Time CL = 50 pF 4 20 ns
tRFM tR/tFMatching 90 110 %
ZDRV Driver Output Resistance(1) Steady State Drive 28 44 Ω
DPx, DMx Source Timings, Full Speed Operation
Symbol Parameter Condition Min Max Unit
tDRATE Full Speed Data Rate(1) Average Bit Rate 11.97 12.03 Mb/s
tFRAME Frame Interval(1) 0.9995 1.0005 ms
tRFI Consecutive Frame Interval Jitter(1) No Clock
Adjustment
42 ns
tRFIADJ Consecutive Frame Interval Jitter(1) With Clock
Adjustment
126 ns
tDJ1
tDJ2
Source Differential Driver Jitter
To N e xt Tr a ns i t i o n
For Paired Transitions
-2
-1
2
1ns
tFDEOP Source Jitter for Differential Transition to SEO
Transitions
-2 5 ns
tDEOP Differential to EOP Transition Skew -2 5 ns
tJR1
tJR2
Receiver Data Jitter Tolerance
To N e xt Tr a ns i t i o n
For Paired Transitions
-18.5
-9
18.5
9ns
tFEOPT Source SEO Interval of EOP 160 175 ns
tFEOPR Receiver SEO Interval of EOP 82 ns
tFST Width of SEO Interval during Differential Transition 14 ns
DPx, DMx Driver Characteristics, Low Speed Operation
Symbol Parameter Condition Min Max Unit
tRRise Time CL = 200 - 600 pF 75 300 ns
tFFall Time CL = 200 - 600 pF 75 300 ns
tRFM tR/tFMatching 80 125 %

13
AT43USB324
1941A–02/01
DPx, DMx Hub Timings, Full Speed Operation
Symbol Parameter Min Max Unit
tHDD2 Hub Differential Data Delay without Cable 44 ns
tHDJ1
tHDJ2
Hub Differential Driver Jitter
To N e xt Tr a ns i t i o n
For Paired Transitions
-3
-1
3
1ns
tFSOP Data Bit Width Distortion after SOP -5 5 ns
tFEOPD Hub EOP Delay Relative to tHDD 015ns
tFHESK Hub EOP Output Width Skew -15 15 ns
DPx, DMx Hub Timings, Low Speed Operation
Symbol Parameter Min Max Unit
tLHDD Hub Differential Data Delay 300 ns
tLHDJ1
tLHDJ2
tLUHJ1
tLUHJ2
Downstream Hub Differential Driver Jitter
To Next Transition, Downstream
For Paired Transitions, Downstream
To Next Transition, Upstream for Paired Transitions, Upstream
-45
-15
-45
-45
45
15
45
45
ns
tSOP Data Bit Width Distortion after SOP -60 60 ns
tLEOPD Hub EOP Delay Relative to tHDD 0200ns
tLHESK Hub EOP Output Width Skew -300 300 ns
Hub Event Timings
Symbol Parameter Condition Min Max Unit
tDCNN Time to Detect a Downstream Port Connect Event 2.5 2000 µs
tDDIS Time to Detect a Disconnect Event on Downstream
Port Awake Hub Suspended Hub
2.5
2.5
2000
12000
µs
tURSM Time from Detecting Downstream Resume to
Rebroadcast
100 µs
tDRST Duration of Driving Reset to a Downstream Device Only for a
SetPortFeature
(PORT_RESET)
Request
10 20 ms
tDSPDEV Time to Evaluate Device Speed after Reset 2.5 1000 µs
tURLK Time to Detect a Long K from Upstream 2.5 5.5 µs
tURLSEO Time to Detect a Long SEO from Upstream 2.5 5.5 µs
tURPSEO Duration of Repeating SEO Upstream 23 FS Bits
tUDEOP Duration of Sending SEO Upstream after EOF1 2 FS Bits

14 AT43USB324
1941A–02/01
Typical Application The Atmel sample version of the AT43USB324 contains firmware that supports custom-
ization of the Vendor ID, Product ID, String Descriptor and the Keyboard Matrix. This
information is stored in an external AT24C02A Serial EEPROM. Data in the EEPROM is
stored in the following format.
Detailed Description
Mask Bits The mask bits identify what features are stored in the EEPROM. A “1”in the mask bit
location means that the feature is stored and should be read. A “0”, not stored and
should not be read.
Address locations 0x04 through 0x6E store the VID, PID and String Descriptors if they
are enabled by the mask bits in location 0x03. The data are stored sequentially as
described below.
Initial Check Byte This check byte is located immediately after the last VID, PID or strings. It is computed
as the truncated sum of Mask 1 and all the string length specified.
Address range Content
0x00 - 0x01 EEPROM’s Signature
0x02 - 0x03 Mask Bits
0x04 Onwards VID, PID and Strings
Initial Check Byte
0x70 - 0xFF Keyboard Matrix
EEPROM’s Signature
Address Location Value/Content
0x00 0x17
0x01 0x5A
Address
Location Remark
0x02 Mask 2 - Reserved for Future Use
0x03
Mask 1
Bit 0:
VID, PID,
Version
Bit 1:
Language
String
Bit 2:
Manufacturer
String
Bit 3:
Product
String
Bit 4:
Serial
Number
String
Bit 5:
Extra Hot
Key Codes
Bit 6:
Reserved
Bit 7:
Keyboard
Matrix
VID and PID
VID
Byte 1
VID
Byte 2
PID
Byte 1
PID
Byte 2
Release #
Byte 1
Release #
Byte 2
Check
Byte
Language ID and Strings
Length (N) Byte 1 Byte 2 Byte N - 1 Check Byte

15
AT43USB324
1941A–02/01
Keyboard Matrix 144 bytes. If specified, its check byte is located in address 0x6F while the matrix itself is
located from address 0x70 - 0xFF.
The mask bits in location 03 are used to indicate whether a particular function is sup-
ported or not.
0x70 = Col 1, Row 1
0x71 = Col 1, Row 2
.......
0x78 = Col 2, Row 1
0x79 = Col 2, Row 2
......
0xF8 = Col 18, Row 1
0xF9 = Col 18, Row 2
.....
0xFF = Col 18, Row 8
Example of EEPROM Data
Address Data Description
00 17 Fixed ID
01 5A Fixed ID
02 00 Reserved
03 BF Mask Bits
0 = Function not Supported
1 = Function Supported
Bit7 = Keyboard Matrix
Bit6 = Reserved. Must be Set to 0
Bit5 = Extra Hot Key USB Codes
Bit4 = Serial Number String
Bit3 = Product String
Bit2 = Manufacturer String
Bit1 = Language ID String
Bit0 = VendorID, ProductID, Version.

16 AT43USB324
1941A–02/01
Vendor ID, Product ID, Version Number
Address Data Description
04 5E Vendor ID
05 04 Vendor ID
06 1D Product ID
07 00 Product ID
08 11 Version Number
09 01 Version Number
0A 91 Checksum
Language ID
Address Data Description
0B 04 Number of Bytes
0C 03 The Next 3 Bytes Specifies the
Language ID
0D 09
0E 10
0F 20 Checksum
Manufacturer String
Address Data Description
10 0C Number of Bytes, 2 Bytes per
Character
11 03
12 41 A
13 00
14 74 T
15 00
16 6D M
17 00
18 65 E
19 00
1A 6C L
1B 00
1C 02 Checksum

17
AT43USB324
1941A–02/01
Product String
Address Data Description
1D 12 Number of Bytes
1E 03
1F 4D M
20 00
21 4D M
22 00
23 4B K
24 00
25 42 B
26 00
27 44 D
28 00
29 48 H
2A 00
2B 55 U
2C 00
2D 42 B
2E 00
2F 5F Checksum
Serial Number String
Address Data Description
30 08 Number of Bytes
31 03
32 31 1
33 00
34 32 2
35 00
36 33 3
37 00
38 A1 Checksum

18 AT43USB324
1941A–02/01
Extra Hot Keys
Address Data Description
39 07 Number of Bytes
3A D0 KB Matrix Code
3B 23 First Byte Sent to Host
3C 02 Second Byte Sent to Host
3D D1 KB Matrix Code
3E 8A First Byte Sent to Host
3F 01 Second Byte Sent to Host
40 58 Checksum
Miscellaneous Data
Address Data Description
41 F0 Checksum of Mask Byte + Bytes
in Language ID + Bytes in Manuf
String + Bytes in Product String +
Bytes in Serial Number + Bytes
in Extra Hot Keys
(BF + 04 + 0C + 12 + 08 + 07 =
F0)
42 through 6E Don’t Cares. May be Written with
0’s
6F 2D Checksum of Keyboard Matrix
Codes
Keyboard Matrix
Address Data KB Row KB Col Description
70 28 0 0 KB Enter
71 31 1 0 KB \
72 50 2 0 Left Arrow
73 3F 3 0 F6
74 30 4 0 ]
75 3E 5 0 F5
76 2A 6 0 Backspace
77 2E 7 0 =
78 36 0 1 Comma
79 07 1 1 D
7A 06 2 1 C
7B 25 3 1 KB 8

19
AT43USB324
1941A–02/01
7C 0E 4 1 K
7D 20 5 1 KB 3
7E 08 6 1 E
7F 0C 7 1 I
80 63 0 2 KP Period
81 5E 1 2 KP 6
82 5B 2 2 KP 3
83 3D 3 2 F4
84 61 4 2 KP 9
85 3C 5 2 F3
86 4C 6 2 Delete
87 49 7 2 Insert
88 37 0 3 Period
89 2F 1 3 [
8A 0F 2 3 L
8B 41 3 3 F8
8C 12 4 3 O
8D 40 5 3 F7
8E 2D 6 3 -
8F 26 7 3 9
90 05 0 4 B
91 0A 1 4 G
92 19 2 4 V
93 22 3 4 5
94 09 4 4 F
95 21 5 4 4
96 17 6 4 T
97 15 7 4 R
98 13 0 5 P
99 34 1 5 Quote
9A 38 2 5 /
9B 43 3 5 F10
9C 33 4 5 ;
9D 42 5 5 F9
9E 41 6 5 Down Arrow
9F 27 7 5 0
Keyboard Matrix (Continued)
Address Data KB Row KB Col Description

20 AT43USB324
1941A–02/01
A0 10 0 6 M
A1 0D 1 6 J
A2 11 2 6 N
A3 24 3 6 7
A4 0B 4 6 H
A5 23 5 6 6
A6 18 6 6 U
A7 1C 7 6 Y
A8 68 0 7
A9 69 1 7
AA 6A 2 7
AB 2C 3 7 Space
AC 78 4 7
AD 4F 5 7 Right Arrow
AE E7 6 7 Right GUI
AF 52 7 7 Up Arrow
B0 62 0 8 KP 0
B1 5D 1 8 KP 5
B2 5A 2 8 KP 2
B3 45 3 8 F12
B4 60 4 8 KP 8
B5 44 5 8 F11
B6 4D 6 8 End
B7 4A 7 8 Home
B8 59 0 9 KP 1
B9 5C 1 9 KP 4
BA 57 2 9 KP +
BB 65 3 9 Application
BC 5F 4 9 KP 7
BD 46 5 9 Print Screen
BE 55 6 9 KP *
BF 54 7 9 KP /
C0 1B 0 10 X
C1 1A 1 10 W
C216210S
C3 3B 3 10 F2
Keyboard Matrix (Continued)
Address Data KB Row KB Col Description