Atmel AT91CAP7E User manual

AT91CAP7E is an ARM7™-based MCU with a direct FPGA interface, six-layer advanced high-speed
bus (AHB), peripheral DMA controller and 160 Kbytes of on-chip SRAM. It offers seamless migration to
AT91CAP7 customizable MCUs for ARM7-plus-FPGA designs. It includes on-chip peripherals such as
USB 2.0 full speed device, SPI master and slave, two USARTs, three 16-bit timer counters, an 8-channel/
10-bit analog to digital converter, plus a full-functioned system controller including interrupt and power
control and supervisory functions.
The FPGA interface on the AT91CAP7E provides the FPGA with direct access to the AT91CAP7E’s
on-chip AHB and peripheral DMA controller. This architecture eliminates FPGA-induced bus contention,
off-loads MCU-to-FPGA communications from the CPU, and frees up the external bus interface for
external memory access.
Interfacing an ARM7-based MCU to an FPGA has traditionally been done through the external bus
interface (EBI) or programmable I/O. Either arrangement requires that the CPU transfer data to and from
the FPGA one word-at-a-time, basically stealing CPU cycles that should be conserved for processing and
limiting access to external memory during FPGA operations.
The FPGA interface on Atmel’s AT91CAP7E provides the FPGA with two AHB masters, four AHB slaves,
a special direct AHB slave interface to an external RAM through the FPGA, and a programmable ROM
that remaps the external RAM to emulate and debug the ROM code. Fourteen advanced peripheral bus
(APB) slaves, two full-duplex DMA channels and 32-bit programmable I/O may be hardware selected to
share I/O. An on-chip priority interrupt controller provides up to 13 encoded interrupts and two additional
un-encoded interrupts for DMA transfers.
CAPTM CUSTOMIZABLE MICROCONTROLLERS
AT91CAP7E
System Controller
Two-Wire Interface
USART
Serial Peripheral
Interface
CAN Controller
Synchronous Serial
Controller
Multi-Channel ADC
PWM Controller
Timer/Counter
Multimedia Card
Interface AC97 Controller
ARM926EJ-S
Processor
External Bus Interface
USB Host
USB HS Device
10/100 Ethernet
MAC
LCD Controller
Image Sensor
Interface
Metal Programmable
Block
(250K or 500K Gates)
Multi-Layer AHB Matrix
ROM
(32KB)
SRAM
(32KB)
Peripheral
Bridge
Multi-Channel
Peripheral DMA
APB
AT91CAP9
NAND Flash
SDRAM/DDRAM
Burst Cellular
RAM
Static RAM
Trans
ceiver
Trans
ceiver
8xRAM
(512x72bit)
12xDPR
(512x36bit)
Instr
Cache
(16KB)
Data
Cache
(16KB)
APB
System Controller
ICE
ARM7TDMI
PIT
Main
OSC
PLL
PMCWDT
PLL
6-layer AHB Matrix
JTAG
AIC
USARTADC
Timer
x3 USART
PIO
x32
SRAM
96KB
FPGA Interface
EBI
Static Mem.
CF
NAND Flash
SDRAM
ROM (256KB)
SPI
RTT
SHWDCGPBREG
POR
32K OSC
RC OSC
USB
FS
Device
SRAM
64KB
POR
AT91CAP7E
Peripheral DMA
Controller
AMBA Bridge

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© 2008 Atmel Corporation.
All rights reserved.
Atmel®, logo and combinations thereof,
and others, are registered trademarks,
CAPTM and others are trademarks of
Atmel Corporation or its subsidiaries.
ARM®, ARM7TDMI®,and others are
registered trademarks or trademarks
of ARM Ltd. Other terms and product
names may be trademarks of others.
REV.: 860/8543A-06/08/1K
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Atmel provides FPGA logic that decodes and encodes the bus traffic that flows between the FPGA and
the AT91CAP7E microcontroller. The logic blocks inside the FPGA are connected to the AT91CAP7E via
the AHB master and slave channels.
The AT91CAP7E is a standard microcontroller with an FPGA interface that makes the FPGA look and work
like it is on the internal bus on the MCU. Customers who are considering the AT91CAP7 customizable
MCU for their designs, frequently need a two-chip, no-NRE, FPGA-plus ARM7 solution as they are
gaining market momentum. The AT91CAP7E provides such a solution and offers an engineering-free
migration path to a lower cost, lower power customizable MCU when volume justifies it. The AT91CAP7E
is available in a 225 LFBGA package (13 x 13 x 1.4mm).
AT91CAP7 Customizable MCUs
Atmel’s AT91CAP7 customizable MCU is an ARM7-based microcontroller with a metal-programmable
(MP) block with 450K gates or the equivalent of 56K FPGA logic cells (LC). Any functionality that has
been implemented in an FPGA may be migrated directly to a CAP7 device with no special EDA tools
or customer-side engineering. Standard FPGA software tools are all that is necessary to implement
functions such as LCD controllers, DSP algorithms (e.g. GPS correlators, FFTs, FIR filters), and proprietary
customer IP. A AT91CAP7 implementation delivers as much as 8X better performance, consumes 98%
less static power, and costs about 30% less than the FPGA-plus-MCU implementation. The AT91CAP7
is available in multiple packages.
USB
PDC
256K ROM
POR
GPBR POR RTT PIT WDT PLL PLL
SHWDC OSC 32K AIC PMC Main OSC
ICE JTAG
AHB/APB Bridge
6-layer AHB Matrix
INTERFACE
FPGA
AHB/APB Bridge
CUSTOM MP
ARM7TDMI
Additional NON-AHB/APB Logic
FPGA
Seamless FPGA Interface
CAP7E to FPGA Interface
CAP7E
HZBT
AHBs
Dedicated
FPGA I/F
2 AHB Masters
4 AHB Slaves
14 APBs Slaves
2 PDC Channels
CAP7E-Ctrol
96KB SRAM
64KB SRAM
FPGA
INTERFACE
SRAM
SRAM
USB
FIFO
POR POR
ADC PLLB LFT
OSC
PLLA
Battery
USB Tranceiver
OSC32
ARM
ROM
ROM
MP
RAM
MP
RAM
FPGA Interface
EBI
Peripheral DMA
Controller
SPI
PIO
TIMERS
USART
USART
ADC
IRQ
SRAM
FPGA Interface