Atmel ATtiny25 User manual

Features
•High Performance, Low Power AVR® 8-Bit Microcontroller
•Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
•Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
•Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
•Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
•I/O and Packages
– Six Programmable I/O Lines
– 8-pin SOIC
– 20-pin QFN
•Operating Voltage
– 2.7 - 5.5V for ATtiny25/45/85
•Speed Grade
– ATtiny25/45/85: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
•Automotive Temperature Range
– -40°C to +125°C
•Low Power Consumption
– Active Mode:
• 1 MHz, 2.7V: 300µA
– Power-down Mode:
• 0.2µA at 2.7V
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25
ATtiny45
ATtiny85
Automotive
7598H–AVR–07/09

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1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
1
2
3
4
8
7
6
5
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
SOIC

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2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH SRAM
MCU CONTROL
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
SERIAL
UNIVERSAL
INTERFACE
TIMER/
COUNTER1
INSTRUCTION
DECODER
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PROGRAMMING
LOGIC
TIMING AND
CONTROL
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORT B DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
8-BIT DATABUS
Z
ADC /
ANALOG COMPARATOR
INTERRUPT
UNIT
DATA
EEPROM
CALIBRATED
OSCILLATORS
Y
X
RESET

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The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel®’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
2.2 Automotive Quality Grade
The ATtiny25/45/85 have been developed and manufactured according to the most stringent
requirements of the international standard ISO-TS-16949. This data sheet contains limit values
extracted from the results of extensive characterization (Temperature and Voltage). The quality
and reliability of the ATtiny25/45/85 have been verified during regular product qualification as
per AEC-Q100 grade 1.
As indicated in the ordering information paragraph, the products are available in three different
temperature grades, but with equivalent quality and reliability objectives. Different temperature
identifiers have been defined as listed in Table 2-1.
Table 2-1. Temperature Grade Identification for Automotive Products
Temperature
Temperature
Identifier Comments
-40 ; +85 T Similar to Industrial Temperature Grade but with Automotive
Quality
-40 ; +105 T1 Reduced Automotive Temperature Range
-40 ; +125 Z Full AutomotiveTemperature Range

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2.3 Pin Descriptions
2.3.1 VCC
Supply voltage.
2.3.2 GND
Ground.
2.3.3 Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on
page 54.
2.3.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page
37. Shorter pulses are not guaranteed to generate a reset.
3. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
4. AVR CPU Core
4.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.

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4.2 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n

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The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions are 16-bits wide. There are
also 32-bit instructions.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
4.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
4.4 Status Register
The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit 76543210
ITHSVNZCSREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

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• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.

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4.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte

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4.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3.
Figure 4-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.6 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28(0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
Bit 151413121110 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
InitialValue00000000
10011111