Atmel AT89C5131A-L User manual

Rev. 4338F–USB–08/07
Features
• 80C52X2 Core (6 Clocks per Instruction)
– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART)
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
• 16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
• 3-KbyteFlash EEPROM for Bootloader
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
• 1-Kbyte EEPROM Data (
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
• On-chip Expanded RAM (ERAM): 1024 Bytes
• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
• USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz DPLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
• 5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
• Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to
6s at 4 MHz
• Keyboard Interrupt Interface on Port P1 (8 Bits)
• TWI (Two Wire Interface) 400Kbit/s
• SPI Interface (Master/Slave Mode)
• 34 I/O Pins
• 4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
• 4-level Priority Interrupt System (11 sources)
• Idle and Power-down Modes
• 0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
• Industrial Temperature Range
• Low Voltage Range Supply: 2.7V to 3.6V (3.0V to 3.6V required for USB)
• Packages: SO28, PLCC52, VQFP64
8-bit Flash
Microcontroller
with Full Speed
USB Device
AT89C5131A-L

2
AT89C5131A-L
4338F–USB–08/07
Description AT89C5131A-L is a high-performance Flash version of the 80C51 single-chip 8-bit
microcontrollers with full speed USB functions.
AT89C5131A-L features a full-speed USB module compatible with the USB specifica-
tions Version 1.1 and 2.0. This module integrates the USB transceivers with a 3.3V
voltage regulator and the Serial Interface Engine (SIE) with Digital Phase Locked Loop
and 48 MHz clock recovery. USB Event detection logic (Reset and Suspend/Resume)
and FIFO buffers supporting the mandatory control Endpoint (EP0) and up to 6 versatile
Endpoints (EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part
of the USB module.
AT89C5131A-L retains the features of the Atmel 80C52 with extended Flash capacity
(32-Kbyte), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit
timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip
oscillator.
In addition, AT89C5131A-L has an on-chip expanded RAM of 1024 bytes (ERAM), a
dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA),
up to 4 programmable LED current sources, a programmable hardware watchdog and a
power-on reset.
AT89C5131A-L has two software-selectable modes of reduced activity for further reduc-
tion in power consumption. In the idle mode the CPU is frozen while the timers, the
serial ports and the interrupt system are still operating. In the power-down mode the
RAM is saved, the peripheral clock is frozen, but the device has full wake-up capability
through USB events or external interrupts.

3
AT89C5131A-L
4338F–USB–08/07
Block Diagram
Notes: 1. Alternate function of Port 1
2. Alternate function of Port 3
3. Alternate function of Port 4
Timer 0 INT
RAM
256x8
T0 T1
RxD TxD
WR
RD
EA
PSEN
ALE
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1 P2 P3
ERAM
1Kx8
PCA
RST
Watch
Dog
CEX ECI
VSS
VDD
(2)(2) (1)(1)
Timer2
T2EX
T2
(1) (1)
Port 4
P4
32Kx8 Flash
+
BRG
USB
D - D +
VREF
Regu-
Key
Board
KIN
lator
AVSS
EEPROM
4Kx8
SPI
MISO MOSI SCK
(1) (1) (1)
SS
(1)
AVDD
TWI
SCL SDA

4
AT89C5131A-L
4338F–USB–08/07
Pinout Description
Pinout
Figure 1. AT89C5131A-L 52-pin PLCC Pinout
21 22 26252423 292827 30 31
5 4 3 2 16 52 51 50 49 48
8
9
10
11
12
13
14
15
16
17
18
46
45
44
43
42
41
40
39
38
37
36
PLCC52
7 47
19
20 32 33
34
35
P1.1/T2EX/KIN1/SS
P1.0/T2/KIN0
P0.6/AD6
ALE
P0.7/AD7
EA
PSEN
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3 P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
PLLF
P3.0/RxD
AVSS
P2.6/A14
XTAL1
P2.5/A13
P0.3/AD3
P0.5/AD5
P0.4/AD4
VREF
P0.2/AD2
P0.0/AD0
P0.1/AD1
AVDD
NC
P3.2/INT0
P3.6/WR/LED2
XTAL2
RST
P3.1/TxD
P3.3/INT1/LED0
P3.7/RD/LED3
D-
P2.0/A8 P2.1/A9
P2.2/A10
P2.3/A11
VSS
P2.4/A12
P4.1/SDA
D+
P4.0/SCL
P1.2/ECI/KIN2 P1.4/CEX1/KIN4
P3.4/T0
P3.5/T1/LED1
NC
NC
VDD
NC
P2.7/A15

5
AT89C5131A-L
4338F–USB–08/07
Figure 2. AT89C5131A-L 64-pin VQFP Pinout
Figure 3. AT89C5131A-L 28-pin SO Pinout
17 18 22212019 252423 26 27
62 61 60 59 5863 57 56 55 54 53
1
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
VQFP64
64 52
12
13
28 29
36
37
51 50 49
35
33
34
14
15
16
30
3132
P1.1/T2EX/KIN1/SS
ALE
EA
PSEN
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO P1.6/CEX3/KIN6/SCK
P2.7/A15
P2.6/A14
P4.1/SDA
P1.2/ECI/KIN2
P1.4/CEX1/KIN4 P1.0/T2/KIN0
PLLF
NC
XTAL2 RST
P3.7/RD/LED3
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NC
NC
P3.0/RxD
NC
VREF
P0.0/AD0
AVSS
P3.2/INT0
P3.6/WR/LED2
P3.1/TxD
P3.3/INT1/LED0
VSS
P3.4/T0
P3.5/T1/LED1
NC
P0.6/AD6
P0.7/AD7
P2.5/A13
P0.3/AD3
P0.5/AD5
P0.4/AD4
P0.2/AD2
P0.1/AD1
D-
D+
P4.0/SCL
XTAL1
AVDD
NC
NC
NC NC NC
NC
NC
NC
NC
NC
NC
VDD
P1.1/T2EX/KIN1/SS
PLLF
P3.0/RxD
P1.0/T2/KIN0
AVSS
VDD
XTAL1
XTAL2
P3.2/INT0
P3.5/T1/LED1
P3.6/WR/LED2
P3.7/RD/LED3
D-
P1.4/CEX1/KIN4
VSS
D+
P1.2/ECI/KIN2
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
RST
P1.6/CEX3/KIN6/SCK
P1.7/CEX4/KIN7/MOSI
P4.0/SCL
VREF P3.1/TxD
P3.4/T0
1
2
3
4
5
6
7
8
9
10
11
12
28
27
26
25
24
23
22
21
20
19
18
17
SO28
13
14
16
15
P4.1/SDA
P3.3/INT1/LED0

6
AT89C5131A-L
4338F–USB–08/07
Signals All the AT89C5131A-L signals are detailed by functionality on Table 1 through Table 12.
Table 1. Keypad Interface Signal Description
Table 2. Programmable Counter Array Signal Description
Table 3. Serial I/O Signal Description
Signal
Name Type Description
Alternate
Function
KIN[7:0) I
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt if enabled. Held line is reported in the KBCON register.
P1[7:0]
Signal
Name Type Description
Alternate
Function
ECI I External Clock Input P1.2
CEX[4:0] I/O
Capture External Input
Compare External Output
P1.3
P1.4
P1.5
P1.6
P1.7
Signal
Name Type Description
Alternate
Function
RxD I Serial Input
The serial input for Extended UART. P3.0
TxD O Serial Output
The serial output for Extended UART. P3.1
Table 4. Timer 0, Timer 1 and Timer 2 Signal Description
Signal
Name Type Description
Alternate
Function
INT0 I
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GATE0
bit in TCON register.
External Interrupt 0
INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits
IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by
a low level on INT0.
P3.2
INT1 I
Timer 1 Gate Input
INT1 serves as external run control for Timer 1, when selected by GATE1
bit in TCON register.
External Interrupt 1
INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits
IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by
a low level on INT1.
P3.3

7
AT89C5131A-L
4338F–USB–08/07
Table 5. LED Signal Description
Table 6. TWI Signal Description
Table 7. SPI Signal Description
T0 I
Timer Counter 0 External Clock Input
When Timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
T1 I
Timer/Counter 1 External Clock Input
When Timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
P3.5
T2 I
O
Timer/Counter 2 External Clock Input
Timer/Counter 2 Clock Output P1.0
T2EX I Timer/Counter 2 Reload/Capture/Direction Control Input P1.1
Signal
Name Type Description
Alternate
Function
LED[3:0] O
Direct Drive LED Output
These pins can be directly connected to the Cathode of standard LEDs
without external current limiting resistors. The typical current of each
output can be programmed by software to 2, 6 or 10 mA. Several outputs
can be connected together to get higher drive capabilities.
P3.3
P3.5
P3.6
P3.7
Signal
Name Type Description
Alternate
Function
SCL I/O
SCL: TWI Serial Clock
SCL output the serial clock to slave peripherals.
SCL input the serial clock from master.
P4.0
SDA I/O SDA: TWI Serial Data
SCL is the bidirectional TWI data line. P4.1
Signal
Name Type Description
Alternate
Function
SS I/O SS: SPI Slave Select P1.1
MISO I/O
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave
peripheral. When SPI is in slave mode, MISO outputs data to the master
controller.
P1.5
SCK I/O SCK: SPI Serial Clock
SCK outputs clock to the slave peripheral or receive clock from the master P1.6
MOSI I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master controller
P1.7
Table 4. Timer 0, Timer 1 and Timer 2 Signal Description (Continued)
Signal
Name Type Description
Alternate
Function

8
AT89C5131A-L
4338F–USB–08/07
Table 8. Ports Signal Description
Table 9. Clock Signal Description
Signal
Name Type Description Alternate Function
P0[7:0] I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0
pins that have 1s written to them float and can be used
as high impedance inputs. To avoid any parasitic current
consumption, Floating P0 inputs must be pulled to VDD or
VSS.
AD[7:0]
P1[7:0] I/O Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
KIN[7:0]
T2
T2EX
ECI
CEX[4:0]
P2[7:0] I/O Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups. A[15:8]
P3[7:0] I/O Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
LED[3:0]
RxD
TxD
INT0
INT1
T0
T1
WR
RD
P4[1:0] I/O Port 4
P4 is an 2-bit open port.
SCL
SDA
Signal
Name Type Description
Alternate
Function
XTAL1 I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, its output is connected to this pin.
-
XTAL2 O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
-
PLLF I
PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter (See Figure 4 on page
11 ).
-

9
AT89C5131A-L
4338F–USB–08/07
Table 10. USB Signal Description
Table 11. System Signal Description
Signal
Name Type Description
Alternate
Function
D+ I/O USB Data + signal
Set to high level under reset. -
D- I/O USB Data - signal
Set to low level under reset. -
VREF O USB Reference Voltage
Connect this pin to D+ using a 1.5 kΩresistor to use the Detach function. -
Signal
Name Type Description
Alternate
Function
AD[7:0] I/O Multiplexed Address/Data LSB for external access
Data LSB for Slave port access (used for 8-bit and 16-bit modes) P0[7:0]
A[15:8] I/O Address Bus MSB for external access
Data MSB for Slave port access (used for 16-bit mode only) P2[7:0]
RD I/O
Read Signal
Read signal asserted during external data memory read operation.
Control input for slave port read access cycles.
P3.7
WR I/O
Write Signal
Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
P3.6
RST I/O
Reset
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns
the chip to normal operation.
This pin is set to 0 for at least 12 oscillator periods when an internal reset
occurs (hardware watchdog or Power monitor).
-
ALE O
Address Latch Enable Output
The falling edge of ALE strobes the address into external latch. This signal
is active only when reading or writing external memory using MOVX
instructions.
-
PSEN O
Program Strobe Enable / Hardware conditions Input for ISP
Used as input under reset to detect external hardware conditions of ISP
mode
-
EA I
External Access Enable
This pin must be held low to force the device to fetch code from external
program memory starting at address 0000h. It is latched during reset and
cannot be dynamically changed during operation.
-

10
AT89C5131A-L
4338F–USB–08/07
Table 12. Power Signal Description
Signal
Name Type Description
Alternate
Function
AVSS GND Alternate Ground
AVSS is used to supply the on-chip PLL and the USB PAD. -
AVDD PWR Alternate Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD. -
VSS GND Digital Ground
VSS is used to supply the buffer ring and the digital core. -
VDD PWR
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard
versions or the digital core of the Low Power versions.
-
VREF O
USB pull-up Controlled Output
VREF is used to control the USB D+ 1.5 kΩpull up.
The Vref output is in high impedance when the bit DETACH is set in the
USBCON register.
-

11
AT89C5131A-L
4338F–USB–08/07
Typical Application
Recommended External components
All the external components described in the figure below must be implemented as
close as possible from the microcontroller package.
The following figure represents the typical wiring schematic.
Figure 4. Typical Application
VSS
XTAL1
XTAL2
Q
22pF
22pF
VSS
PLLF
100R
10nF
2.2nF
VSS
VSS
AVSS
VSS
D-
D+
27R
27R
VRef
1.5K
USB
D+
D-
VBUS
GND
VSS
VDD
AVDD
VDD
4.7µF
VSS
100nF
VSS
100nF
VSS
AT89C5131A-L

12
AT89C5131A-L
4338F–USB–08/07
PCB Recommandations
Figure 5. USB Pads
Figure 6. USB PLL
D+
VRef
D-
USB Connector
Wires must be routed in Parallel and
Components must be
If possible, isolate D+ and D- signals from other signals
with ground wires
must be as short as possible
close to the
microcontroller
PLLFAVss
Components must be
Isolate filter components
with a ground wire
microcontroller
close to the
C2 C1
R

13
AT89C5131A-L
4338F–USB–08/07
Clock Controller
Introduction The AT89C5131A-L clock controller is based on an on-chip oscillator feeding an on-chip
Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are gen-
erated by this controller.
The AT89C5131A-L X1 and X2 pins are the input and the output of a single-stage on-
chip inverter (see Figure 7) that can be configured with off-chip components as a Pierce
oscillator (see Figure 8). Value of capacitors and crystal characteristics are detailed in
the section “DC Characteristics”.
The X1 pin can also be used as input for an external 48 MHz clock.
The clock controller outputs three different clocks as shown in Figure 7:
• a clock for the CPU core
• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port
sampling clocks
• a clock for the USB controller
These clocks are enabled or disabled depending on the power reduction mode as
detailed in Section “Power Management”, page 152.
Figure 7. Oscillator Block Diagram
Oscillator Two clock sources are available for CPU:
• Crystal oscillator on X1 and X2 pins: Up to 32 MHz
• External 48 MHz clock on X1 pin
In order to optimize the power consumption, the oscillator inverter is inactive when the
PLL output is not selected for the USB device.
X1
X2
PD
PCON.1
IDL
PCON.0
Peripheral
CPU Core
0
1
X2
CKCON.0
÷ 2
Clock
Clock
EXT48
PLLCON.2
0
1
PLL
USB
Clock

14
AT89C5131A-L
4338F–USB–08/07
Figure 8. Crystal Connection
PLL
PLL Description The AT89C5131A-L PLL is used to generate internal high frequency clock (the USB
Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL
clock is used to generate the USB interface clock. Figure 9 shows the internal structure
of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Figure 9) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figu re 10). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
REF
pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 9. PLL Block Diagram and Symbol
Figure 10. PLL Filter Connection
The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.
VSS
X1
X2
Q
C1
C2
PLLEN
PLLCON.1
N3:0
N divider
R divider
VCO USB Clock
USBclk OSCclk R 1+( )×
N 1+
-----------------------------------------------=
OSC
CLOCK
PFLD
PLOCK
PLLCON.0
PLLF
CHP Vref
Up
Down
R3:0
USB
CLOCK
USB Clock Symbol
VSS
PLLF
R
C1
C2
VSS

15
AT89C5131A-L
4338F–USB–08/07
PLL Programming The PLL is programmed using the flow shown in Figure 11. As soon as clock generation
is enabled user must wait until the lock indicator is set to ensure the clock output is
stable.
Figure 11. PLL Programming Flow
Divider Values To generate a 48 MHz clock using the PLL, the divider values have to be configured fol-
lowing the oscillator frequency. The typical divider values are shown in Table 13.
Table 13. Typical Divider Values
PLL
Programming
Configure Dividers
N3:0 = xxxxb
R3:0 = xxxxb
Enable PLL
PLLEN = 1
PLL Locked?
LOCK = 1?
Oscillator Frequency R+1 N+1 PLLDIV
3 MHz 16 1 F0h
6 MHz 8 1 70h
8 MHz 6 1 50h
12 MHz 4 1 30h
16 MHz 3 1 20h
18 MHz 8 3 72h
20 MHz 12 5 B4h
24 MHz 2 1 10h
32 MHz 3 2 21h
40 MHz 12 10 B9h

16
AT89C5131A-L
4338F–USB–08/07
Registers Table 14. CKCON0 (S:8Fh)
Clock Control Register 0
Reset Value = 0000 0000b
76543210
TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit Number
Bit
Mnemonic Description
7 TWIX2
TWI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
6 WDX2
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5 PCAX2
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4 SIX2
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3 T2X2
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2 T1X2
Timer1 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
1 T0X2
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
0 X2
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER =
FOSC / 2).
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).

17
AT89C5131A-L
4338F–USB–08/07
Table 15. CKCON1 (S:AFh)
Clock Control Register 1
Reset Value = 0000 0000b
Table 16. PLLCON (S:A3h)
PLL Control Register
Reset Value = 0000 0000b
Table 17. PLLDIV (S:A4h)
PLL Divider Register
Reset Value = 0000 0000
76543210
- - - - - - - SPIX2
Bit Number
Bit
Mnemonic Description
7-1 - Reserved
The value read from this bit is always 0. Do not set this bit.
0 SPIX2
SPI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
76543210
- - - - - EXT48 PLLEN PLOCK
Bit Number
Bit
Mnemonic Description
7-3 - Reserved
The value read from this bit is always 0. Do not set this bit.
2 EXT48
External 48 MHz Enable Bit
Set this bit to bypass the PLL and disable the crystal oscillator.
Clear this bit to select the PLL output as USB clock and to enable the crystal
oscillator.
1 PLLEN
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
0 PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
76543210
R3 R2 R1 R0 N3 N2 N1 N0
Bit Number
Bit
Mnemonic Description
7-4 R3:0 PLL R Divider Bits
3-0 N3:0 PLL N Divider Bits

18
AT89C5131A-L
4338F–USB–08/07
SFR Mapping The Special Function Registers (SFRs) of the AT89C5131A-L fall into the following
categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP
• I/O port registers: P0, P1, P2, P3, P4
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH,
CCAPxH, CCAPxL (x: 0 to 4)
• Power and clock control registers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• LED register: LEDCON
• Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR
• Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT
• USB registers: Uxxx (17 registers)
• PLL registers: PLLCON, PLLDIV
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Flash register: FCON (FCON access is reserved for the Flash API and ISP
software)
• EEPROM register: EECON
• Others: AUXR, AUXR1, CKCON0, CKCON1

19
AT89C5131A-L
4338F–USB–08/07
The table below shows all SFRs with their address and their reset value.
Note: 1. FCON access is reserved for the Flash API and ISP software.
Table 18. SFR Descriptions
Bit
Addressable Non-Bit Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h UEPINT
0000 0000
CH
0000 0000
CCAP0H
XXXX XXXX
CCAP1H
XXXX XXXX
CCAP2H
XXXX XXXX
CCAP3H
XXXX XXXX
CCAP4H
XXXX XXXX FFh
F0h B
0000 0000
LEDCON
0000 0000 F7h
E8h CL
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAP2L
XXXX XXXX
CCAP3L
XXXX XXXX
CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000
UBYCTLX
0000 0000
UBYCTHX
0000 0000 E7h
D8h CCON
00X0 0000
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000 DFh
D0h PSW
0000 0000
FCON (1)
XXXX 0000
EECON
XXXX XX00
UEPCONX
1000 0000
UEPRST
0000 0000 D7h
C8h T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
UEPSTAX
0000 0000
UEPDATX
0000 0000 CFh
C0h P4
XXXX 1111
UEPIEN
0000 0000
SPCON
0001 0100
SPSTA
0000 0000
SPDAT
XXXX XXXX
USBADDR
1000 0000
UEPNUM
0000 0000 C7h
B8h IPL0
X000 000
SADEN
0000 0000
UFNUML
0000 0000
UFNUMH
0000 0000
USBCON
0000 0000
USBINT
0000 0000
USBIEN
0000 0000 BFh
B0h P3
1111 1111
IEN1
X0XX X000
IPL1
X0XX X000
IPH1
X0XX X000
IPH0
X000 0000 B7h
A8h IEN0
0000 0000
SADDR
0000 0000
CKCON1
0000 0000 AFh
A0h P2
1111 1111
AUXR1
XXXX X0X0
PLLCON
XXXX XX00
PLLDIV
0000 0000
WDTRST
XXXX XXXX
WDTPRG
XXXX X000 A7h
98h SCON
0000 0000
SBUF
XXXX XXXX
BRL
0000 0000
BDRCON
XXX0 0000
KBLS
0000 0000
KBE
0000 0000
KBF
0000 0000 9Fh
90h P1
1111 1111
SSCON
0000 0000
SSCS
1111 1000
SSDAT
1111 1111
SSADR
1111 1110 97h
88h TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
XX0X 0000
CKCON0
0000 0000 8Fh
80h P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Reserved

20
AT89C5131A-L
4338F–USB–08/07
The Special Function Registers (SFRs) of the AT89C5131 fall into the following
categories:
Table 19. C51 Core SFRs
Table 20. I/O Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status
Word
SP 81h Stack Pointer
LSB of SPX
DPL 82h
Data Pointer
Low byte
LSB of DPTR
DPH 83h
Data Pointer
High byte
MSB of DPTR
Mnemonic Add Name 7 6 5 4 3 2 1 0
P0 80h Port 0
P1 90h Port 1
P2 A0h Port 2
P3 B0h Port 3
P4 C0h Port 4 (2bits)