Atmel AT90PWM2 User manual

Features
•High Performance, Low Power AVR ® 8-bit Microcontroller
•Advanced RISC Architecture
– 129 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
•Data and Non-Volatile Program Memory
– 8K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
•In-System Programming by On-chip Boot Program
•True Read-While-Write Operation
– 512 Bytes of In-System Programmable EEPROM
•Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
•On Chip Debug Interface (debugWIRE)
•Peripheral Features
– Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit
Resolution Enhancement
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Event Driven PFC Implementation
• Less than 25 Hz Step Width at 150 kHz Output Frequency
• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture
Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– Programmable Serial USART
• Standard UART mode
• 16/17 bit Biphase Mode for DALI Communications
– Master/Slave SPI Serial Interface
– 10-bit ADC
• Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs
• Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)
• Internal Reference Voltage
– 10-bit DAC
– Two or three Analog Comparator with Resistor-Array to Adjust Comparison
Voltage
– 4 External Interrupts
– Programmable Watchdog Timer with Separate On-Chip Oscillator
•Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– Flag Array in Bit-programmable I/O Space (4 bytes) 4317I–AVR–01/08
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90PWM2
AT90PWM3
AT90PWM2B
AT90PWM3B

24317I–AVR–01/08
AT90PWM2/3/2B/3B
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator ( 8 MHz)
– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)
•Operating Voltage: 2.7V - 5.5V
•Extended Operating Temperature:
– -40°C to +105°
1. History
This datasheet deals with product characteristics of AT90PW2 and AT90WM3. It will be updated
as soon as characterization will be done.
2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max val-
ues will be available after the device is characterized.
Product Package 12 bit PWM with deadtime ADC Input ADC Diff Analog Compar Application
AT90PWM2
AT90PWM2B SO24 2 x 2 8 1 2 One fluorescent ballast
AT90PWM3
AT90PWM3B SO32,
QFN32 3 x 2 11 2 3 HID ballast, fluorescent ballast, Motor control
Product Revision
AT90PWM2
AT90PWM3 First revision of parts, only for running production.
AT90PWM2B
AT90PWM3B
Second revision of parts, for all new developments.
The major changes are :
• complement the PSCOUT01, PSCOUT11, PSCOUT21 polarity in
centered mode - See “PSCn0 & PSCn1 Basic Waveforms in Center
Aligned Mode” on page 139.
• Add the PSC software triggering capture - See “PSC 0 Input Capture
Register – PICR0H and PICR0L” on page 170.
• Add bits to read the PSC output activity - See “PSC0 Interrupt Flag
Register – PIFR0” on page 172.
• Add some clock configurations - See “Device Clocking Options Select
AT90PWM2B/3B” on page 31.
• Change Amplifier Synchonization - See “Amplifier” on page 252. and
See “” on page 255.
• Correction of the Errata - See “Errata” on page 350.

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4317I–AVR–01/08
AT90PWM2/3/2B/3B
3. Pin Configurations
Figure 3-1. SOIC 24-pin Package
Figure 3-2. SOIC 32-pin Package
AT90PWM2/2B
SOIC24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
(PSCOUT00/XCK/SS_A) PD0
(RESET/OCD) PE0
(PSCIN0/CLKO) PD1
(PSCIN2/OC1A/MISO_A) PD2
(TXD/DALI/OC0A/SS/MOSI_A) PD3
VCC
GND
(MISO/PSCOUT20) PB0
(MOSI/PSCOUT21) PB1
(OC0B/XTAL1) PE1
(ADC0/XTAL2) PE2
ADC1/RXD/DALI/ICP1A/SCK_A) PD4
PB7(ADC4/PSCOUT01/SCK)
PB6 (ADC7/ICP1B)
PB5 (ADC6/INT2)
PB4 (AMP0+)
PB3 (AMP0-)
AREF
GND
AVCC
PB2 (ADC5/INT1)
PD7 (ACMP0)
PD6 (ADC3/ACMPM/INT0)
PD5 (ADC2/ACMP2)
AT90PWM3/3B
SOIC 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(PSCOUT00/XCK/SS_A) PD0
(INT3/PSCOUT10) PC0
(RESET/OCD) PE0
(PSCIN0/CLKO) PD1
(PSCIN2/OC1A/MISO_A) PD2
(TXD/DALI/OC0A/SS/MOSI_A) PD3
(PSCIN1/OC1B) PC1
VCC
GND
(T0/PSCOUT22) PC2
(T1/PSCOUT23) PC3
(MISO/PSCOUT20) PB0
(MOSI/PSCOUT21) PB1
(OC0B/XTAL1) PE1
(ADC0/XTAL2) PE2
(ADC1/RXD/DALI/ICP1A/SCK_A) PD4
PB7(ADC4/PSCOUT01/SCK)
PB6 (ADC7/PSCOUT11/ICP1B)
PB5 (ADC6/INT2)
PC7 (D2A)
PB4 (AMP0+)
PB3 (AMP0-)
PC6 (ADC10/ACMP1)
AREF
GND
AVCC
PC5 (ADC9/AMP1+)
PC4 (ADC8/AMP1-)
PB2 (ADC5/INT1)
PD7 (ACMP0)
PD6 (ADC3/ACMPM/INT0)
PD5 (ADC2/ACMP2)

44317I–AVR–01/08
AT90PWM2/3/2B/3B
Figure 3-3. QFN32 (7*7 mm) Package.
3.1 Pin Descriptions
:
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(PSCIN2/OC1A/MISO_A) PD2
(
TXD/DALI/OC0A/SS/MOSI_A) PD3
(PSCIN1/OC1B) PC1
VCC
GND
(T0/PSCOUT22) PC2
(T1/PSCOUT23) PC3
(MISO/PSCOUT20) PB0
PB4 (AMP0+)
PB3 (AMP0-)
PC6 (ADC10/ACMP
1)
AREF
AGND
AVCC
PC5 (ADC9/AMP1+)
PC4 (ADC8/AMP1-)
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
(MOSI/PSCOUT21) PB1
(OC0B/XTAL1) PE1
(ADC0/XTAL2) PE2
(
ADC1/RXD/DALI/ICP1_A/SCK_A) PD4
(ADC2/ACMP2 ) PD5
(ADC3/ACMPM/INT0) PD6
(ACMP0) PD7
(ADC5/INT1) PB2
PD1
(PSCIN0/CLKO)
PE0
(RESET/OCD)
PC0
(INT3/PSCOUT10)
PD0
(PSCOUT00/XCK/SS_A)
PB7 (ADC4/PSCOUT01/SCK) PB6 (ADC7/PSCOUT11/ICP1B) PB5 (ADC6/INT2) PC7 (D2A)
AT90PWM3/3B QFN 32
Table 3-1. Pin out description
S024 Pin
Number SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function
795GNDPowerGround: 0V reference
18 24 20 AGND Power Analog Ground: 0V reference for analog part

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4317I–AVR–01/08
AT90PWM2/3/2B/3B
6 8 4 VCC power Power Supply:
17 23 19 AVCC Power Analog Power Supply: This is the power supply voltage for analog
part
For a normal use this pin must be connected.
19 25 21 AREF Power Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by
external analog
8128PBOI/O
MISO (SPI Master In Slave Out)
PSCOUT20 output
9139PB1I/O
MOSI (SPI Master Out Slave In)
PSCOUT21 output
16 20 16 PB2 I/O ADC5 (Analog Input Channel5 )
INT1
20 27 23 PB3 I/O AMP0- (Analog Differential Amplifier 0 Input Channel )
21 28 24 PB4 I/O AMP0+ (Analog Differential Amplifier 0 Input Channel )
22 30 26 PB5 I/O ADC6 (Analog Input Channel 6)
INT 2
23 31 27 PB6 I/O ADC7 (Analog Input Channel 7) ICP1B (Timer 1 input capture alternate input)
PSCOUT11 output (see note 1)
24 32 28 PB7 I/O PSCOUT01 output ADC4 (Analog Input Channel 4)
SCK (SPI Clock)
NA
230PC0I/O
PSCOUT10 output (see note 1)
INT3
73PC1I/O
PSCIN1 (PSC 1 Digital Input)
OC1B (Timer 1 Output Compare B)
10 6 PC2 I/O T0 (Timer 0 clock input)
PSCOUT22 output
11 7 PC3 I/O T1 (Timer 1 clock input)
PSCOUT23 output
21 17 PC4 I/O ADC8 (Analog Input Channel 8)
AMP1- (Analog Differential Amplifier 1 Input Channel )
22 18 PC5 I/O ADC9 (Analog Input Channel 9)
AMP1+ (Analog Differential Amplifier 1 Input Channel )
26 22 PC6 I/O ADC10 (Analog Input Channel 10)
ACMP1 (Analog Comparator 1 Positive Input )
29 25 PC7 I/O D2A : DAC output
Table 3-1. Pin out description (Continued)
S024 Pin
Number SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function

64317I–AVR–01/08
AT90PWM2/3/2B/3B
1. PSCOUT10 & PSCOUT11 are not present on 24 pins package
4. Overview The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
1129PD0I/O
PSCOUT00 output
XCK (UART Transfer Clock)
SS_A (Alternate SPI Slave Select)
3432PD1I/O
PSCIN0 (PSC 0 Digital Input )
CLKO (System Clock Output)
451PD2I/O
PSCIN2 (PSC 2 Digital Input)
OC1A (Timer 1 Output Compare A)
MISO_A (Programming & alternate SPI Master In Slave Out)
562PD3I/O
TXD (Dali/UART Tx data)
OC0A (Timer 0 Output Compare A)
SS (SPI Slave Select)
MOSI_A (Programming & alternate Master Out SPI Slave In)
12 16 12 PD4 I/O
ADC1 (Analog Input Channel 1)
RXD (Dali/UART Rx data)
ICP1A (Timer 1 input capture)
SCK_A (Programming & alternate SPI Clock)
13 17 13 PD5 I/O ADC2 (Analog Input Channel 2)
ACMP2 (Analog Comparator 2 Positive Input )
14 18 14 PD6 I/O ADC3 (Analog Input Channel 3 ) ACMPM reference for analog comparators
INT0
15 19 15 PD7 I/O ACMP0 (Analog Comparator 0 Positive Input )
2 3 31 PE0 I/O or I RESET (Reset Input)
OCD (On Chip Debug I/O)
10 14 10 PE1 I/O XTAL1: XTAL Input
OC0B (Timer 0 Output Compare B)
11 15 11 PE2 I/O XTAL2: XTAL OuTput
ADC0 (Analog Input Channel 0)
Table 3-1. Pin out description (Continued)
S024 Pin
Number SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function

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4317I–AVR–01/08
AT90PWM2/3/2B/3B
4.1 Block Diagram
Figure 4-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general
purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex-
ible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11-
channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a
programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug
system and four software selectable power saving modes.
8Kx8 Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
512 bytes
Data Bus 8-bit
Data
SRAM
512 bytes
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
3 Analog
Comparators
DAC
ADC
PSC 2/1/0
Timer 1
Timer 0
DALI USART

84317I–AVR–01/08
AT90PWM2/3/2B/3B
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt
system to continue functioning. The Power-down mode saves the register contents but freezes
the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The
ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switch-
ing noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90PWM2/3 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The AT90PWM2/3 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
4.2 Pin Descriptions
4.2.1 VCC Digital supply voltage.
4.2.2 GND Ground.
4.2.3 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed
on page 69.
4.2.4 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C is not available on 24 pins package.
Port C also serves the functions of special features of the AT90PWM2/2B/3/3B as listed on page
72.

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4317I–AVR–01/08
AT90PWM2/3/2B/3B
4.2.5 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed
on page 74.
4.2.6 Port E (PE2..0) RESET/ XTAL1/
XTAL2 Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-
acteristics of PE0 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 9-1 on page 47. Shorter pulses are not guaranteed
to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
The various special features of Port E are elaborated in “Alternate Functions of Port E” on page
77 and “Clock Systems and their Distribution” on page 29.
4.2.7 AVCC AVCC is the supply voltage pin for the A/D Converter. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-
pass filter.
4.2.8 AREF This is the analog reference pin for the A/D Converter.
4.3 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.

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4317I–AVR–01/08
AT90PWM2/3/2B/3B
5. AVR CPU Core
5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2 Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n