Cypress Semiconductor AutoStore STK14CA8 User manual

STK14CA8
128Kx8 AutoStore™nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document Number: 001-51592 Rev. ** Revised March 04, 2009
Features
■ 25, 35, 45 ns Read Access and Read/Write Cycle Time
■ Unlimited Read/Write Endurance
■ Automatic Nonvolatile STORE on Power Loss
■ Nonvolatile STORE Under Hardware or Software Control
■ Automatic RECALL to SRAM on Power Up
■ Unlimited RECALL Cycles
■ 200K STORE Cycles
■ 20-Year Nonvolatile Data Retention
■ Single 3.0V + 20%, -10% Operation
■ Commercial and Industrial Temperatures
■ Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
ROW DECODERINPUT BUFFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT A
15
– A
0
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
0
A
1
A
2
A
3
A
4
A
10
A
11
V
CC
V
CAP
Logic Block Diagram
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STK14CA8
Document Number: 001-51592 Rev. ** Page 2 of 16
Pinouts
Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC
Figure 3. Relative PCB Area Usage
[1]
Pin Descriptions
VSS
A14
A12
A7
A6
DQ0
DQ1
VCC
DQ2
A3
A2
A1
VCAP
A13
A8
A9
A11
A10
DQ7
DQ6
VSS
A0
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC 23
24
A5
NC
NC
NC
NC
NC
NC
A4
48
47
46
45
VCC
HSB
NC
NC
W
NC
NC
DQ5
DQ3
DQ4
G
E
A16 A15
Note
1. See Package Diagrams on page 15 for detailed package size specifications.
A
16
A
14
A
12
A
7
DQ
0
DQ
1
DQ
2
A
4
A
2
A
1
V
CAP
A
13
A
8
A
9
A
11
A
10
DQ
7
DQ
6
V
SS
A
0
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
6
A
3
A
5
32
31
30
29
V
CC
HSB
W
DQ
5
DQ
3
DQ
4
G
E
A
15
Pin Name I/O Description
A
16
-A
0
Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
DQ
7
-DQ
0
I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
EInput Chip Enable: The active low E input selects the device.
WInput Write Enable: The active low W allows to write the data on the DQ pins to the address location
latched by the falling edge of E.
GInput Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high causes the DQ pins to tri-state.
V
CC
Power Supply Power: 3.0V, +20%, -10%.
HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).
V
CAP
Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
V
SS
Power Supply Ground.
NC No Connect Unlabeled pins have no internal connections.
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STK14CA8
Document Number: 001-51592 Rev. ** Page 3 of 16
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
SS
...........–0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB......................–0.5V to (V
CC
+ 0.5V)
Temperature under Bias............................... –55°C to 125°C
Junction Temperature................................... –55°C to 140°C
Storage Temperature.................................... –65°C to 150°C
Power Dissipation.............................................................1W
DC Output Current (1 output at a time, 1s duration)....15mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
θ
jc
5.4 C/W; θ
ja
44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θ
jc
6.2 C/W; θ
ja
51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
Note: Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
DC Characteristics
(V
CC
= 2.7V to 3.6V)
Note The HSB pin has I
OUT
=-10 uA for V
OH
of 2.4 V, this parameter is characterized but not tested.
Symbol Parameter Commercial Industrial Units Notes
Min Max Min Max
I
CC1
Average V
CC
Current 65
55
50
70
60
55
mA
mA
mA
t
AVAV
= 25 ns
t
AVAV
= 35 ns
t
AVAV
= 45 ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
I
CC2
Average V
CC
Current during
STORE 3 3 mA All Inputs Don’t Care, V
CC
= max
Average current for duration of STORE
cycle (t
STORE
)
I
CC3
Average V
CC
Current at t
AVAV
=
200 ns
3V, 25°C, Typical
10 10 mA W ≥ (V
CC
– 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output loads.
I
CC4
Average V
CAP
Current during
AutoStore Cycle 3 3 mA All Inputs Don’t Care Average current for duration of STORE
cycle (t
STORE
)
I
SB
V
CC
Standby Current
(Standby, Stable CMOS Levels) 33mAE
≥ ( V
CC
-0.2V)
All Others V
IN
≤ 0.2V or ≥ (V
CC
-0.2V)
Standby current level after nonvolatile
cycle complete
I
ILK
Input Leakage Current ±1±1μAV
CC
= max
V
IN
= V
SS
to V
CC
I
OLK
Off-State Output Leakage
Current ±1±1μAV
CC
= max
V
IN
= V
SS
to V
CC
, E or G ≥ V
IH
V
IH
Input Logic “1” Voltage 2.0 V
CC
+0.3 2.0 V
CC
+0.3 V All Inputs
V
IL
Input Logic “0” Voltage V
SS
–0.5 0.8 V
SS
–0.5 0.8 V All Inputs
V
OH
Output Logic “1” Voltage 2.4 2.4 V I
OUT
=–2 mA
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 4 mA
T
A
Operating Temperature 0 70 –40 85 ° C
V
CC
Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V + 0.3V
V
CAP
Storage Capacitance 17 120 17 120 μFBetweenV
CAP
pin and V
SS
, 5V rated.
NV
C
Nonvolatile STORE operations 200 200 K
DATA
R
Data Retention 20 20 Years At 55 ° C
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STK14CA8
Document Number: 001-51592 Rev. ** Page 4 of 16
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times ................................................. ≤ 5 ns
Input and Output Timing Reference Levels....................1.5V
Output Load..................................See Figure 4 and Figure 5
Capacitance
(T
A
= 25°C, f = 1.0 MHz)
Figure 4. AC Output Loading
Figure 5. AC Output Loading for Tristate Specifications
(t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
)
Symbol Parameter
[2]
Max Units Conditions
C
IN
Input Capacitance 7 pF Δ V = 0 to 3V
C
OUT
Output Capacitance 7 pF Δ V = 0 to 3V
577 Ohms
30 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
577 Ohms
5 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
Note
2. These parameters are guaranteed but not tested.
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STK14CA8
Document Number: 001-51592 Rev. ** Page 5 of 16
SRAM READ Cycles #1 and #2
Figure 6. SRAM READ Cycle #1: Address Controlled
[3, 4, 6]
Figure 7. SRAM READ Cycle #2: E and G Controlled
[3, 6]
NO. Symbols Parameter STK14CA8-25 STK14CA8-35 STK14CA8-45 Units
#1 #2 Alt. Min Max Min Max Min Max
1
t
ELQV
t
ACS
Chip Enable Access Time 25 35 45 ns
2
t
AVAV[3]
t
ELEH[3]
t
RC
Read Cycle Time 25 35 45 ns
3
t
AVQV[4]
t
AVQV[4]
t
AA
Address Access Time 25 35 45 ns
4
t
GLQV
t
OE
Output Enable to Data Valid 12 15 20 ns
5
t
AXQX[4]
t
AXQX[4]
t
OH
Output Hold after Address Change 3 3 3 ns
6
t
ELQX
t
LZ
Address Change or Chip Enable to
Output Active 333ns
7
t
EHQZ[5]
t
HZ
Address Change or Chip Disable to
Output Inactive 10 13 15 ns
8
t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 ns
9
t
GHQZ[5]
t
OHZ
Output Disable to Output Inactive 10 13 15 ns
10
t
ELICCH[2]
t
PA
Chip Enable to Power Active 0 0 0 ns
11
t
EHICCL[2]
t
PS
Chip Disable to Power Standby 25 35 45 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ±200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles
229
11
7
9
10
84
3
61
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STK14CA8
Document Number: 001-51592 Rev. ** Page 6 of 16
SRAM WRITE Cycles #1 and #2
Figure 8. SRAM WRITE Cycle #1: W Controlled
[7,8]
Figure 9. SRAM WRITE Cycle #2: E Controlled
[7,8]
NO. Symbols Parameter STK14CA8-25 STK14CA8-35 STK14CA8-45 Units
#1 #2 Alt. Min Max Min Max Min Max
12
t
AVAV
t
AVAV
t
WC
Write Cycle Time 25 35 45 ns
13
t
WLWH
t
WLEH
t
WP
Write Pulse Width 20 25 30 ns
14
t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 20 25 30 ns
15
t
DVWH
t
DVEH
t
DW
Data Setup to End of Write 10 12 15 ns
16
t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 0 ns
17
t
AVWH
t
AVEH
t
AW
Address Setup to End of Write 20 25 30 ns
18
t
AVWL
t
AVEL
t
AS
Address Setup to Start of Write 0 0 0 ns
19
t
WHAX
t
EHAX
t
WR
Address Hold after End of Write 0 0 0 ns
20
t
WLQZ[5,7]
t
WZ
Write Enable to Output Disable 10 13 15 ns
21
t
WHQX
t
OW
Output Active after End of Write 3 3 3 ns
Notes
7. If W is low when E goes low, the outputs remain in the high impedance state.
8.
Eor W must be ≥V
IH
during address transitions.
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA IN
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
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STK14CA8
Document Number: 001-51592 Rev. ** Page 7 of 16
AutoStore/POWER UP RECALL
t
Figure 10. AutoStore/POWER UP RECALL
Note Read and Write cycles are ignored during STORE, RECALL, and while V
CC
is below V
SWITCH.
NO. Symbols Parameter STK14CA8 Units Notes
Standard Alternate Min Max
22
t
HRECALL
Power up RECALL Duration 20 ms 9
23
t
STORE
t
HLHZ
STORE Cycle Duration 12.5 ms 10, 11
24
V
SWITCH
Low Voltage Trigger Level 2.65 V
25
V
CCRISE
V
CC
Rise Time 150 μs
Notes
9. t
HRECALL
starts from the time V
CC
rises above V
SWITCH
10.If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place
11. Industrial Grade devices require maximum 15 ms.
25
23 23
22 22
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STK14CA8
Document Number: 001-51592 Rev. ** Page 8 of 16
Software Controlled STORE/RECALL Cycle
Figure 11. Software STORE/RECALL CYCLE: E Controlled
[13]
Figure 12. Software STORE/RECALL CYCLE: G Controlled
[13]
NO. Symbols Parameter
[12,13]
STK14CA8-35 STK14CA8-35 STK14CA8-45 Units Notes
ECont GCont Alt Min Max Min Max Min Max
26
t
AVAV
t
AVAV
t
RC
STORE/RECALL Initiation Cycle
Time 25 35 45 ns 13
27
t
AVEL
t
AVGL
t
AS
Address Setup Time 0 0 0 ns
28
t
ELEH
t
GLGH
t
CW
Clock Pulse Width 20 25 30 ns
29
t
EHAX
t
GHAX
Address Hold Time 1 1 1 ns
30
t
RECALL
t
RECALL
RECALL Duration 50 50 50 μs
26 26
27 28
29
23 30
26 26
27 28
29 23 30
Notes
12.The software sequence is clocked on the falling edge of E controlled READs or G controlled READs
13.Thesixconsecutiveaddressesmustbereadin theorderlistedintheSoftwareSTORE/RECALL ModeSelectionTable.Wmustbehigh during allsixconsecutive cycles.
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STK14CA8
Document Number: 001-51592 Rev. ** Page 9 of 16
Hardware STORE Cycle
Figure 13. Hardware STORE Cycle
Soft Sequence Commands
Figure 14. Software Sequence Commands
NO. Symbols Parameter STK14CA8 Units Notes
Standard Alternate Min Max
31
t
DELAY
t
HLQZ
Hardware STORE to SRAM Disabled 1 70 μs 14
32
t
HLHX
Hardware STORE Pulse Width 15 ns
32
23
31
NO. Symbols Parameter STK14CA8 Units Notes
Standard Min Max
33
t
SS
Soft Sequence Processing Time 70 μs15,16
33 33
Notes
14.On a hardware STORE initiation, SRAM operation continues to be enabled for time t
DELAY
to allow read/write cycles to complete.
15.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
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STK14CA8
Document Number: 001-51592 Rev. ** Page 10 of 16
Mode Selection
E W G A
16
-A
0
Mode I/O Power Notes
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
17, 18, 19
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
17, 18, 19
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active 17, 18, 19
0x08FC0 Nonvolatile Store Output High Z I
CC2
L H L 0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
17, 18, 19
Notes
17.The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
18.While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
19.I/O state depends on the state of G. The I/O table shown assumes G low
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