Cypress Semiconductor Perform CY62147EV30 User manual

CY62147EV30 MoBL
®
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document #: 38-05440 Rev. *G Revised March 31, 2009
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Wide voltage range: 2.20V to 3.60V
■ Pin compatible with CY62147DV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE
[1]
and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ AvailableinPb-free48-ballVFBGA(single/dualCEoption)and
44-pin TSOPII packages
■ Byte power down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL
®
) in portable appli-
cations such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO
0
through IO
15
) are placed
in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE)
and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the Truth Table on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
256K x 16
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
CE
[1]
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
A
17
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE
refers to the internal logical combination of CE
1
and
CE
2
such that when CE
1
is LOW and CE
2
is HIGH, CE is LOW. For all other cases CE is HIGH.
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 2 of 13
Pin Configuration
Figure 1. 48-Ball VFBGA (Single Chip Enable)
[3, 4]
Figure 2. 48-Ball VFBGA (Dual Chip Enable)
[3, 4]
Figure 3. 44-Pin TSOP II
[3]
Product Portfolio
Product Range V
CC
Range (V) Speed
(ns)
Power Dissipation
Operating I
CC
(mA) Standby I
SB2
(μA)
f = 1 MHz f = f
max
Min Typ
[2]
Max Typ
[2]
Max Typ
[2]
Max Typ
[2]
Max
CY62147EV30LL Ind’l/Auto-A 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
Auto-E 2.2 3.0 3.6 55 ns 2 3 15 25 1 20
WE
A
11
A
10
A
6
A
0
A
3
CE
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
NC
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
WE
A
11
A
10
A
6
A
0
A
3
CE
1
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
CE
2
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC NC
326
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°.
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 3 of 13
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential .............................–0.3V to + 3.9V (V
CCmax
+ 0.3V)
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
...............–0.3V to 3.9V (V
CCmax
+ 0.3V)
DC Input Voltage
[5, 6]
............–0.3V to 3.9V (V
CCmax
+ 0.3V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage .......................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Device Range Ambient
Temperature V
CC [7]
CY62147EV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to
3.6V
Auto-E –40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Typ
[2]
Max Min Typ
[2]
Max
V
OH
Output HIGH
Voltage I
OH
= –0.1 mA 2.0 2.0 V
I
OH
= –1.0 mA, V
CC
>2.70V 2.4 2.4 V
V
OL
Output LOW
Voltage I
OL
= 0.1 mA 0.4 0.4 V
I
OL
= 2.1 mA, V
CC
= 2.70V 0.4 0.4 V
V
IH
Input HIGH
Voltage V
CC
= 2.2V to 2.7V 1.8 V
CC
+ 0.3 1.8 V
CC
+ 0.3 V
V
CC
= 2.7V to 3.6V 2.2 V
CC
+ 0.3 2.2 V
CC
+ 0.3 V
V
IL
Input LOW
Voltage V
CC
= 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V
V
CC
= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V
I
IX
Input Leakage
Current GND <V
I
< V
CC
–1 +1 –4 +4 μA
I
OZ
Output Leakage
Current GND <V
O
<V
CC
,Output Disabled –1 +1 –4 +4 μA
I
CC
V
CC
Operating
Supply Current f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
15 20 15 25 mA
f = 1 MHz 2 2.5 2 3
I
SB1
Automatic CE
Power Down
Current —
CMOS Inputs
CE > V
CC
– 0.2V
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V
f = f
max
(Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
V
CC
= 3.60V
17 120μA
I
SB2 [8]
Automatic CE
Power Down
Current —
CMOS Inputs
CE > V
CC
– 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
17 120μA
Capacitance
For all packages.
[9]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
10 pF
C
OUT
Output Capacitance 10 pF
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 4 of 13
Thermal Resistance
[9]
Parameter Description Test Conditions VFBGA
Package TSOP II Package Unit
Θ
JA
Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 75 77 °C/W
Θ
JC
Thermal Resistance
(Junction to Case) 10 13 °C/W
Figure 4. AC Test Load and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
8000 645 Ω
V
TH
1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[2]
Max Unit
V
DR
V
CC
for Data Retention 1.5 V
I
CCDR[8]
Data Retention Current V
CC
= 1.5V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V Ind’l/Auto-A 0.8 7 μA
Auto-E 12
t
CDR [9]
Chip Deselect to Data Retention Time 0 ns
t
R [10]
Operation Recovery Time t
RC
ns
Figure 5. Data Retention Waveform
[
1
, 11]
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
ALL INPUT PULSES
R
TH
R1
Equivalent to: THEVENIN EQUIVALENT
V
CC(min)
V
CC(min)
t
CDR
V
DR
>1.5V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE.BLE
Notes
10.Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 5 of 13
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter Description 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 45 55 ns
t
AA
Address to Data Valid 45 55 ns
t
OHA
Data Hold from Address Change 10 10 ns
t
ACE
CE LOW to Data Valid 45 55 ns
t
DOE
OE LOW to Data Valid 22 25 ns
t
LZOE
OE LOW to LOW Z
[14]
55ns
t
HZOE
OE HIGH to High Z
[14, 15]
18 20 ns
t
LZCE
CE LOW to Low Z
[14]
10 10 ns
t
HZCE
CE HIGH to High Z
[14, 15]
18 20 ns
t
PU
CE LOW to Power Up 0 0 ns
t
PD
CE HIGH to Power Down 45 55 ns
t
DBE
BLE/BHE LOW to Data Valid 45 55 ns
t
LZBE
BLE/BHE LOW to Low Z
[14]
10 10 ns
t
HZBE
BLE/BHE HIGH to HIGH Z
[14, 15]
18 20 ns
Write Cycle
[16]
t
WC
Write Cycle Time 45 55 ns
t
SCE
CE LOW to Write End 35 40 ns
t
AW
Address Setup to Write End 35 40 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Setup to Write Start 0 0 ns
t
PWE
WE Pulse Width 35 40 ns
t
BW
BLE/BHE LOW to Write End 35 40 ns
t
SD
Data Setup to Write End 25 25 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High-Z
[14, 15]
18 20 ns
t
LZWE
WE HIGH to Low-Z
[14]
10 10 ns
Notes
12.Test conditions for all parameters otherthan tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the AC Test Load and Waveforms on page 4.
13.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
14.At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
15.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
16.The internal write time of the memory is defined by the overlap of WE, CE
= V
IL
, BHE, BLE, or both = V
IL
. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback

CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 6 of 13
Switching Waveforms
Figure 6. Read Cycle No. 1 (Address Transition Controlled)
[17, 18]
Figure 7. Read Cycle No. 2 (OE Controlled)
[1, 18, 19]
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGHIMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
17.The device is continuously selected. OE, CE
= V
IL
, BHE, BLE, or both = V
IL
.
18.WE is HIGH for read cycle.
19.Address valid before or similar to CE and BHE, BLE transition LOW.
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 7 of 13
Figure 8. Write Cycle No. 1 (WE Controlled)
[1, 16, 20, 21]
Figure 9. Write Cycle No. 2 (CE Controlled)
[1, 16, 20, 21]
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
t
HZOE
DATA
IN
NOTE 22
t
BW
t
SCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
t
BW
t
SA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 22
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 8 of 13
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW)
[1, 21]
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[1, 21]
Switching Waveforms (continued)
DATA
IN
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 22
CE
ADDRESS
WE
DATA IO
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
DATA
IN
t
BW
t
SCE
t
PWE
t
HZWE
t
LZWE
NOTE 22
DATA IO
ADDRESS
CE
WE
BHE/BLE
Notes
20.Data I/O is high impedance if OE = V
IH
.
21.If CE goes HIGH simultaneously with WE = V
IH
, the output remains in a high impedance state.
22.During this period, the IOs are in output state. Do not apply input signals.
[+] Feedback

CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 9 of 13
Truth Table
CE
[
1
]
WE OE BHE BLE IOs Mode Power
H X X X X High Z Deselect/Power Down Standby (I
SB
)
L X X H H High Z Deselect/Power Down Standby (I
SB
)
L H L L L Data Out (IO
0
–IO
15
) Read Active (I
CC
)
L H L H L Data Out (IO
0
–IO
7
);
IO
8
–IO
15
in High Z Read Active (I
CC
)
L H L L H Data Out (IO
8
–IO
15
);
IO
0
–IO
7
in High Z Read Active (I
CC
)
L H H L L High Z Output Disabled Active (I
CC
)
L H H H L High Z Output Disabled Active (I
CC
)
L H H L H High Z Output Disabled Active (I
CC
)
L L X L L Data In (IO
0
–IO
15
) Write Active (I
CC
)
L L X H L Data In (IO
0
–IO
7
);
IO
8
–IO
15
in High Z Write Active (I
CC
)
L L X L H Data In (IO
8
–IO
15
);
IO
0
–IO
7
in High Z Write Active (I
CC
)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62147EV30LL-45BVI 51-85150 48-Ball Very Fine Pitch Ball Grid Array
[23]
Industrial
CY62147EV30LL-45BVXI 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free)
[23]
CY62147EV30LL-45B2XI 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free)
[24]
CY62147EV30LL-45ZSXI 51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
CY62147EV30LL-45BVXA 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free)
[23]
Automotive-A
CY62147EV30LL-45ZSXA 51-85087 44-Pin Thin Small Outline Package II (Pb-Free)
55 CY62147EV30LL-55ZSXE 51-85087 44-Pin Thin Small Outline Package II (Pb-Free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Notes
23.This BGA package is offered with single chip enable.
24.This BGA package is offered with dual chip enable.
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 10 of 13
Package Diagrams
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
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