Cypress Semiconductor CY62147DV18 User manual

4-Mb (256K x 16) Static RAM
CY62147DV18
MoBL2™
Cypress Semiconductor Corporation •3901 North First Street •San Jose, CA 95134 •408-943-2600
Document #: 38-05343 Rev. *B Revised February 26, 2004
Features
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
Functional Description[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0through I/O15) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0through
I/O7), is written into the location specified on the address pins
(A0through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8through I/O15) is written into the location
specified on the address pins (A0through A17).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8to I/O15. See
the truth table for a complete description of read and write
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
256K x 16
RAM Array I/O
0
– I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
– I/O
15
CE
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
Power - Down
Circuit
A
10
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 2 of 11
Pin Configuration[2, 3, 4]
FBGA (Top View)
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
WE
A11
A10
A6
A0
A3CE
I/O
10
I/O
8
I/O
9
A4
A5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
Vss
A7
I/O
0
BHE
NC
A17
A2
A1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A14
A13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
DNU
Vcc
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground
Potential......................................–0.2V to + VCC(MAX) + 0.2V
DC Voltage Applied to Outputs
in High Z State[5,6]..........................–0.2V to VCC(MAX) + 0.2V
DC Input Voltage[5,6] .....................–0.2V to VCC (MAX) + 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Device Range
Ambient
Temperature
(TA) VCC[7]
CY62147DV18L Industrial –40°Cto +85°C 1.65V to 2.25V
CY62147DV18LL
Product Portfolio
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby ISB2 (µA)f = 1MHz f = fmax
Min. Typ.[7] Max. Typ.[7] Max. Typ.[7] Max. Typ.[7] Max.
CY62147DV18L 1.65 1.8 2.25 55 1.0 2.0 615 0.5 18
CY62147DV18LL 10 12
CY62147DV18L 1.65 1.8 2.25 70 1.0 2.0 615 0.5 18
CY62147DV18LL 10 12
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
CY62147DV18-55 CY62147DV18-70
UnitMin. Typ.[7] Max. Min. Typ.[7] Max.
VOH Output HIGH
Voltage IOH = –0.1 mA VCC = 1.65V 1.4 1.4 V
VOL Output LOW
Voltage IOL = 0.1 mA VCC = 1.65V 0.2 0.2 V
VIH Input HIGH
Voltage VCC =1.65V to 2.25V 1.4 VCC + 0.2V 1.4 VCC + 0.2V V
VIL Input LOW
Voltage VCC =1.65V to 2.25V –0.2 0.4 –0.2 0.4 V
IIX Input Leakage
Current GND <VI< VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND <VO <VCC, Output Disabled –1 +1 –1 +1 µA
ICC VCC Operating
Supply Current f = fMAX = 1/tRC VCC(max) = 1.95V
IOUT = 0 mA
CMOS levels
L 6 12 612 mA
LL 8 8
VCC(max) = 2.25V
IOUT = 0 mA
CMOS levels
L 6 15 615 mA
LL 10 10
f = 1 MHz VCC(max) = 1.95V L 1 1.5 11.5 mA
LL
VCC(max) = 2.25V L 1 2 1 2 mA
LL
Notes:
5. VIL(min.) = –2.0V for pulse durations less than 20 ns.
6. VIH(max)=VCC+0.75V for pulse durations less than 20ns.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 4 of 11
ISB1 Automatic CE
Power-Down
Current —
CMOS Inputs
CE > VCC−0.2V,
VIN>VCC–0.2V,
VIN<0.2V); f = fMAX
(Address and Data
Only), f = 0 (OE,
WE,BHE and BLE)
VCC(max)=1.95V L0.5 12 0.5 12 µA
LL 8 8
VCC(max)=2.25V L0.5 18 0.5 18
LL 12 12
ISB2 Automatic CE
Power-down
Current —
CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V, f = 0
VCC(max)=1.95V L0.5 12 0.5 12 µA
LL 8 8
VCC(max)=2.25V L0.5 18 0.5 18
LL 12 12
Capacitance for all Packages[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Thermal Resistance
Parameter Description Test Conditions BGA Unit
ΘJA Thermal Resistance
(Junction to Ambient)[8] Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
75 °C/W
ΘJC Thermal Resistance
(Junction to Case)[8] 10 °C/W
AC Test Loads and Waveforms
Parameters 1.80V Unit
R1 13500 Ω
R2 10800 Ω
RTH 6000 Ω
VTH 0.80 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.[7] Max. Unit
VDR VCC for Data Retention 1.0 V
ICCDR Data Retention Current VCC= 1.0V CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
L 6 µA
LL 4
tCDR[8] Chip Deselect to Data Retention Time 0ns
tROperation Recovery Time tRC ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions
CY62147DV18-55 CY62147DV18-70
UnitMin. Typ.[7] Max. Min. Typ.[7] Max.
VCCVCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 5 of 11
wqewqewq
Data Retention Waveform[9]
Switching Characteristics Over the Operating Range [10.]
Parameter Description
55 ns 70 ns
UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to LOW Z[11]5 5 ns
tHZOE OE HIGH to High Z[11, 12]16 16 ns
tLZCE CE LOW to Low Z[11]10 10 ns
tHZCE CE HIGH to High Z[11, 12]20 25 ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 55 70 ns
tDBE BLE / BHE LOW to Data Valid 55 70 ns
tLZBE BLE / BHE LOW to Low Z[11]10 10 ns
tHZBE BLE / BHE HIGH to HIGH Z[11, 12]20 25 ns
Write Cycle[13]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 40 50 ns
tAW Address Set-up to Write End 40 50 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Width 40 45 ns
tBW BLE / BHE LOW to Write End 40 50 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z[11, 12]20 25 ns
tLZWE WE HIGH to Low-Z[11]10 10 ns
Notes:
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
VCC(min)
VCC(min)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 6 of 11
Switching Waveforms
Notes:
14. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle 1 (Address Transition Controlled)[14, 15]
Read Cycle No. 2 (OE Controlled) [15, 16]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DBE
t
DOE
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 7 of 11
Notes:
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN
NOTE
Write Cycle No. 1 (WE Controlled)[13, 17, 18]
19
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN
CE
ADDRESS
WE
DATA I/O
OE
NOTE 19
Write Cycle No. 2 (CE Controlled)
BHE/BLE tBW
[13, 17, 18]
tSA
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 8 of 11
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 19
Write Cycle No. 3 (WE Controlled, OE LOW)
tBW
BHE/BLE
[18]
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [18]
NOTE 19
t
BW
BHE/BLE
tSCE
t
PWE
tHZWE
tLZWE
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 9 of 11
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
X X X H H High Z Deselect/Power-Down Standby (ISB)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read (Lower byte only) Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read (Higher byte only) Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write (Lower byte only) Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write (Higher byte only) Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
55 CY62147DV18L-55BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62147DV18LL-55BVI
70 CY62147DV18L-70BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62147DV18LL-70BVI
55 CY62147DV18L-55BVXI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free Industrial
CY62147DV18LL-55BVXI
70 CY62147DV18L-70BVXI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free Industrial
CY62147DV18LL-70BVXI
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CY62147DV18
MoBL2™
Document #: 38-05343 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
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