Cypress Semiconductor CY7C68300C User manual

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document 001-05809 Rev. *A Revised November 30, 2006
Features
• Fixed-function mass storage device—requires no firmware
• Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portable USB
hard drives
• Certified compliant for USB 2.0 (TID# 40490119), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
• Operatesathigh-speed(480Mbps)orfull-speed(12Mbps)
USB
• Complies with ATA/ATAPI-6 specification
• Supports 48 bit addressing for large hard drives
• Supports ATA security features
• Supports any ATA command with the ATACB function
• Supports mode page 5 for BIOS boot support
• SupportsATAPIserialnumberVPDpageretrievalforDigital
Rights Management (DRM) compatibility
• Supports PIO modes 0, 3, and 4, multiword DMA mode 2,
and UDMA modes 2, 3, and 4
• UsesonesmallexternalserialEEPROMforstorageofUSB
descriptors and device configuration data
• ATA interface IRQ signal support
• Supports one or two ATA/ATAPI devices
• Supports CompactFlash and one ATA/ATAPI device
• Supports board-level manufacturing test using the USB I/F
• Can place the ATA interface in high impedance (Hi-Z) to
allowsharingoftheATA buswith another controller(i.e.,an
IEEE-1394 to ATA bridge chip or MP3 Decoder)
• Low-power 3.3V operation
• FullycompatiblewithnativeUSBmassstorageclassdrivers
• Cypress mass storage class drivers available for Windows
(98SE, ME, 2000, XP) and Mac OS X operating systems
Features (CY7C68320C/CY7C68321C only)
• SupportsHIDinterfaceorcustomGPIOstoenablefeatures
such as single button backup, power-off, LED-based notifi-
cation, etc.
• 56-pin QFN and 100-pin TQFP lead-free packages
• CY7C68321C is ideal for battery-powered designs
• CY7C68320C is ideal for self- and bus-powered designs
Features (CY7C68300C/CY7C68301C only)
• Pin-compatible with CY7C68300A (using Backward
Compatibility mode)
• 56-pin SSOP and 56-pin QFN lead-free packages
• CY7C68301C is ideal for battery-powered designs
• CY7C68300C is ideal for self- and bus-powered designs
USB 2.0
Tranceiver CY Smart USB FS/HS Engine 4 kByte FIFO
PLL
I2C Bus Master
ATA
Interface
Logic
Data
Control
24
MHz
XTAL
16 Bit ATA DataUSB D+
D-
Internal Control Logic
VBUS
ATA Interface
Control Signals
Misc control signals and GPIO
SDA
SCL
ATA 3-state Control
Reset
Block Diagram
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 2 of 42
Applications
The CY7C68300C/301C and CY7C68320C/321A implement
a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage
devices, such as the following:
• Hard drives
• CD-ROM, CD-R/W
• DVD-ROM, DVD-RAM, DVD±R/W
• MP3 players
• Personal media players
• CompactFlash
• Microdrives
• Tape drives
• Personal video recorders
TheCY7C68300C/301C and CY7C68320C/321Asupport one
or two devices in the following configurations:
• ATA/ATAPI master only
• ATA/ATAPI slave only
• ATA/ATAPI master and ATA/ATAPI slave
• CompactFlash only
• ATA/ATAPI slave and CompactFlash or other removable
IDE master
Additional Resources
• CY4615C EZ-USB AT2LP Reference Design Kit
•USB Specification version 2.0
•ATA Specification T13/1410D Rev 3B
• USBMassStorageClassBulkOnlyTransportSpecification,
www.usb.org
Introduction
The EZ-USB AT2LP™(CY7C68300C/CY7C68301C and
CY7C68320C/CY7C68321C) implements a fixed-function
bridge between one USB port and one or two ATA- or
ATAPI-based mass storage device ports. This bridge adheres
to the Mass Storage Class Bulk-Only Transport Specification
(BOT) and is intended for bus- and self-powered devices.
The AT2LP is the latest addition to the Cypress USB mass
storage portfolio, and is an ideal cost- and power-reduction
path for designs that previously used Cypress’s ISD-300A1,
ISD-300LP, or EZ-USB AT2.
Specifically, the CY7C68300C/CY7C68301C includes a
mode that makes it pin-for-pin compatible with the
EZ-USB AT2 (CY7C68300A).
The USB port of the CY7C68300C/301C and
CY7C68320C/321A (AT2LP) are connected to a host
computer directly or with the downstream port of a USB hub.
Software on the USB host system issues commands and
sends data to the AT2LP and receives status and data from
the AT2LP using standard USB protocol.
The ATA/ATAPI port of the AT2LP is connected to one or two
mass storage devices. A 4 KB buffer maximizes ATA/ATAPI
data transfer rates by minimizing losses due to device seek
times. The ATA interface supports ATA PIO modes 0, 3, and 4,
multiword DMA mode 2, and Ultra DMA modes 2, 3, and 4.
The device initialization process is configurable, enabling the
AT2LP to initialize ATA/ATAPI devices without software inter-
vention.
CY7C68300A Compatibility
As mentioned above, the CY7C68300C/301C contains a
backward compatibility mode that allows it to be used in
existing EZ-USB AT2 (CY7C68300A) designs. The backward
compatibility mode is enabled by programming the EEPROM
with the CY7C68300A signature.
During startup, the AT2LP checks the I2C™ bus for an
EEPROM with a valid signature in the first two bytes. If the
signature is 0x4D4D, the AT2LP configures itself for pin-to-pin
compatibility with the AT2 and begins normal mass storage
operation. If the signature is 0x534B, the AT2LP configures
itself with the AT2LP pinout and begins normal mass storage
operation.
Refer to the logic flow in Figure 1 for more information on the
pinout selection process.
Most designs that use the AT2 can migrate to the AT2LP with
no changes to either the board layout or EEPROM data.
Cypress has published an application note focused on
migrating from the AT2 to the AT2LP to help expedite the
process. It can be downloaded from the Cypress website
(http://www.cypress.com) or obtained through a Cypress
representative.
Figure 1. Simplified Pinout Selection Flowchart
Read EEPROM
EEPROM
Signature
0x4D4D?
Yes
Set
EZ-USB AT2
(CY7C68300A)
Pinout
Set
EZ-USB AT2LP
(CY7C68300B)
Pinout
No
Normal Operation
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 3 of 42
Pin Diagrams
TheAT2LP is available in different packagetypes tomeeta varietyofdesign needs. The CY7C68320C/321Cisavailablein 56-pin
QFN and 100-pin TQFP packages to provide thegreatestflexibilityfornew designs. The CY7C68300C/301Cis available in 56-pin
SSOP and QFN package types to ensure backward compatibility with CY7C68300A designs.
Figure 2. 56-pin SSOP Pinout (CY7C68300C/CY7C68301C only)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56
55
54
53
ATAPUEN (GND)
VCC
GND
IORDY
DMARQ
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
PWR500# (PU 10K)
GND (Reserved)
SCL
SDA
VCC
DD0
DD1
DD2
DD3
DD13
DD14
DD15
GND
EZ-USB AT2LP
CY7C68300C
CY7C68301C
56-pin SSOP
DD8
(ATA_EN) VBUS_ATA_ENABLE
VCC
RESET#
GND
ARESET#
(VBUS_PWR_VALID) DA2
CS1#
CS0#
(DA2) DRVPWRVLD
DA1
DA0
INTRQ
VCC
DMACK#
DIOR#
DIOW#
GND
VCC
GND
DD7
DD6
DD5
DD4
DD12
DD11
DD10
DD9
NOTE: Labels in italics denote pin functionality
during CY7C68300A compatibility mode.
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 4 of 42
Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C)
RESET#
GND
ARESET#
DA2 (VBUS_PWR_VALID)
CS1#
CS0#
DRVPWRVLD (DA2)
DA1
DA0
INTRQ
VCC
DMACK#
DIOR#
DIOW#
IORDY
DMARQ
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
(PU10K) PWR500#
GND
15 16 17 18 19 20
21
22 23 24 25 26 27 28
SCL
SDA
VCC
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7
GND
VCC
GND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND VCC ATAPUEN (NC) GND DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 VBUS_ATA_ENABLE (ATA_EN) VCC
EZ-USB AT2LP
CY7C68300C
CY7C68301C
56-pin QFN
NOTE: Italic labels denote pin functionality
during CY7C68300A compatibility mode.
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 5 of 42
Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56
55
54
53
GPIO2
VCC
GND
IORDY
DMARQ
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
GPIO1
GND
SCL
SDA
VCC
DD0
DD1
DD2
DD3
DD13
DD14
DD15
GND
EZ-USB AT2LP
CY7C68320C
CY7C68321C
56-pin SSOP
DD8
VBUS_ATA_ENABLE
VCC
RESET#
GND
ARESET#
DA2
CS1#
CS0#
GPIO0
DA1
DA0
INTRQ
VCC
DMACK#
DIOR#
DIOW#
GND
VCC
GND
DD7
DD6
DD5
DD4
DD12
DD11
DD10
DD9
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 6 of 42
Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C)
GND VCC GPIO2 GND DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 VBUS_ATA_ENABLE VCC
RESET#
GND
ARESET#
DA2
CS1#
CS0#
GPIO0
DA1
DA0
INTRQ
VCC
DMACK#
DIOR#
DIOW#
IORDY
DMARQ
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
GPIO1
GND
SCL
SDA
VCC
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7
GND
VCC
GND
15 16 17 18 19 20
21
22 23 24 25 26 27 28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EZ-USB AT2LP
CY7C68320C
CY7C68321C
56-pin QFN
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 7 of 42
Figure 6. 100-pin TQFP Pinout (CY7C68320C/CY7C68321C only)
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DD8
VBUS_ATA_ENABLE
VCC
RESET#
NC
GND
ARESET#
DA2
CS1#
CS0#
DRVPWRVLD
DA1
DA0
INTRQ
VCC
GND
NC
NC
VBUSPWRD
NC
NC
NC
LOWPWR#
NC
DMACK#
DIOR#
DIOW#
VCC
NC
NC
VCC
GND
IORDY
DMARQ
GND
GND
GND
GND
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
VCC
GND
SYSIRQ
GND
GND
GND
PWR500#
GND
NC
SCL
SDA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EZ-USB AT2LP
CY7C68320A
CY7C68321A
100-pin TQFP
NC NC VCC DD0 DD1 DD2 DD3 VCC GND NC GND NC GND DD4 DD5 DD6 DD7 GND VCC GND
ATAPUEN
GND
DD15 DD14 DD13 DD12
GND
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
NC NC
VCC
GND
DD11 DD10
DD9
C
C
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 8 of 42
Pin Descriptions
Thefollowingtableliststhepinoutsfor the56-pin SSOP,56-pin
QFN and 100-pin TQFP package options for the AT2LP. Refer
to the “Pin Diagrams” on page 3 for differences between the
68300C/01C and 68320C/321C pinouts for the 56-pin
packages. For information on the CY7C68300A pinout, refer
to the CY7C68300A data sheet that is found in the ’EZ-USB
AT2’ folder of the CY4615C reference design kit CD.
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
100
TQFP 56 QFN 56 SSOP Pin Name Pin Type DefaultState at Startup Pin Description
155 6 VCC PWR VCC. Connect to 3.3V power source.
256 7 GND GND Ground.
3 1 8 IORDY I[1] Input ATA control. Apply a 1k pull up to 3.3V.
4 2 9 DMARQ I[1] Input ATA control.
5
6
7
8
N/A N/A GND Ground.
9 3 10 AVCC PWR AnalogVCC.Connect toVCC throughthe shortestpath
possible.
10 411 XTALOUT Xtal Xtal 24 MHz crystal output. (See “XTALIN, XTALOUT” on
page 11).
11 512 XTALIN Xtal Xtal 24 MHz crystal input. (See “XTALIN, XTALOUT” on
page 11).
12 613 AGND GND Analog ground. Connect to ground with as short a
path as possible.
13
14
15
N/A N/A NC No connect.
16 714 VCC PWR VCC. Connect to 3.3V power source.
17 815 DPLUS IO Hi-Z USB D+ signal (See “DPLUS, DMINUS” on page 11).
18 916 DMINUS IO Hi-Z USB D–signal (See “DPLUS, DMINUS” on page 11).
19 10 17 GND GND Ground.
20 11 18 VCC PWR VCC. Connect to 3.3V power source.
21 12 19 GND GND Ground.
22 N/A N/A SYSIRQ IInput USB interrupt request. (See “SYSIRQ” on page 12).
Active HIGH. Connect to GND if functionality is not
used.
23
24
25
N/A N/A GND GND Ground.
26[3] 13[3] 20 PWR500#[2]
(PU 10K)ObMaxPower request granted indicator. (See
“PWR500#” on page 14). Active LOW.
N/A for CY7C68320C/CY7C68321C 56-pin packages.
27 14 21 GND (RESERVED)Reserved. Tie to GND.
28 N/A N/A NC No connect.
29 15 22 SCL OActive for
severalms at
startup.
Clock signal for I2C interface. (See “SCL, SDA” on
page 11). Apply a 2.2k pull up resistor.
Notes
1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See “VBUS_ATA_ENABLE” on
page 14.
2. A ‘#’ sign after the pin name indicates that it is active LOW.
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Document 001-05809 Rev. *A Page 9 of 42
30 16 23 SDA IO Data signal for I2C interface. (See “SCL, SDA” on
page 11).
Apply a 2.2k pull up resistor.
31
32 N/A N/A NC No connect.
33 17 24 VCC PWR VCC. Connect to 3.3V power source.
34 18 25 DD0 IO[1] Hi-Z ATA data bit 0.
35 19 26 DD1 IO[1] Hi-Z ATA data bit 1.
36 20 27 DD2 IO[1] Hi-Z ATA data bit 2.
37 21 28 DD3 IO[1] Hi-Z ATA data bit 3.
38 N/A N/A VCC PWR VCC. Connect to 3.3V power source.
39 N/A N/A GND GND Ground.
40 N/A N/A NC NC No connect.
41 N/A N/A GND Ground.
42 N/A N/A NC NC No connect.
43 N/A N/A GND Ground.
44 22 29 DD4 IO[1] Hi-Z ATA data bit 4.
45 23 30 DD5 IO[1] Hi-Z ATA data bit 5.
46 24 31 DD6 IO[1] Hi-Z ATA data bit 6.
47 25 32 DD7 IO[1] Hi-Z ATA data bit 7. Apply a 1k pull down to GND.
48 26 33 GND GND Ground.
49 27 34 VCC PWR VCC. Connect to 3.3V power source.
50 28 35 GND GND Ground.
51
52 N/A N/A NC NC No connect.
53 N/A N/A VCC PWR VCC. Connect to 3.3V power source.
54 29 36 DIOW#[2] O/Z[1] Driven HIGH
(CMOS) ATA control.
55 30 37 DIOR# O/Z[1] Driven HIGH
(CMOS) ATA control.
56 31 38 DMACK# O/Z[1] Driven HIGH
(CMOS) ATA control.
57 N/A N/A NC NC No connect.
58 N/A N/A LOWPWR# OUSB suspend indicator. (See “LOWPWR#” on
page 13).
59
60
61
N/A N/A NC NC No connect.
62 N/A N/A VBUSPWRD IInput Bus-powered mode selector. (See “VBUSPWRD”on
page 14).
63
64 N/A N/A NC NC No connect.
65 N/A N/A GND GND Ground.
66 32 39 VCC PWR VCC. Connect to 3.3V power source.
67 33 40 INTRQ I[1] Input ATA interrupt request.
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)
100
TQFP 56 QFN 56 SSOP Pin Name Pin Type DefaultState at Startup Pin Description
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Document 001-05809 Rev. *A Page 10 of 42
68 34 41 DA0 O/Z[1] Driven HIGH
after 2 ms
delay
ATA address.
69 35 42 DA1 O/Z[1] Driven HIGH
after 2 ms
delay
ATA address.
70[3] 36[3] 43 DRVPWRVLD
(DA2)IInput Device presence detect. (See “DRVPWRVLD” on page 13). Configurable logical polarity is controlled by
EEPROM address 0x08. This pin must be pulled HIGH
if functionality is not utilized.
Alternate function. Input when the EEPROM configu-
ration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 0).
71 37 44 CS0# O/Z[1] Driven HIGH
after 2 ms
delay
ATA chip select.
72 38 45 CS1# O/Z[1] Driven HIGH
after 2 ms
delay
ATA chip select.
73 39 46 DA2
(VBUS_PWR_VALID)O/Z[1] Driven HIGH after 2 ms
delay
ATA address.
74 40 47 ARESET# O/Z[1] ATA reset.
75 41 48 GND GND Ground.
76 N/A N/A NC NC No connect.
77 42 49 RESET# IInput Chip reset (See “RESET#” on page 14).
78 43 50 VCC PWR VCC. Connect to 3.3V power source.
79 44 51 VBUS_ATA_ENABLE
(ATA_EN)IInput VBUS detection (See “VBUS_ATA_ENABLE” on page 14).
80 45 52 DD8 IO[1] Hi-Z ATA data bit 8.
81 46 53 DD9 IO[1] Hi-Z ATA data bit 9.
82 47 54 DD10 IO[1] Hi-Z ATA data bit 10.
83 48 55 DD11 IO[1] Hi-Z ATA data bit 11.
84 N/A N/A GND Ground.
85 N/A N/A VCC PWR VCC. Connect to 3.3V power source.
86
87 N/A N/A NC NC No connect.
88
89
90
91
92
93
36[3]
13[3]
54[3]
N/A GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
IO[3] General purpose IO pins (See “GPIO Pins” on
page 13). The GPIO pins must be tied to GND if
functionality is not used.
94 N/A N/A GND GND Ground.
95 49 56 DD12 IO[1] Hi-Z ATA data bit 12.
96 50 1DD13 IO[1] Hi-Z ATA data bit 13.
97 51 2DD14 IO[1] Hi-Z ATA data bit 14.
98 52 3DD15 IO[1] Hi-Z ATA data bit 15.
99 53 4 GND GND Ground.
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)
100
TQFP 56 QFN 56 SSOP Pin Name Pin Type DefaultState at Startup Pin Description
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