Cypress Semiconductor CY7C1338G User manual

4-Mbit (128K x 32) Flow-Through Sync SRAM
CY7C1338G
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05521 Rev. *D Revised July 5, 2006
Features
• 128K x 32 common I/O
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
•User-selectable burst counter supporting Intel®
Pentium®interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1338G is a 128K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1338G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1338G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE A
[1:0]
ZZ
A
0, A1, A
ADV
CLK
ADSP
ADSC
BW D
BW C
BW B
BW A
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQ A BYTE
WRITE REGISTER
DQ
B BYTE
WRITE REGISTER
DQ
C BYTE
WRITE REGISTER
WRITE REGISTER
DQ
D BYTE DQ
D BYTE
WRITE REGISTER
DQ
C BYTE
WRITE REGISTER
DQ
B BYTE
WRITE REGISTER
DQ
A BYTE
WRITE REGISTER
DQ
s
Logic Block Diagram

CY7C1338G
Document #: 38-05521 Rev. *D Page 2 of 17
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum Standby Current 40 40 mA
Pin Configurations 100-Pin TQFP Pinout
A A A A A1 A0
NC/72M NC/36M
VSS
VDD
NC/9M
A A A A A A
NC
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
A
A
CE1
CE2
BWD BWC
BWB BWA
CE3
VDD VSS
CLK
GW
BWE OE
ADSP
A A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
BYTE A
BYTE C
AADV
ADSC
ZZ
MODE
NC/18M
BYTE B
DQB
BYTE D
CY7C1338G

CY7C1338G
Document #: 38-05521 Rev. *D Page 3 of 17
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1,CE2, andCE3 are sampled active. A[1:0] feed
the 2-bit counter.
BWA, BWB
BWC, BWDInput-
Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
GW Input-
Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE Input-
Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2and CE3to select/deselect the device. ADSP is ignored if CE1is HIGH. CE1is sampled only
when a new external address is loaded.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1and CE3to select/deselect the device. CE2is sampled only when a new external address is
loaded.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1and CE2to select/deselect the device. CE3 is sampled only when a new external address is
loaded.
OE Input-
Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
inputdatapins.OE ismaskedduringthefirst clockofa readcycle whenemergingfroma deselected
state.
ADV Input-
Synchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
Pin Configurations (continued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M NCDQ
C
DQ
D
DQ
C
DQ
D
AA AA
ADSP V
DDQ
CE
2
A
DQ
C
V
DDQ
DQ
C
V
DDQ
V
DDQ
V
DDQ
DQ
D
DQ
D
NC
NC V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
NCNCNCNC NC/36MNC/72M NC
V
DDQ
V
DDQ
V
DDQ
AAAA
NC/9M
AA
A
AA
AA0
A1
DQ
A
DQ
C
DQ
A
DQ
A
DQ
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQ
B
V
DD
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
MODE
NC
NC
BW
B
BW
C
NC V
DD
NC
BW
A
NC
BWE
BW
D
ZZ
119-Ball BGA Pinout
A

CY7C1338G
Document #: 38-05521 Rev. *D Page 4 of 17
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tC0) is 6.5 ns (133-MHz device).
The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1is HIGH.
ADSP Input-
Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE1is deasserted HIGH
ADSC Input-
Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ Input-
Asynchronous ZZ“sleep”Input,activeHIGH.WhenassertedHIGHplacesthedeviceinanon-time-critical“sleep” condition with data integrity preserved. During normal operation, this pin has to be low or left floating.
ZZ pin has an internal pull-down.
DQs I/O-
Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
are placed in a tri-state condition.
VDD Power
Supply Power supply inputs to the core of the device.
VSS Ground Ground for the core of the device.
VDDQ I/O Power
Supply Power supply for the I/O circuitry.
VSSQ I/O Ground Ground for the I/O circuitry.
MODE Input-
Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floatingselectsinterleavedburstsequence.Thisisastrappinandshouldremainstaticduringdevice
operation. Mode Pin has an internal pull-up.
NC No Connects. Not Internally connected to the die.
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.
Pin Definitions (continued)
Name I/O Description

CY7C1338G
Document #: 38-05521 Rev. *D Page 5 of 17
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:D])are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWAcontrolsDQAand BWB controls DQB.
BWC controls DQC, and BWDcontrols DQD. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:D])
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. During byte writes, BWAcontrols DQA, BWBcontrols
DQB, BWC controls DQC, and BWDcontrols DQD. All I/Os are
tri-statedwhenawriteis detected,even abytewrite. Sincethis
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1338G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
Second
Address
A1,A0
Third
Address
A1,A0
Fourth
Address
A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 40 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

CY7C1338G
Document #: 38-05521 Rev. *D Page 6 of 17
Truth Table [2, 3, 4, 5, 6]
Cycle Description Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power-down None H X X L X L X X X L-H Tri-State
Deselected Cycle, Power-down None L L X L L X X X X L-H Tri-State
Deselected Cycle, Power-down None L X H L L X X X X L-H Tri-State
Deselected Cycle, Power-down None L L X L H L X X X L-H Tri-State
Deselected Cycle, Power-down None X X X L H L X X X L-H Tri-State
Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

CY7C1338G
Document #: 38-05521 Rev. *D Page 7 of 17
Partial Truth Table for Read/Write[2, 7]
Function GW BWE BWDBWCBWBBWA
Read HHXXXX
Read HLHHHH
WriteByteA HLHHHL
Write Byte B H L H H L H
Write Bytes B, A H L H H L L
WriteByteC HLHLHH
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
WriteByteD HLLHHH
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, B H L L L H H
Write Bytes D, B, A H L L L H L
WriteBytesD,C,A HLLLLH
WriteAllBytes HLLLLL
WriteAllBytes LXXXXX
Note:
7. Table only lists a partial listing of the byte write combinations. Any combination of BWXis valid. Appropriate write will be done based on which byte write is active.

CY7C1338G
Document #: 38-05521 Rev. *D Page 8 of 17
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state............................................ –0.5V to VDDQ + 0.5V
DC Input Voltage ...................................–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200mA
Operating Range
Range Ambient Temperature]VDD VDDQ
Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%
to VDD
Industrial –40°C to+85°C
Electrical CharacteristicsOver the Operating Range [8, 9]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ I/O Supply Voltage 2.375 VDD V
VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V
for 2.5V I/O, IOH = –1.0 mA 2.0 V
VOL Output LOW Voltage for 3.3V I/O,IOL = 8.0 mA 0.4 V
for 2.5V I/O, IOL = 1.0 mA 0.4 V
VIH Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 VDD + 0.3V V
VIL Input LOW Voltage[8] for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
IXInput Leakage Current
except ZZ and MODE GND ≤VI≤VDDQ −55µA
Input Current of MODE Input = VSS –30 µA
Input = VDD 5µA
Input Current of ZZ Input = VSS –5 µA
Input = VDD 30 µA
IOZ Output Leakage Current GND ≤VI≤VDDQ, Output Disabled –5 5 µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz 225 mA
10-ns cycle, 100 MHz 205 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥VIH or VIN ≤VIL, f = fMAX,
inputs switching
7.5-ns cycle, 133 MHz 90 mA
10-ns cycle, 100 MHz 80 mA
ISB2 Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥VDD – 0.3V or VIN ≤0.3V,
f = 0, inputs static
All speeds 40 mA
ISB3 Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥VDDQ – 0.3V or VIN ≤
0.3V,
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz 75 mA
10-ns cycle, 100 MHz 65 mA
ISB4 Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥VDD – 0.3V or VIN ≤0.3V,
f = 0, inputs static
All speeds 45 mA
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ <VDD.

CY7C1338G
Document #: 38-05521 Rev. *D Page 9 of 17
Capacitance[10]
Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
55pF
CCLK Clock Input Capacitance 5 5 pF
CI/O Input/Output Capacitance 5 7 pF
Thermal Resistance[10]
Parameter Description Test Conditions 100 TQFP Package 119 BGA Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Testconditionsfollowstandardtest methods and procedures for
measuringthermalimpedance,per
EIA/JESD51.
30.32 34.1 °C/W
ΘJC Thermal Resistance
(Junction to Case) 6.85 14.0 °C/W
AC Test Loads and Waveforms
Note:
10.Tested initially and after any design or process change that may affect these parameters.
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
V
T
= 1.5V
3.3V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1 ns ≤1 ns
(c)
OUTPUT
R = 1667Ω
R =1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
VT= 1.25V
2.5V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1ns ≤1ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load

CY7C1338G
Document #: 38-05521 Rev. *D Page 10 of 17
Switching Characteristics Over the Operating Range [11, 12, 13, 14, 15, 16]
Parameter Description
–133 –100
UnitMin. Max. Min. Max.
tPOWER VDD(Typical) to the first Access[11] 11ms
Clock
tCYC Clock Cycle Time 7.5 10 ns
tCH Clock HIGH 2.5 4.0 ns
tCL Clock LOW 2.5 4.0 ns
Output Times
tCDV Data Output Valid After CLK Rise 6.5 8.0 ns
tDOH Data Output Hold After CLK Rise 2.0 2.0 ns
tCLZ Clock to Low-Z[12, 13, 14] 00ns
tCHZ Clock to High-Z[12, 13, 14] 3.5 3.5 ns
tOEV OE LOW to Output Valid 3.5 3.5 ns
tOELZ OE LOW to Output Low-Z[12, 13, 14] 00ns
tOEHZ OE HIGH to Output High-Z[12, 13, 14] 3.5 3.5 ns
Setup Times
tAS Address Set-up Before CLK Rise 1.5 2.0 ns
tADS ADSP, ADSC Set-up Before CLK Rise 1.5 2.0 ns
tADVS ADV Set-up Before CLK Rise 1.5 2.0 ns
tWES GW, BWE, BWXSet-up Before CLK Rise 1.5 2.0 ns
tDS Data Input Set-up Before CLK Rise 1.5 1.5 ns
tCES Chip Enable Set-up 1.5 2.0 ns
Hold Times
tAH Address Hold After CLK Rise 0.5 0.5 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns
tWEH GW, BWE, BWXHold After CLK Rise 0.5 0.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns
Notes:
11. This parthas a voltage regulator internally;tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
12.tCHZ, tCLZ,tOELZ, and tOEHZ are specifiedwith AC test conditions shown in part(b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14.This parameter is sampled and not 100% tested.
15.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.