Cypress Semiconductor CY7C027AV User manual

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
3.3V 32K/64K x 16/18 Dual-Port Static
RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document #: 38-06078 Rev. *B Revised December 09, 2008
Features
■ True Dual-Ported memory cells which allow
simultaneous access of the same memory location
■ 32K x 16 organization (CY7C027V/027VN/027AV
[1]
)
■ 64K x 16 organization (CY7C028V)
■ 32K x 18 organization (CY7C037V/037AV
[2]
)
■ 64K x 18 organization (CY7C038V)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15, 20, and 25 ns
■ Low operating power
■ Active: I
CC
= 115 mA (typical)
■ Standby: I
SB3
= 10 μA (typical)
■ Fully asynchronous operation
■ Automatic power down
■ Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Dual chip enables
■ Pin select for Master or Slave
■ Commercial and Industrial temperature ranges
■ 100-pin Pb-free TQFP and 100-pin TQFP
Notes
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.
2. CY7C037V and CY7C037AV are functionally identical.
3. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
4. I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices.
5. A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
6. BUSY is an output in master mode and an input in slave mode.
R/W
L
CE
0L
CE
1L
OE
L
I/O
8/9L
–I/O
15/17L
I/O
Control
Address
Decode
A
0L
–A
14/15L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
I/O
0L
–I/O
7/8L
R/W
R
CE
0R
CE
1R
OE
R
I/O
8/9L
–I/O
15/17R
CE
R
UB
R
LB
R
I/O
0L
–I/O
7/8R
UB
L
LB
L
Logic Block Diagram
A
0L
–A
14/15L
True Dual-Ported
RAM Array
A
0R
–A
14/15R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode A
0R
–A
14/15R
[3] [3]
[4] [4]
[5] [5]
[6] [6]
[5] [5]
15/16
8/9
8/9
15/16
8/9
8/9
15/16 15/16
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 2 of 18
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
SEMR
OER
GND
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
CY7C027V/027VN/027AV (32K x 16)
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
SEML
OEL
GND
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L A7L A6L A5L A4L A3L INTL A1L NC GND M/S A0R A1R A0L A2L BUSYR INTR A2R A3R A4R A5R A6R A7R A8R BUSYL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R I/O8R I/O7R
VCC
I/O6R
I/01R
I/O4R I/O2R
GND
I/O0L I/O2L I/O3L
I/O3R I/O5R
I/O1L
GND
I/O4L I/O5L I/O6L I/O7L
VCC
I/O8L I/O9L
I/O0R
3332313029282726
CY7C028V (64K x 16)
[1] [1]
Note
1. This pin is NC for CY7C027V/027VN/027AV.
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 3 of 18
Pin Configurations (continued)
Figure 2. 100-Pin TQFP (Top View)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A8R
A9R
A10R
A11R
A12R
A13R
CE0R
A15R
UBR
SEMR
R/WR
GND
I/O17R
LBR
A14R
GND
OER
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CE1R
58
57
56
55
54
53
52
51
CY7C037V/037AV (32K x 18)
A9L
A10L
A11L
A12L
A13L
A14L
CE1L
LBL
CE0L
R/WL
OEL
I/O17L
I/O16L
UBL
A15L
VCC
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
SEML
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L A7L A6L A5L A4L A3L BUSYL A1L INTL GND VCC INTR A0R A0L A2L M/S BUSYR A1R A2R A3R A4R A5R A6R A7R GND
34 35 36 424139 403837 43 44 45 5048 494746
I/O10R
I/O9R I/O8R I/O7R
VCC
I/O6R
I/01R
I/O4R I/O2R
GND
I/O0L I/O2L I/O3L
I/O3R I/O5R
I/O1L
GND
I/O4L I/O5L I/O6L I/O7L
VCC
I/O8L I/O9L
I/O0R
3332313029282726
CY7C038V (64K x 18)
[2]
[2]
Selection Guide
Parameter -15 -20 -25 Unit
Maximum Access Time 15 20 25 ns
Typical Operating Current 125 120 115 mA
Typical Standby Current for I
SB1
(Both ports TTL level) 35 35 30 mA
Typical Standby Current for I
SB3
(Both ports CMOS level) 10 μA10μA10μAμA
Note
2. This pin is NC for CY7C037V/037AV.
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 4 of 18
Architecture
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V consist of an array of 32K and 64K words
of 16 and 18 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output enable
control (OE),which allows data to be read from the device.
Functional Description
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V are low power CMOS 32K, 64K x 16/18
dual-port static RAMs. Various arbitration schemes are included
on the devices to handle situations when multiple processors
access the same piece of data. Two ports are provided, permit-
ting independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
stand-alone 16/18-bit dual-port static RAMs or multiple devices
can be combined to function as a 32/36-bit or wider master/slave
dual-port static RAM. An M/S pin is provided for implementing
32/36-bit or wider memory applications without the need for sep-
arate master and slave devices or additional discrete logic. Ap-
plication areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port video/graphics
memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W),andoutputenable(OE).Twoflagsareprovided
on each port (BUSY and INT). BUSY signals that the port is trying to
access the same location currently being accessed by the other port.
The interrupt flag (INT) permits communication between ports or
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic powerdown feature iscontrolled independently on each port
by a chip select (CE) pin.
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V are available in 100-pin Thin Quad Plas-
tic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of t
SD
before the rising edge of
R/W to guarantee a valid write. A write operation is controlled by either
theR/Wpin(seeFigure 7)ortheCEpin(seeFigure 8).Requiredinputs
for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
DDD
after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
ACE
after CE or t
DOE
after OE is asserted. If
the userwishes toaccessa semaphoreflag,thenthe SEM pinmustbe
asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is
the mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027VN/027AV/037V/037AV,
FFFE for the CY7C028V/38V) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is
Pin Definitions
Left Port Right Port Description
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enable (CE is LOW when CE
0
≤V
IL
and CE
1
≥ V
IH
)
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
–A
15L
A
0R
–A
15R
Address (A
0
–A
14
for 32K; A
0
–A
15
for 64K devices)
I/O
0L
–I/O
17L
I/O
0R
–I/O
17R
Data Bus Input/Output (I/O
0
–I/O
15
for x16 devices; I/O
0
–I/O
17
for x18)
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select (I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices)
LB
L
LB
R
Lower Byte Select (I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices)
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S Master or Slave Select
V
CC
Power
GND Ground
NC No Connect
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 5 of 18
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Busy
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEsareassertedandanaddressmatchoccurswithint
PS
ofeachother,
the busy logic determines which port has access. If t
PS
is violated, one
port definitely gains permission to the location, but it is not predictable
whichportgetsthatpermission.BUSYisassertedt
BLA
afteranaddress
match or t
BLC
after CE is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring the
device as either a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This allows the device to
interface to a master device with no external components. Writing to
slave devices must be delayed until after the BUSY input has settled
(t
BLC
or t
BLA
), otherwise, the slave chip may begin a write cycle during
a contention situation. When tied HIGH, the M/S pin allows the device
tobeusedasamasterand,therefore,theBUSYlineisanoutput.BUSY
can then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V provide eight semaphore latches, which
are separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource,it setsalatchbywritingazeroto asemaphorelocation.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for t
SOP
before attempting to read the semaphore. The
semaphore value is availablet
SWRD
+ t
DOE
after the rising edge of the
semaphore write. If the left port was successful (reads a zero), it
assumes control of the shared resource, otherwise (reads a one) it
assumestherightporthascontrolandcontinuesto pollthesemaphore.
When the right side has relinquished control of the semaphore (by
writing a one), the left side succeeds in gaining control of the
semaphore. If the left side no longer requires the semaphore, a one is
written to cancel its request.
Semaphores are accessed by asserting SEMLOW. The SEM pin
functions as a chip select for the semaphore latches (CE must remain
HIGHduringSEMLOW).A
0–2
representsthesemaphoreaddress.OE
and R/W are used in the same manner as a normal memory access.
When writing or reading a semaphore, the other address pins have no
effect.
When writing to the semaphore, only I/O
0
isused.Ifazeroiswritten
to the left port of an available semaphore, a one appears at the same
semaphoreaddressontheright port.Thatsemaphorecannowonlybe
modified by the side showing zero (the left port in this case). If the left
port now relinquishes control by writing a one to the semaphore, the
semaphore is set to one for both sides. However, if the right port had
requestedthesemaphore(writtenazero)while theleftporthadcontrol,
theright portwouldimmediatelyown thesemaphoreas soonas theleft
port released it. Table 3 shows sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within t
SPS
of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which side
controls the semaphore.
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 6 of 18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .................................–65
° C to +150 ° C
Ambient Temperature with
Power Applied ............................................–55
° C to +125 ° C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State...........................–0.5V to V
CC
+0.5V
DC Input Voltage
[2]
..................................–0.5V to V
CC
+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 1100V
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0 ° C to +70 ° C 3.3V ±300 mV
Industrial
[3]
–40 ° C to +85 ° C 3.3V ±300 mV
Electrical Characteristics Over the Operating Range
Parameter Description CY7C027V/027VN/027AV/028V/CY7C037V/037AV/038V Unit-15 -20 -25
Min Typ Max Min Typ Max Min Typ Max
V
OH
Output HIGH Voltage
(V
CC
=Min., I
OH
= –4.0 mA) 2.4 2.4 2.4 V
V
OL
Output LOW Voltage (V
CC
=Min., I
OH
= +4.0 mA) 0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 2.2 2.2 V
V
IL
Input LOW Voltage 0.8 0.8 0.8 V
I
IX
Input Leakage Current −55−55−55μA
I
OZ
Output Leakage Current –10 10 –10 10 –10 10 μA
I
CC
Operating Current (V
CC
=Max. I
OUT
=0
mA) Outputs Disabled Com’l. 125 185 120 175 115 165 mA
Ind.
[3]
140 195 mA
I
SB1
Standby Current (Both Ports TTL
Level) CE
L
& CE
R
≥V
IH
, f=f
MAX
Com’l. 35 50 35 45 30 40 mA
Ind.
[3]
45 55 mA
I
SB2
Standby Current (One Port TTL Level)
CE
L
| CE
R
≥V
IH
, f=f
MAX
Com’l. 80 120 75 110 65 95 mA
Ind.
[3]
85 120 mA
I
SB3
Standby Current (Both Ports CMOS
Level) CE
L
& CE
R
≥V
CC
−0.2V, f=0 Com’l. 10 250 10 250 10 250 μA
Ind.
[3]
10 250 μA
I
SB4
Standby Current(OnePort CMOS Lev-
el) CE
L
| CE
R
≥V
IH
, f=f
MAX[4]
Com’l. 75 105 70 95 60 80 mA
Ind.
[3]
80 105 mA
Capacitance
[5]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25 ° C, f = 1 MHz,
V
CC
= 3.3V 10 pF
C
OUT
Output Capacitance 10 pF
Notes
2. Pulse width < 20 ns.
3. Industrial parts are available in CY7C028V and CY7C038V only.
4. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except outputenable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
SB3
.
5. Tested initially and after any design or process changes that may affect these parameters.
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 7 of 18
Figure 3. AC Test Loads and Waveforms
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
(a) Normal Load (Load 1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30pF
V
TH
=1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c)Three-State Delay(Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
R
TH
= 250Ω
≤≤
including scope and jig)
(Used for t
LZ
, t
HZ
, t
HZWE
, & t
LZWE
Switching Characteristics Over the Operating Range
[6]
Parameter Description
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V Unit
-15 -20 -25
Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 15 20 25 ns
t
AA
Address to Data Valid 15 20 25 ns
t
OHA
Output Hold From Address Change 3 3 3 ns
t
ACE[7]
CE LOW to Data Valid 15 20 25 ns
t
DOE
OE LOW to Data Valid 10 12 13 ns
t
LZOE[8, 9, 10]
OE LOW to Low Z 3 3 3 ns
t
HZOE[8, 9, 10]
OE HIGH to High Z 10 12 15 ns
t
LZCE[8, 9, 10]
CE LOW to Low Z 3 3 3 ns
t
HZCE[8, 9, 10]
CE HIGH to High Z 10 12 15 ns
t
PU[10]
CE LOW to Power Up 0 0 0 ns
t
PD[10]
CE HIGH to Power Down 15 20 25 ns
t
ABE[7]
Byte Enable Access Time 15 20 25 ns
Write Cycle
t
WC
Write Cycle Time 15 20 25 ns
t
SCE[7]
CE LOW to Write End 12 16 20 ns
t
AW
Address Valid to Write End 12 16 20 ns
t
HA
Address Hold From Write End 0 0 0 ns
t
SA[7]
Address Setup to Write Start 0 0 0 ns
t
PWE
Write Pulse Width 12 17 22 ns
t
SD
Data Setup to Write End 10 12 15 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputloading of the specified I
OI
/I
OH
and 30 pF load capacitance.
7. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
8. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
9. Test conditions used are Load 2.
10.This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Figure 11.
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 8 of 18
Data Retention Mode
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGHduring data retention, within
V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during
the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the mini-
mum operating voltage (3.0 volts).
t
HD
Data Hold From Write End 0 0 0 ns
t
HZWE[9, 10]
R/WLOW to High Z 10 12 15 ns
t
LZWE[9 ,10]
R/WHIGH to Low Z 3 3 3 ns
t
WDD[36]
Write Pulse to Data Delay 30 40 50 ns
t
DDD[36]
Write Data Valid to Read Data Valid 25 30 35 ns
Busy Timing
[11]
t
BLA
BUSY LOW from Address Match 15 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch 15 20 20 ns
t
BLC
BUSY LOW from CE LOW 15 20 20 ns
t
BHC
BUSY HIGH from CE HIGH 15 16 17 ns
t
PS
Port Setup for Priority 5 5 5 ns
t
WB
R/WHIGH after BUSY (Slave) 0 0 0 ns
t
WH
R/WHIGH after BUSY HIGH(Slave) 13 15 17 ns
t
BDD[13]
BUSY HIGH to Data Valid 15 20 25 ns
Interrupt Timing
[11]
t
INS
INT Set Time 15 20 20 ns
t
INR
INT Reset Time 15 20 20 ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OEor SEM)101012ns
t
SWRD
SEM Flag Write to Read Time 5 5 5 ns
t
SPS
SEM Flag Contention Window 5 5 5 ns
t
SAA
SEM Address Access Time 15 20 25 ns
Switching Characteristics Over the Operating Range
[6]
(continued)
Parameter Description
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V Unit
-15 -20 -25
Min Max Min Max Min Max
Timing
Parameter Test Conditions
[14]
Max Unit
ICC
DR1
At VCC
DR
= 2V 50 μA
Data Retention Mode
3.0V 3.0V
V
CC
> 2.0V
V
CC
to V
CC
–0.2V
V
CC
CE
t
RC
VIH
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
12.Test conditions used are Load 1.
13.t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
14.CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 9 of 18
Switching Waveforms
Notes
15.R/Wis HIGH for read cycles.
16.Device is continuously selected CE = V
IL
and UB or LB = V
IL
. This waveform cannot be used for semaphore reads.
17.OE = V
IL
.
18.Address valid prior to or coincident with CE transition LOW.
19.To access RAM, CE= V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATAVALID
DATA OUT
ADDRESS
t
OHA
Figure 4. Read Cycle No. 1 (Either Port Address Access)
[15, 16, 17]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
OE
CE and
LB or UB
CURRENT
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)
[15, 18, 19]
UB or LB
DATA OUT
t
RC
ADDRESS
t
AA
t
OHA
CE
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Figure 6. Read Cycle No. 3 (Either Port)
[15, 17, 18, 19]
[+] Feedback

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 10 of 18
Notes
20.R/Wmust be HIGH duringall address transitions.
21.A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
22.t
HA
is measured from the earlier of CEor R/W or (SEM or R/W) going HIGH at the end of write cycle.
23.If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be placed on
the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
PWE
.
24.To access RAM, CE= V
IL
, SEM = V
IH
.
25.To access upper byte, CE = V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE = V
IL
, LB = V
IL
, SEM = V
IH
.
26.Transition is measured ±500 mV from steadystate with a 5 pF load (including scope and jig).This parameter is sampled and not 100% tested.
27.During this period, the I/O pins are in the output state, and input signals must not be applied.
28.If the CEor SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Switching Waveforms (continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Figure 7. Write Cycle No. 1: R/W Controlled Timing
[20, 21, 22, 23]
[26]
[26]
[23]
[24,25]
NOTE 27 NOTE 27
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Figure 8. Write Cycle No. 2: CE Controlled Timing
[20, 21, 22, 28]
[24,25]
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